HIGH-SPEED DECODER FOR POLAR CODES
20200382136 ยท 2020-12-03
Assignee
Inventors
Cpc classification
International classification
Abstract
A high speed decoding algorithm that can decode all the information bits simultaneously at the same time, i.e., in parallel. The method of high speed decoding of polar codes includes the steps of transmitting data bits through a second part of communication channels, wherein a receiver is provided to set frozen bits as 0, apply Sc algorithm, and decode remaining bits in parallel.
Claims
1) A method of high speed decoding of polar codes comprising the steps of; the transmitting data bits through a second part of communication channels, wherein a receiver is provided to; For setting set frozen bits as 0 (first 512 bits); input N frame length and received bits, determine active frozen level, and let
2) The method of high speed decoding of polar codes according to claim 1; wherein all information bits are simultaneously decoded.
3) The method of high speed decoding of polar codes according to claim 1; wherein at the top node of the tree, a decision is made using:
4) The method of high speed decoding of polar codes according to claim 1; wherein the method comprises bitwise parallel decoding.
5) The method of high speed decoding of polar codes according to claim 1; wherein the method reduces latency and increases speed of decoding.
6) The method of high speed decoding of polar codes according to claim 1; wherein the method includes use of a second group containing remaining N/2 channels for data bits.
7) The method of high speed decoding of polar codes according to claim 1; wherein data bits are decoded in parallel without needing previously decoded bits.
8) The method of high speed decoding of polar codes according to claim 1; wherein the method includes F-type nodes characterized by not having bit-labels.
9) The method of high speed decoding of polar codes according to claim 1; wherein the method includes g-type nodes characterized by having bit-labels.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0032] The figures used to better explain developed with this invention and their descriptions are as follows:
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DETAILED DESCRIPTION OF THE EMBODIMENTS
[0042] Polar codes are a recently discovered family of capacity-achieving codes that are seen as a major breakthrough in coding theory. Polar codes are the first mathematically proven capacity achieving codes. The proposed high-speed decoding algorithm can decode all the information bits simultaneously at the same time, i.e., in parallel. Next, improved version of the proposed high speed decoding algorithm is introduced. The proposed high speed decoding approach and its improved version are simulated on computer environment and their BER performances are compared to that of the classical successive cancellation method.
[0043] The present invention has been described in detail in the following.
[0044] In this section, a novel high speed decoding technique for successive cancellation polar decoding is going to be demonstrated. A proposed High-speed decoder is based on original SC decoder which is limited by the bit by bit decoding strategy [1], [6]. Since the original SC decoder requires (2N2) cycles to output a codeword, the latency with large N is not suitable for real-time high-speed applications [6]. Therefore, the design of low-latency and high-speed polar decoders is a requirement for the employment of polar decoders in practical applications. Our proposed algorithm can decode N successive bits at the same time. Therefore, the latency can be reduced and speed can be increased.
[0045] The presented N-bit-decoding algorithm, able to decode N bits at the same time (in parallel), i.e., it can decode n.sup.th bit without a need to (n1) previously decoded bits. The estimated code word is denoted by .sub.1.sup.N=(.sub.1, . . . .sub.N). If u.sub.i is a frozen bit, then it's simply assigned .sub.i=0. Otherwise, the code bit can be determined by (2). In the next section, the proposed algorithm is explained in detail.
4. High-Speed Decoding Algorithm
[0046] Using the proposed code tree in
where i denotes the active level index. The g-nodes in active levels have labels 1 or 0. The distribution of the previously decoded bits to the nodes is illustrated in
where powers of 2 indicates the locations of g-type nodes. i.e., they indicate the active levels. From
[0047] After the first stage of the decoding operation, i.e., distribution of previously decoded bits to the nodes, the second stage of the decoding operation starts. In the second stage of the decoding operation LRs of the nodes in each level starting from bottom level to top level are calculated. In addition, during the LRs calculations (10) is used for f-type nodes and (11) is used for g-type nodes. F-type nodes do not have bit-labels; on the other hand g-type nodes have bit-labels. After calculating the likelihood of the top-node, the decision for the decoding of current bit is made according to
[0048] Since frozen bits are chosen as 0, likelihood calculation is not needed for frozen bits and they are automatically resolved as 0 and used for the decoding of next bit in decoding sequence.
5. High-Speed Decoding
[0049] For an N-bit information sequence, after channel splitting operation there are N new channels. For these N channels it is seen that most of the low capacity channels occurs in the first half, i.e., low capacity channels have indices 1, . . . , N/2. And most of the frozen bits are assigned to these low capacity channels. This is the main motivation of our study. Although some of the channels in the second half have low capacities, their number is few considering the total number of channels. For this reason, the first group containing N/2 channels dedicated to the frozen bits, and use the second group containing the rest of the N/2 channels for the data bits. This means that the decoding operation starts for the data bits transmitted through the second part of the communication channels.
[0050] When N/2 frozen bits are distributed on the tree, it is seen that N/2 nodes get 0 as node-bit. Besides, these N/2 nodes exist on the same level which is called as frozen level. When the bit distribution is performed for the decoding of consecutive data bits, it is seen that these N/2 nodes always contain 0s as node-bits, i.e., frozen level stay the same. And some levels depending on the order of the data bit to be decoded become active levels, and the nodes in these active levels either contain 0 or 1, and these nodes are nothing but g-type nodes. The likelihood ratio at these nodes can be calculated separately for node-bit 0 and node-bit 1 and the larger can be selected to be used for the nodes at upper levels. And this logic can be carried till the top level. In this way, there is no need to know the previously decoded bits, but just need to know the active and frozen levels.
[0051] The advantage of the mentioned method is that the active levels can be determined for the decoding of data bits and data bits can be decoded in a parallel manner without needing the previously decoded bits. Hence, if sufficient place can be found in an electronic device like FPGA it is possible to decode all the data bits in a concurrent manner. The algorithm explained can be outlined as in the chart Algorithm-1.
TABLE-US-00001 ALGORITHM1: HIGH-SPEED DECODING 1: INPUT N FRAME LENGTH AND RECEIVED BITS. 2: DETERMINE ACTIVE FROZEN LEVEL. 3:
6. Improved High-Speed Decoding
[0052] In order to improve performance of proposed high-speed decoder, a new decoding scheme called improved high-speed decoding technique is introduced. In this new approach some percent of the information bits are decoded using the classical successive cancellation method and the rest is of the bits are decoded at the same time using the proposed parallel decoding approach. With this approach aim is to increase the BER performance of the communication system. An example of the new approach is depicted in
[0053] Computer simulation is performed using the improved high decoding method employing the frame structure in
[0054] In
[0055] A high speed low latency decoding algorithm for polar codes, such that, using the proposed algorithm it is possible to decode all the information bits simultaneously in parallel, is shown. BER performance of polar codes under proposed high-speed decoding method over binary-erasure channels is obtained via computer simulations. From simulation results, it's obvious that proposed high-speed decoding algorithm shows good performance at high code rates, especially for the rates between 0.35 and 0.5. The proposed high-speed decoding algorithm gives a great improvement in polar codes decoding speed. For frame length N=1024 and rate=0.5, while original SC decoder can decode only one bit for a decoding stage, the proposed high-speed decoder can decode 512 bits all together at the same decoding stage and since in the proposed high-speed decoding algorithm there is no need to know the previously decoded bits. Next, it's suggested that an improved version of the proposed high speed decoding technique. The proposed improved high speed decoding method shows better performance than that of the classical successive cancellation decoding method at high rates with much lower decoding latency. In fact, originally for N=1024, at least 1024 clock cycles to decode whole sequence. However, only 257 (256 for SC decoding, 1 for proposed method) clock cycles are sufficient.
[0056] From the above detailed description, the method of high speed decoding of polar codes comprising the steps of; [0057] the data bits transmitted through the second part of the communication channels, [0058] In receiver part; [0059] For setting frozen bits as 0(first 512 bits); [0060] Input N frame length and received bits, [0061] Determine active frozen level, [0062] Let