CURRENT PHASE LOCKING AND DRIVER PULSE GENERATION METHOD USED IN WIRELESS CHARGING FOR ELECTRIC VEHICLES

Abstract

The present invention discloses a current phase locking and driver pulse generation method for wireless charging for electric vehicles. By monitoring the resonant current i.sub.L2 of the receiving coil, the proposed method generates the synchronization signal accurately based on the phase of the current i.sub.L2. Moreover, it controls the phases of driver pulses of switching transistors according to the synchronization signal so as to control the turn-on moment and turn-off moment of the switching transistors in the secondary rectifier. As a result, by using the proposed method, the pulse losing of the switching transistors in the secondary active rectifier can be avoided; the stable and reliable phase locking of the high-frequency resonant current and generation of driver pulses can be achieved; the anti-interference capability can be greatly enhanced, and the stability and reliability of the wireless charging system for electric vehicles can also be improved.

Claims

1. A current phase locking and driver pulse generation method used in wireless charging for electric vehicles comprising driver pulse generation and current phase locking; the driver pulse generation comprises: sampling the resonant current i.sub.L2 of the receiving coil in the wireless charging system by a high-frequency current transformer, and sending it to the signal processing unit; by the signal processing unit, converting the current signal from the high-frequency current transformer into a voltage signal with a dc bias, u.sub.c, and by a hysteresis comparator, processing the voltage signal u.sub.c to obtain the square waveform i.sub.L2 in phase with the secondary resonant current i.sub.L2; inputting the square waveform i.sub.L2 into a DSP processor, and using the rising edge of the square waveform i.sub.L2 as the synchronization signal S.sub.n1 of the PWM1 module in the DSP processor to initialize the phase of the counter CNT1 of the PWM1 module; all the counters CNT1, CNT2 and CNT3 operate in the down-count mode; when the counter CNT1 counts to 0, generating the synchronization signal S.sub.n2 of the PWM2 module in the DSP processor and by the synchronization signal S.sub.n2, initializing the phase of the counter CNT2 of the PWM2 module; when the counter CNT2 counts to 0, generating the synchronization signal S.sub.n3 of the PWM3 module in the DSP processor, and by the synchronization signal S.sub.n3, initializing the phase of the counter CNT3 of the PWM3 module, where the initial values of the counters CNT1, CNT2 and CNT3 are Pha1, Pha2 and Pha3, respectively; when the counter CNT2 counts to 0, the driver signal Q.sub.1 is set to the high level 1 in the PWM2 module, and the driver signal Q.sub.2 is set to the low level 0 in the PWM2 module; when the counter CNT2 counts to half of the maximum count value, the driver signal Q.sub.1 is set to the low level 0 in the PWM2 module, and the driver signal Q.sub.2 is set to the high level 1 in the PWM2 module; when the counter CNT3 counts to 0, the driver signal Q.sub.3 is set to the high level 1 in the PWM3 module, and the driver signal Q.sub.4 is set to the low level 0 in the PWM3 module; when the counter CNT3 counts to half of the maximum count value, the driver signal Q.sub.3 is set to the low level 0 in the PWM3 module, and the driver signal Q.sub.4 is set to the high level 1 in the PWM3 module; controlling the upper and the lower switching transistors of the leading leg of the active rectifier by the driver signal Q.sub.1 and the driver signal Q.sub.2, respectively; controlling the upper and the lower switching transistors of the lagging leg of the active rectifier by the driver signal Q.sub.3 and the driver signal Q.sub.4, respectively; the specific process of the current phase locking comprises: using the square waveform i.sub.L2 as the synchronization signal of the PWM1 module; using the S.sub.1A generated by the PWM1 module as the reference signal; locking the phase difference between the rising edge of i.sub.L2 and the rising edge of S.sub.1A by dual D-type flip-flops to generate the phase difference signal S.sub.ph; capturing the rising and falling edges of the phase difference signal S.sub.ph by the CAP module in the DSP processor to obtain the phase value .sub.hap; acquiring the precise phase value of the synchronization signal S.sub.n2 by the calibration unit, where *.sub.iref is the reference signal of the phase of S.sub.n2 and .sub.ifb is the phase feedback signal of S.sub.n2; based on *.sub.iref and .sub.ifb, calculating the initial value Pha1 of the counter CNT1 by the PID algorithm in the DSP processor; controlling the phase of S.sub.1A by adjusting the phase value .sub.C1 of the counter CNT1 to control the phase of the synchronization signal S.sub.n2.

2. The current phase locking and driver pulse generation method for wireless charging for electric vehicles according to claim 1, where the initial phase values of the counter CNT2 and the counter CNT3 are .sub.C2 and .sub.C3, respectively, where $\{\begin{array}{c}{}_{C.Math..Math.2}=\left(1-D_s\right).Math./2+\\ {}_{C.Math..Math.3}=D_s.Math.\end{array},$ is the phase difference between S.sub.n2 and the positive zero-crossing point of i.sub.z and D.sub.s is the phase shift angle of the active rectifier D.sub.s is changed according to the desired charging voltage and charging current to adjust .sub.C2 and .sub.C3; the PWM1 module generates the reference signal S.sub.1A; when the counter CNT1 in the PWM1 module counts to 0 naturally, S.sub.1A is set to the high level 1; when the counter CNT1 in the PWM1 module counts to half of the maximum count value naturally, S.sub.1A is set to the low level 0; meanwhile, the phase difference S.sub.ph between S.sub.n1 and S.sub.n2 is obtained by the dual D-type flip-flops; the CAP module in the DSP processor captures the phase difference S.sub.ph and acquires the phase value .sub.cap of S.sub.ph; according to .sub.i=.sub.s.sub.cap, the phase difference .sub.i, between the rising edge of S.sub.1A and the positive zero-crossing point of i.sub.z, can be calculated, where .sub.s is the hysteresis time-delay angle between the positive zero-crossing point of i.sub.L2 and the rising edge of i.sub.L2. .sub.i is controlled by the phase-locked loop to adjust the phase of the synchronization signal S.sub.n2.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIG. 1 is the schematic diagram of the phase locking of the secondary resonant current and control method of the system according to the present invention;

[0024] FIG. 2 is the schematic diagram of the driver pulse generation process in the chained trigger mode according to the present invention;

[0025] FIG. 3 shows the operating principle of the phase-locked loop according to the present invention;

[0026] FIG. 4 is the circuit diagram of dual D-type flip-flops of the phase-locked loop according to the present invention;

[0027] FIG. 5 is the control block diagram of the current phase-locked loop based on DSP28335 according to the present invention;

[0028] FIG. 6 is the zero-crossing point detection circuit diagram of the secondary resonant current i.sub.L2 according to the present invention;

[0029] FIG. 7 is the time-delay analytical diagram of the system according to the present invention;

[0030] FIG. 8 is the operating waveform diagram of the phase-locked loop with the input dc voltage V.sub.1=80V;

[0031] FIG. 9 is the operating waveform diagram of the driver signals with the input dc voltage V.sub.1=80V and the phase shift duty cycle D.sub.s=1;

[0032] FIG. 10a is the operating waveform diagram of the driver signals with the input dc voltage V.sub.1=80V and the phase shift duty cycle D.sub.s=0.8;

[0033] FIG. 10b is the operating waveform diagram of the driver signals with the input dc voltage V.sub.1=80V and the phase shift duty cycle D.sub.s=0.5;

DETAILED DESCRIPTION OF THE PRESENT INVENTION

[0034] The present invention will be further described below in detail with reference to the accompanying diagrams.

[0035] The current phase locking and driver pulse generation method in wireless charging for electric vehicles provided by the present invention includes the following steps.

[0036] The specific process of the driver pulse generation can be described as follows.

[0037] Referring to FIG. 1, the resonant current i.sub.L2 of the receiving coil can be sampled in the wireless charging system by a high-frequency current transformer and then the sampled results will be sent to the signal processing unit. By the signal processing unit, the current signal is converted from the high-frequency current transformer into a voltage signal with a dc bias, u.sub.c, and by a hysteresis comparator, the voltage signal u.sub.c is processed to obtain the square waveform i.sub.L2 in phase with the secondary resonant current i.sub.L2. Furthermore, the square waveform i.sub.L2 is input into the DSP processor, and the rising edge of the square waveform i.sub.L2 is used as the synchronization signal S.sub.n1 of the PWM1 module in the DSP processor to initialize the phase of the counter CNT1 of the PWM1 module.

[0038] Referring to FIG. 2, all the counters CNT1, CNT2 and CNT3 operate in the down-count mode. When the counter CNT1 counts to 0, the synchronization signal S.sub.n2 of the PWM2 module is generated in the DSP processor and by the synchronization signal S.sub.n2, the phase of the counter CNT2 of the PWM2 module is initialized. When the counter CNT2 counts to 0, the synchronization signal S.sub.n3 of the PWM3 module is generated in the DSP processor, and by the synchronization signal S.sub.n3, the phase of the counter CNT3 of the PWM3 module is initialized, where the initial values of the counters CNT1, CNT2 and CNT3 are Pha1, Pha2 and Pha3, respectively;

[0039] when the counter CNT2 counts to 0, the driver signal Q.sub.1 is set to the high level 1 in the PWM2 module, and the driver signal Q.sub.2 is set to the low level 0 in the PWM2 module. When the counter CNT2 counts to half of the maximum count value, the driver signal Q.sub.1 is set to the low level 0 in the PWM2 module, and the driver signal Q.sub.2 is set to the high level 1 in the PWM2 module. When the counter CNT3 counts to 0, the driver signal Q.sub.3 is set to the high level 1 in the PWM3 module, and the driver signal Q.sub.4 is set to the low level 0 in the PWM3 module. When the counter CNT3 counts to half of the maximum count value, the driver signal Q.sub.3 is set to the low level 0 in the PWM3 module, and the driver signal Q.sub.4 is set to the high level 1 in the PWM3 module. The upper and the lower switching transistors of the leading leg of the active rectifier are controlled by the driver signal Q.sub.1 and the driver signal Q.sub.2, respectively, and the upper and the lower switching transistors of the lagging leg of the active rectifier are controlled by the driver signal Q.sub.3 and the driver signal Q.sub.4, respectively.

[0040] The specific process of the current phase locking can be described as follows.

[0041] The square waveform i.sub.L2 can be used as the synchronization signal of the PWM1 module. The S.sub.1A generated by the PWM1 module can be used as the reference signal. The phase difference between the rising edge of i.sub.L2 and the rising edge of S.sub.1A can be locked by dual D-type flip-flops to generate the phase difference signal S.sub.ph. The rising and falling edges of the phase difference signal S.sub.n1 can be captured by the CAP module in the DSP28335 processor to obtain the phase value .sub.cap. The precise phase value of the synchronization signal S.sub.n2 can be acquired by the calibration unit, where *.sub.iref is the reference signal of the phase of S.sub.n2 and .sub.ifb is the phase feedback signal of S.sub.n2. Based on *.sub.iref and .sub.ifb, the initial value Pha1 of the counter CNT1 is calculated by the PID algorithm in the DSP28335 processor. The phase of S.sub.1A can be controlled by adjusting the phase value cod of the counter CNT1 to control the phase of the synchronization signal S.sub.n2.

[0042] Initial phase values of the counter CNT2 and the counter CNT3 are .sub.C2 and .sub.C3, respectively, where

[00002]$\{\begin{array}{c}{}_{C.Math..Math.2}=\left(1-D_s\right).Math./2+\\ {}_{C.Math..Math.3}=D_s.Math.\end{array},$

is the phase difference between S.sub.n2 and the positive zero-crossing point of i.sub.z and D.sub.s is the phase shift duty cycle of the active rectifier D.sub.s is changed according to the desired charging voltage and charging current to adjust .sub.C2 and .sub.C3.

[0043] The PWM1 module generates the reference signal S.sub.1A. When the counter CNT1 in the PWM1 module counts to 0 naturally, S.sub.1A is set to the high level 1. When the counter CNT1 in the PWM1 module counts to half of the maximum count value naturally, S.sub.1A is set to the low level 0. Meanwhile, the phase difference S.sub.ph between S.sub.n1 and S.sub.n2 is obtained by the dual D-type flip-flops. The CAP module in the DSP processor captures the phase difference S.sub.ph and acquires the phase value .sub.hap of S.sub.ph. According to .sub.i=.sub.s.sub.cap, the phase difference .sub.i between the rising edge of S.sub.1A and the positive zero-crossing point of i.sub.z, can be calculated, where .sub.s is the hysteresis time-delay angle between the positive zero-crossing point of i.sub.L2 and the rising edge of i.sub.L2. .sub.i is controlled by the phase-locked loop to adjust the phase of the synchronization signal S.sub.n2.

[0044] Referring to FIG. 3, in order to observe and control the phase of S.sub.n2, the PWM1 module generates the reference signal S.sub.1A. When the counter CNT1 in the PWM1 module counts to 0 naturally, the reference signal S.sub.1A generated by the PWM1 module is the high level 1. When the counter CNT1 counts to PRD/2 naturally, the reference signal S.sub.1A generated by the PWM1 module is the low level 0. Meanwhile, the phase difference S.sub.ph between S.sub.n1 and S.sub.n2 is obtained by the dual D-type flip-flops and used as the input signal, and the phase difference .sub.cap between S.sub.n1 and S.sub.n2 is obtained by the CAP module in the DSP, where .sub.i can be represented as:

.sub.i=.sub.s.sub.cap(2)

[0045] Where .sub.s is the time-delay angle between the positive zero-crossing point of i.sub.L2 and the rising edge of i.sub.L2. By controlling .sub.i in the phase-locked loop, the phase of the synchronization signal S.sub.n2 can be adjusted.

[0046] Referring to FIG. 4, the dual D-type flip-flops consist of two separate D type edge triggered flip-flops, the input signals are i.sub.L2 and S.sub.1A, and the output signal is S.sub.ph. The output signal has the same frequency as the input signals. The duty cycle represents the phase difference between the two input signals, which is .sub.cap in FIG. 3 in practice.

[0047] Referring to FIG. 5, the present invention is used to adjust the phase of the synchronization signal S.sub.n2. Firstly, the square waveform i.sub.L2 can be used as the synchronization signal of the PWM1 module. The S.sub.1A generated by the PWM1 module can be used as the reference signal. The phase difference between the rising edge of i.sub.L2 and the rising edge of S.sub.1A can be locked by dual D-type flip-flops to generate the phase difference signal S.sub.ph. The rising and falling edges of the phase difference signal S.sub.ph can be captured by the CAP module in the DSP28335 processor to obtain the phase value .sub.cap. The precise phase value of the synchronization signal S.sub.n2 can be acquired by the calibration unit with Formula (2), where *.sub.iref is the reference signal of the phase of S.sub.n2 and .sub.ifb is the phase feedback signal of S.sub.n2. Based on *.sub.iref and .sub.ifb, the initial value Pha1 of the counter CNT1 is calculated by the PID algorithm in the DSP28335 processor. The phase of S.sub.1A can be controlled by adjusting the phase value .sub.C1 of the counter CNT1 to control the phase of the synchronization signal S.sub.n2.

[0048] Referring to FIG. 6, i.sub.2s is the output signal of the current transformer and then converted into the voltage signal u.sub.s by the resistor R.sub.1. u.sub.c is obtained by adding the bias of 2.5V to u.sub.s. Next, u.sub.c is compared with the reference voltage 2.5V and then the corresponding square waveform i.sub.L2 is obtained by the hysteresis comparator.

[0049] Referring to FIG. 7, the time-delay analysis of the phase-locked loop proposed in the present invention is shown in the dashed box. The delay time of the phase-locked loop mainly includes two parts: the delay time t.sub.CT_SP of the current transformer and the signal processing unit and the delay time t.sub.HY of the hysteresis comparator. The delay time t.sub.CT_SP of the current transformer and the signal processing unit is hardly related to the parameters of the hardware circuit, which is approximately constant, and its corresponding phase time-delay angle is .sub.CT_SP. The actual physical meaning of the phase time-delay angle .sub.CT_SP is the phase difference between the ac component of u.sub.c and i.sub.L2, where the phase time-delay angle .sub.CT_SP is:

.sub.CT_SP=t.sub.CT_SPf.sub.s2(3).

[0050] The delay time t.sub.HY of the hysteresis comparator is related to the amplitude and frequency of the resonant current, and its corresponding phase time-delay angle is .sub.HY. The actual physical meaning of the delay time t.sub.HY is the phase difference between the rising edge of i.sub.L2 and the positive zero-crossing point of the ac component u.sub.c of u.sub.c. The delay time for the hysteresis comparator mainly includes two parts: the delay time t.sub.hyst determined by the characteristics of the hysteresis comparator itself and related to the amplitude and frequency of the input signal; the delay time t.sub.ac which is the action response delay time of the comparator and is determined by the device itself. Since the high-speed comparator is generally used in the practical system, this delay time t.sub.ac is approximately constant. Therefore, .sub.HY can be calculated as:

[00003]$\begin{array}{cc}{}_{H.Math.Y}=\arcsin \left(\frac{N_I.Math.R_3.Math.V_{\mathrm{ref}}}{\sqrt{2}.Math.I_{L.Math..Math.2}.Math.R_{\mathrm{fb}}}\right)+t_{a.Math.c}{f}_{s}2.Math.& \left(4\right)\end{array}$

where N.sub.1 is the ratio of the effective value of i.sub.L2 to the effective value of u.sub.c, I.sub.L2 is the effective value of the signal i.sub.L2, and V.sub.ref is the bias voltage. Therefore, by comprehensively considering all the delay time in the phase-locked loop, the corresponding phase difference is .sub.s, whose actual meaning is the phase difference between the rising edge of i.sub.L2 and the positive zero-crossing point of i.sub.L2. .sub.s is expressed as:

.sub.s=.sub.CT_SP+.sub.HY(5)

[0051] To describe the effectiveness of the present invention, the present invention is experimentally verified by the parameters listed in Table 1.

TABLE-US-00001 TABLE 1 Name Parameter Numerical value Unit Primary resonant coil L.sub.1 118.43 H Primary resonant capacitor C.sub.1 29.92 nF Secondary resonant coil L.sub.2 118.55 H Secondary resonant capacitor C.sub.2 29.88 nF Coupling coefficient k 0.2 / Load resistor R.sub.L 18

[0052] Referring to FIG. 8, by the phase locking method proposed in the present invention, the rising edge of S.sub.1A is located at the positive zero-crossing point of i.sub.z, and the falling edge of S.sub.1A leads the negative zero-crossing point of i.sub.z with t.sub.DT, where t.sub.DT is the preset dead time of driver pulses. With the calibration unit shown in Formula (2), when the amplitude of the resonant current is changed, the rising edge of the reference signal S.sub.1A always tracks the positive zero-crossing point of i.sub.z, and the falling edge of S.sub.1A leads the negative zero-crossing point of i.sub.z with 267 ns, i.e., t.sub.DT.

[0053] Referring to FIG. 9a, taking the synchronous rectification as an example, with the method proposed in the present invention, the driver signals Q.sub.1 and Q.sub.3 are generated, and the positive zero-crossing point of i.sub.z is exactly located at the middle point of the dead band, which is set to 267 ns.

[0054] Referring to FIGS. 9b and 9c, with the method proposed in the present invention, the phase of the driver pulses can be accurately controlled when the duty cycle D.sub.s of the rectifier is changed.

[0055] In conclusion, with the method proposed in the present invention, the accurate and stable control of the high-frequency active rectifier in the wireless charging system for electric vehicles can be realized. By acquiring the phase of the resonant current by the hysteresis comparator, the disturbance of the current near the zero-crossing point during the wireless charging process of electric vehicles can be effectively suppressed, and the reliability of the current phase locking method can be improved. The phase of the synchronization signal can be controlled accurately by the phase-locked loop, so that the phase of the driver pulses can be controlled accurately. In the chained trigger mode, the problem of the driver pulse losing can be avoided so that the stable and reliable operation of the active rectifier can be guaranteed. Specifically: 1) the accurate phase locking of the secondary high-frequency resonant current can be realized; 2) the driver pulses of the high-frequency rectifier can be stably generated, and the problem of the driver pulse losing can be avoided; 3) by introducing the hysteresis comparison in the current phase-locked loop, the wireless charging system for electric vehicles achieves sufficiently satisfying anti-interference performance.