Driver circuit for a buck converter, related integrated circuit, electronic buck converter and method

Abstract

An embodiment buck converter control circuit comprises an error amplifier configured to generate an error signal based on a feedback signal and a reference signal, a pulse generator circuit configured to generate a pulsed signal having switching cycles set to high and low as a function of the error signal, a driver circuit configured to generate a drive signal for an electronic switch of the buck converter as a function of the pulsed signal, a variable load, connected between two output terminals of the buck converter, configured to absorb a current based on a control signal, and a detector circuit configured to monitor a first signal indicative of an output current provided by the buck converter and a second signal indicative of a negative transient of the output current, and verify whether the second signal indicates a negative transient of the output current.

Claims

1. A control circuit, for a buck converter configured to provide via two output terminals an output voltage and an output current, the control circuit comprising: a first terminal configured to be connected to an electronic switch of the buck converter; a second terminal configured to receive a feedback signal indicative of the output voltage; two terminals configured to be connected to the two output terminals of the buck converter; an error amplifier configured to generate an error signal as a function of the feedback signal and a reference signal; a pulse generator circuit configured to generate a pulsed signal having switching cycles where the pulsed signal is set to high for a first duration and to low for a second duration, wherein the pulse generator circuit is configured to vary the first and/or the second duration as a function of the error signal; a driver circuit configured to generate a drive signal at the first terminal as a function of the pulsed signal; a variable load connected between the two terminals, wherein the variable load is configured to absorb a current determined as a function of a control signal; and a detector circuit configured to: monitor a first signal indicative of the output current, and a second signal indicative of a negative transient of the output current; verify whether the second signal indicates the negative transient of the output current; in response to the second signal not indicating the negative transient of the output current, store the monitored first signal; and in response to the second signal indicating the negative transient of the output current, generate the control signal as a function of a difference between the stored first signal and the monitored first signal.

2. The control circuit according to claim 1, wherein the pulse generator circuit is a pulse width modulator, and wherein the pulsed signal is a pulse width modulated signal having a constant frequency and a duty cycle determined as a function of the error signal.

3. The control circuit according to claim 1, wherein the error amplifier is a regulator having an integral and/or a proportional component.

4. The control circuit according to claim 3, wherein the error amplifier is the regulator having the integral component, and wherein the first signal corresponds to the error signal.

5. The control circuit according to claim 1, wherein the detector circuit comprises a transient detection circuit configured to determine the second signal by at least one of: verifying whether the first signal indicates that the output current decreases more than a first predetermined amount; verifying whether the feedback signal indicates that the output voltage increases more than a second predetermined amount; or verifying whether the feedback signal indicates that the output voltage exceeds a given maximum threshold value.

6. The control circuit according to claim 1, wherein the variable load comprises a current mirror receiving at an input the control signal, and wherein an output of the current mirror is connected between the two terminals.

7. The control circuit according to claim 1, wherein the detector circuit is configured to: verify whether the second signal indicates that the output current is stable; and in response to the second signal indicating that the output current is stable, gradually reduce the control signal, whereby the variable load absorbs gradually less current.

8. The control circuit according to claim 1, further comprising: a current ramp generator configured to generate a current ramp signal when the pulsed signal is set to high; a reference electronic switch, wherein the current ramp signal flows through the reference electronic switch when the pulsed signal is set to high; and a comparator circuit configured to compare a voltage at the reference electronic switch with a voltage at the electronic switch of the buck converter, wherein the comparator circuit is configured to set the pulsed signal to low, when the voltage at the electronic switch of the buck converter exceeds the voltage at the reference electronic switch.

9. The control circuit according to claim 1, wherein the control circuit is disposed on an integrated circuit.

10. A buck converter comprising: two input terminals configured to receive an input voltage; two output terminals configured to provide an output voltage and an output current; an electronic switch and a further electronic switch connected between the two input terminals, wherein an intermediate node between the electronic switch and the further electronic switch represents a switching node; an inductance connected between the switching node and a first output terminal of the two output terminals; a capacitor connected between the two output terminals; a feedback circuit configured to provide a feedback signal indicative of the output voltage; and a control circuit comprising: a first terminal connected to the electronic switch; a second terminal configured to receive the feedback signal indicative of the output voltage; an error amplifier configured to generate an error signal as a function of the feedback signal and a reference signal; a pulse generator circuit configured to generate a pulsed signal having switching cycles where the pulsed signal is set to high for a first duration and to low for a second duration, wherein the pulse generator circuit is configured to vary the first and/or the second duration as a function of the error signal; a driver circuit configured to generate a drive signal at the first terminal as a function of the pulsed signal; a variable load connected between the two output terminals, wherein the variable load is configured to absorb a current determined as a function of a control signal; and a detector circuit configured to: monitor a first signal indicative of the output current, and a second signal indicative of a negative transient of the output current; verify whether the second signal indicates the negative transient of the output current; in response to the second signal not indicating the negative transient of the output current, store the monitored first signal; and in response to the second signal indicating the negative transient of the output current, generate the control signal as a function of a difference between the stored first signal and the monitored first signal.

11. The buck converter according to claim 10, wherein the pulse generator circuit is a pulse width modulator, and wherein the pulsed signal is a pulse width modulated signal having a constant frequency and a duty cycle determined as a function of the error signal.

12. The buck converter according to claim 10, wherein the error amplifier is a regulator having an integral and/or a proportional component.

13. The buck converter according to claim 12, wherein the error amplifier is the regulator having the integral component, and wherein the first signal corresponds to the error signal.

14. The buck converter according to claim 10, wherein the detector circuit comprises a transient detection circuit configured to determine the second signal by at least one of: verifying whether the first signal indicates that the output current decreases more than a first predetermined amount; verifying whether the feedback signal indicates that the output voltage increases more than a second predetermined amount; or verifying whether the feedback signal indicates that the output voltage exceeds a given maximum threshold value.

15. The buck converter according to claim 10, wherein the variable load comprises a current mirror receiving at an input the control signal, and wherein an output of the current mirror is connected between the two output terminals.

16. The buck converter according to claim 10, wherein the detector circuit is configured to: verify whether the second signal indicates that the output current is stable; and in response to the second signal indicating that the output current is stable, gradually reduce the control signal, whereby the variable load absorbs gradually less current.

17. The buck converter according to claim 10, further comprising: a current ramp generator configured to generate a current ramp signal when the pulsed signal is set to high; a reference electronic switch, wherein the current ramp signal flows through the reference electronic switch when the pulsed signal is set to high; and a comparator circuit configured to compare a voltage at the reference electronic switch with a voltage at the electronic switch of the buck converter, wherein the comparator circuit is configured to set the pulsed signal to low, when the voltage at the electronic switch of the buck converter exceeds the voltage at the reference electronic switch.

18. The buck converter according to claim 10, wherein the buck converter is disposed on an integrated circuit.

19. A method of operating a buck converter configured to provide via two output terminals an output voltage and an output current, the method comprising: monitoring a first signal indicative of the output current, and a second signal indicative of a negative transient of the output current; verifying whether the second signal indicates the negative transient of the output current; in response to verifying that the second signal does not indicate the negative transient of the output current, storing the monitored first signal; repeating the monitoring and the verifying; in response to verifying that the second signal indicates the negative transient of the output current, generating a control signal as a function of a difference between the stored first signal and the monitored first signal; and driving a variable load connected between the two output terminals as a function of the control signal.

20. The method according to claim 19, further comprising determining the second signal by at least one of: verifying whether the first signal indicates that the output current decreases more than a first predetermined amount; verifying whether a feedback signal indicates that the output voltage increases more than a second predetermined amount; or verifying whether the feedback signal indicates that the output voltage exceeds a given maximum threshold value.

21. The method according to claim 19, further comprising: verifying whether the second signal indicates that the output current is stable; and in response to the second signal indicating that the output current is stable, gradually reducing the control signal, whereby the variable load absorbs gradually less current.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The embodiments of the present disclosure will now be described with reference to the annexed plates of drawings, which are provided purely to way of non-limiting example and in which:

(2) The features and advantages of the present invention will become apparent from the following detailed description of practical embodiments thereof, shown by way of non-limiting example in the accompanying drawings, in which:

(3) FIG. 1 shows a typical application of an electronic converter;

(4) FIG. 2 shows an example of a buck converter;

(5) FIG. 3 shows exemplary waveforms of the converter of FIG. 2;

(6) FIG. 4 shows an embodiment of a control circuit for a buck converter;

(7) FIG. 5 shows an embodiment of a pulse generator circuit for the control circuit of FIG. 4;

(8) FIG. 6 shows an embodiment of a buck converter comprising a detector circuit and a variable load;

(9) FIG. 7 shows an embodiment of the operation of the buck converter of FIG. 6;

(10) FIG. 8 shows a first embodiment the detector circuit and the variable load of FIG. 6;

(11) FIG. 9 shows a second embodiment the detector circuit and the variable load of FIG. 6; and

(12) FIGS. 10 and 11 show embodiments of a current limiter for the high side switch of the buck converter of FIG. 6.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(13) In the ensuing description, various specific details are illustrated aimed at enabling an in-depth understanding of the embodiments. The embodiments may be provided without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail so that various aspects of the embodiments will not be obscured.

(14) Reference to “an embodiment” or “one embodiment” in the framework of this description is meant to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment”, “in one embodiment”, or the like that may be present in various points of this description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

(15) The references used herein are only provided for convenience and hence do not define the sphere of protection or the scope of the embodiments.

(16) In FIGS. 4 to 11 described below, parts, elements or components that have already been described with reference to FIGS. 1 to 3 are designated by the same references used previously in these figures. The description of these elements has already been made and will not be repeated in what follows in order not to burden the present detailed description.

(17) As explained in the foregoing, various embodiments of the present description relate to a control circuit 22a for a buck converter.

(18) FIG. 4 shows a first embodiment of a control circuit 22a for a buck converter. For a general description of a buck converter 20, reference may be made to the description of FIGS. 1 to 3. Specifically, as described in the foregoing, a buck converter 20 comprises: two input terminals 200a and 200b for receiving an input voltage V.sub.in, two output terminals 202a and 202b for providing an output voltage V.sub.out; two electronic switches Q1 and Q2, such as NMOS (wherein the electronic switch Q2 may also be a diode), connected in series between the terminals 200a and 200b, wherein the intermediate node represents a switching node Lx; an inductance L, such as an inductor, connected between the switching node Lx and the output terminal 202a; a capacitor Cout connected between the two output terminals; a feedback circuit 24, corresponding to a voltage measurement circuit, configured to generate a signal indicative of the output voltage V.sub.out; and a control circuit 22a configured to generate the drive signals for the electronic switch Q1 and optionally the electronic switch Q2 as a function of the feedback signal FB.

(19) As shown in FIG. 4, in various embodiments, such a control circuit 22a may be implemented in an integrated circuit 40, e.g. the integrated circuit 40 may comprise: a pad (of a respective die) or pin (of a respective integrated circuit package) configured to be connected to the feedback circuit 24, such as a voltage divider comprising two or more resistors R1 and R2 connected in series between the output terminals 202a and 202b, whereby the feedback signal FB is a voltage proportion to the output voltage V.sub.out; a pad/pin for providing the drive signal DRV.sub.1 to the electronic switch Q1 and optionally a pad/pin for providing the drive signal DRV.sub.2 to the electronic switch Q2, e.g. to the gate terminals of respective FETs; and the control circuit 22a.

(20) As shown in FIG. 3, in various embodiments, the integrated circuit 40 may also comprise the electronic switch Q1 and optionally the electronic switch (or diode) Q2. For example, in this case, the two pads/pins for providing the drive signal DRV.sub.1 and DRV.sub.2 may be omitted and the integrated circuit may comprise pads/pins for connection to the terminals 200a, 200b and Lx. In various embodiments, the integrated circuit may in any case be connected to the terminals 200a/200b insofar as these terminals may be used to provide the power supply to the control circuit 22a. Alternatively, the power supply for the control circuit 22a may be obtained, e.g., from the input voltage V.sub.in (terminals 200a/200b) or the output voltage V.sub.out (terminals 202a/202b).

(21) In various embodiments, the integrated circuit 40 may also comprises the feedback circuit/voltage measurement circuit 24. In this case, the feedback pad/pin may be omitted and the integrated circuit 40 may comprise two pins/pads for connection to the terminals 202a and 202b. As mentioned before, the integrated circuit 40 may already be connected to the terminal 202b and accordingly the pin/pad for the terminal 202b may be omitted.

(22) Thus, irrespective of the integration of the various blocks in the integrated circuit 40, the control circuit 22a comprises: a terminal/node for receiving the feedback signal FB indicative of (and preferably proportional to) the output voltage V.sub.out; and a terminal/node for providing the drive signal DRV.sub.1 and optionally a terminal/node for providing the drive signal DRV.sub.2.

(23) Specifically, in the embodiment considered, the control circuit 22a comprises an error amplifier configured to generate an error signal V.sub.comp, by comparing the feedback signal FB with a reference signal, such as a reference voltage V.sub.ref.

(24) For example, in the embodiment considered, the error amplifier is implemented with an operational amplifier 202 and a compensation/feedback network 204 associated with the operational amplifier 202. For example, in the embodiment considered, the feedback signal FB is connected to the inverting/negative input of the operational amplifier 202 and the reference voltage V.sub.ref is connected to the non-inverting/positive input terminal of the operational amplifier 202.

(25) In various embodiments, the compensation network 204 is connected between the output of the operational amplifier 202 and the feedback terminal (e.g. the inverting input of the operational amplifier 202) and/or ground GND, which as mentioned before may correspond to the terminal 200b and/or 202b.

(26) For example, in the embodiment considered, the compensation network 204 comprises at least one capacitor Cc (integral component) and/or at least one resistor Rc (proportional component). For example, in the embodiment considered, a resistor Rc and a capacitor Cc are connected in series between the feedback terminal and the output of the operational amplifier 202. Specifically, in the embodiment considered, the operational amplifier 202 provides a current i.sub.comp as a function of the difference between the reference voltage V %/and the feedback signal FB, and the compensation network 204, e.g. via the resistor Rc and/or the capacitor Cc, is configured to convert the current i.sub.comp into the error signal/voltage V.sub.comp.

(27) In general, the compensation network 204 may be integrated in or may be external to the integrated circuit 40. For example, in the embodiment considered, the integrated circuit 40 comprises a pin/pad COMP connected to the output of the operational amplifier 202, and the compensation network 204 may be connected (e.g. externally) between the pin/pad COMP and ground GND.

(28) Accordingly, in various embodiments, the error amplifier 202/204 may be configured as regulator comprising an I (Integral) and/or a P (Proportional) component.

(29) In the embodiment considered, the error signal V.sub.comp is provided to a pulse generator circuit 208, such as a PWM generator circuit, configured to generate a binary/pulsed signal DRV which is alternatively set to a first logic level (e.g. high) and a second logic level (e.g. low) for respective durations T.sub.1 and T.sub.2. Specifically, the pulse generator circuit 208 is configured to vary at least one of the durations T.sub.1 and T.sub.2 as a function of the error signal V.sub.comp.

(30) In the embodiment considered, the binary/pulsed signal DRV is provided to a driver circuit 210 configured to generate the drive signal DRV.sub.1 and DRV.sub.2 as a function of the drive signal DRV. For example, in various embodiments, the driver circuit 210 may be configured to: set the signal DRV.sub.1 to high when the signal DRV has the first logic level and to low when the signal DRV has the second logic level; and optionally set the signal DRV.sub.2 to high when the signal DRV has the second logic level and to low when the signal DRV has the first logic level.

(31) Accordingly, in various embodiments the switch-on and switch-off durations Tom and T.sub.OFF1 correspond to the durations T.sub.1 and T.sub.2, respectively. For example, the logic levels of the signal DRV.sub.1 may correspond to the logic levels of the signal DRV.sub.1 and optionally the logic levels of the signal DRV.sub.2 may correspond to the inverted version of the logic levels of the signal DRV.

(32) Accordingly, essentially, the feedback loop via the feedback circuit 24 and the error amplifier 202/204 varies the error signal V.sub.comp, which in turn is used by the pulse generator circuit 208 to drive via the driver circuit 210 the electronic switches Q1 and Q2, thereby regulating the output voltage V.sub.out to a requested value, which may be determined, e.g., as a function of the scaling factor of the feedback circuit 24 and the reference voltage V.sub.ref.

(33) In various embodiments, the reference voltage V.sub.ref may also be provided by a soft-start circuit 206 configured to increase, in response to a power-on of the control circuit 22a, the reference voltage V.sub.ref from a minimum value (e.g. 0 V) to a maximum value (corresponding to the nominal value of the reference voltage V.sub.ref).

(34) FIG. 5 shows a possible embodiment of the pulse generator circuit 208. For example, in the embodiment considered, the pulse generator circuit 208 is a fixed frequency PWM generator circuit, i.e. the signal DRV has a constant switching frequency (T.sub.SW=T.sub.1+T.sub.2) and a variable duty cycle (D=T.sub.1/T.sub.SW).

(35) For example, in the embodiment considered, the error signal V.sub.comp is provided to an input (e.g. the positive input terminal) of a comparator 2080 configured to determine whether the error signal V.sub.comp is smaller or greater than a threshold value V.sub.th.

(36) Specifically, in the embodiment considered, the signal at the output of the comparator 2080 is fed to a flip-flop 2082 configured to set the signal DRV to: high with the rising edge (or alternatively the falling edge) of a clock signal CLK; and low when the error signal V.sub.comp reaches or exceeds the threshold value V.sub.th.

(37) For example, in the embodiment considered, the flip-flop 2082 is a D type flip-flop receiving: at a clock input the clock signal CLK; at a data input the logic value high (“1”); and at a reset input the signal provided by the comparator 2080.

(38) Thus, in the embodiment considered, the signal DRV is set to high with a fixed frequency (determined by the clock signal CLK) and then set to low when the signal V.sub.comp reaches or exceeds the threshold value V.sub.th.

(39) Generally, the embodiment shown in FIG. 5 may also be adapted to support an over-voltage protection and/or burst mode. Specifically, by using an additional comparator configured to determine whether the feedback signal FB exceeds a given maximum threshold value, the flip-flop 2082 may receive a masked version of the clock signal CLK, whereby: when the feedback signal FB is smaller than the maximum threshold, the flip-flop 2082 is periodically set via the clock signal CLK; and when the feedback signal FB is greater than the maximum threshold, the clock signal CLK is masked and the flip-flop 2082 remains reset.

(40) As mentioned before, various embodiments of the present disclosure relate to solutions, which permit to limit the overshoot of the output voltage V.sub.out, when the output current i.sub.out varies rapidly.

(41) For example, in the control circuit 22a shown in FIG. 4 there will be intrinsic delays (e.g. due to the operational amplifier 202, the compensation network and the pulse generator circuit 208, e.g. the comparator 2080) in the regulation loop, which usually cannot ensure that the output voltage V.sub.out does not increase significantly, e.g. because there may still be stored energy in the inductance L or the error signal V.sub.comp will not follow immediately the load variation.

(42) FIG. 6 shows an embodiment of a modified buck converter 20a, and in particular a modified control circuit 22a. Specifically, also in this case, the control circuit 22a comprises: a terminal configured to be connected to a feedback circuit 24 configured to generate a feedback FB as a function of the output voltage V.sub.out; an error amplifier 212 configured to generate an error signal V.sub.comp as a function of the feedback FB, wherein the error amplifier 212 may comprise the operational amplifier 202, the compensation network 204 and optionally the soft-start circuit 206 of FIG. 4; a pulse generator circuit 208 configured to generate a pulsed signal DRV; and a driver circuit 210 configured to generate the drive signal DRV.sub.1 and optionally the drive signal DRV.sub.2 as a function of the signal DRV.

(43) Accordingly, these blocks are configured to regulate during normal operation the output voltage V.sub.out to a given requested value.

(44) In the embodiment considered, the control circuit 22a comprises a variable load 216 configured to absorb a current i.sub.F as a function of the control signal CTR and a detector circuit 214 configured to generate the control signal CTR (at least) as a function of a signal being indicative of the output current i.sub.out.

(45) FIG. 7 shows an embodiment of the operation of the detector circuit 214. In the embodiment considered, after a start step 1000, the detector circuit 214 monitors at a step 1002 the signal being indicative of the output current i.sub.out provided via the output terminals 202a and 202b. For example, the signal being indicative of the output current i.sub.out may be a current sense signal CS provided by a current sensor 218, such as a shunt resistor, connected in series with the output terminals 202a and 202b. Alternatively, in case the compensation network 204 comprises a capacitor Cc, whereby the error signal V.sub.comp is proportional to (or at least indicative of) the output current i.sub.out, the signal being indicative of the output current i.sub.out may correspond to the error signal V.sub.comp.

(46) At a following step 1004, the detector circuit 214 stores the signal being indicative of the output current i.sub.out. For example, the detector circuit 214 may store the signal being indicative of the output current i.sub.out periodically or in response to given events.

(47) At a following step 1006, the detector circuit 214 verifies whether a negative transition of the output current occurs. For example, for this purpose, the detector circuit 214 may verify at least one of the following conditions: verify whether the signal being indicative of the output current i.sub.out (e.g. the signal V.sub.comp) indicates that the output current i.sub.out decreases more than a given amount (relative variation), e.g. by comparing the current value of the signal being indicative of the output current i.sub.out with a respective stored value; verify whether the feedback signal FB indicates that the output voltage V.sub.out increases more than a given amount (relative variation), e.g. by comparing the current value of the feedback signal FB with a respective stored value; or verify whether the feedback signal FB indicates that the output voltage V.sub.out exceeds a given maximum threshold value (absolute value).

(48) In case no negative transient of the output current is detected (output “N” of the verification step 1006), the detector circuit 214 may return to the step 1002 for performing a new monitoring operation.

(49) Conversely, in case a negative transition of the output current is detected (output “Y” of the verification step 1006), the detector circuit 214 proceeds to a step 1008, where the detector circuit 214 generates the control signal CTR. Specifically, in various embodiments, the control signal CTR is indicative of the difference between the stored signal and the current value of the signal being indicative of the output current i.sub.out. Accordingly, when the converter 20a provides a given output current i.sub.out,1 and the output current is reduce to a value i.sub.out,2, the detector circuit 214 drives the variable load 216 via the signal CTR in order to absorb a current i.sub.F=i.sub.out,1−i.sub.out,2, whereby the total current i.sub.out′=i.sub.F+i.sub.out,1 provided by the capacitor Cout remains constant.

(50) The step 1006 is thus purely optional, because when the monitored signal corresponds to the stored signal (static condition), also the signal CTR would indicate that the difference is zero and the variable load 216 would absorb a current I.sub.F=0.

(51) In various embodiments, the detector circuit 214 proceeds then to a verification step 1010, where the detector circuit 214 verifies whether the output current i.sub.out remains stable. For example, for this purpose, the detector circuit 214 may verify at least one of the following conditions: verify whether the signal being indicative of the output current i.sub.out (e.g. the signal V.sub.comp) indicates that the output current i.sub.out varies less than a given amount (relative variation), e.g. by comparing the current value of the signal being indicative of the output current i.sub.out with a respective stored value; verify whether the feedback signal FB indicates that the output voltage V.sub.out varies less than a given amount (relative variation), e.g. by comparing the current value of the feedback signal FB with a respective stored value; or verify whether the feedback signal FB indicates that the output voltage V.sub.out is below a given maximum threshold value (absolute value).

(52) In case the output current i.sub.out is not stable (output “N” of the verification step 1010), the detector circuit returns to the step 1008.

(53) Conversely, in case the output current i.sub.out is stable (output “Y” of the verification step 1010), the detector circuit 214 may reduce (preferably gradually and slowly) the control signal CTR, e.g. by reducing the stored value, whereby the variable load 216 absorbs less current i.sub.F and the feedback loop regulated the output voltage V.sub.out as a function of the new load condition. However, insofar as the detector circuit 214 is configured to vary the control signal CTR with a time constant being greater than the time constant of the feedback loop, the feedback loop is able to follow the load variation without overshoots in the output voltage V.sub.out.

(54) Accordingly, once the detector circuit 214 has reduced the current i.sub.F to zero via the control signal CTR, the detector circuit 214 may return to the step 1002 for detecting a following load transition.

(55) Accordingly, in various embodiments, the detector circuit 214 is configured to track the output current load and sample its value. This sampled value is used to apply an internal current load i.sub.F to the output terminals 202a and 202b in order to replace the reduction of the external load current. Next, the detector circuit 214 may decrease the internal current load i.sub.F with a controlled slope minimizing overshoot.

(56) FIG. 8 shows a possible embodiment of the detector circuit 214 and the variable load 216. Specifically, in the embodiment considered, the signal being indicative of the output current i.sub.out corresponds to the error signal V.sub.comp. However also the current sense signal CS may be used.

(57) In the embodiment considered, the error signal V.sub.comp is provided to an analog sample-and-hold circuit 2140. For example, such a sample-and-hold circuit 2140 may be implemented with a storage capacitor Cs and an electronic switch SW1 configured to connect the storage capacitor Cs to the error signal V.sub.comp.

(58) In the embodiment considered, the sample-and-hold circuit 2140, e.g. the electronic switch SW1, is controlled by a negative transient detection circuit 2142. For example, this circuit may be configured to: enable storage of the error signal V.sub.comp (e.g. close the electronic switch SW1) when no negative load transient is detected; and disable storage of the error signal V.sub.comp (e.g. open the electronic switch SW1) when a negative load transient is detected.

(59) For example, as described in the foregoing, the negative transient detection circuit 2142 may monitor for this purpose the variation or absolute value of the feedback signal FB, or the variation of the current sense signal CS. For example, such transients may be detected by determining the variation of a respective signal by comparing the signal with a previous value of the signal (e.g. stored via a sample-and-hold circuit, e.g. 2140) or via a derivative network.

(60) In the embodiment considered, the detector circuit 214 comprises a first current generator M1/M2/M3 configured to generate a current 2, proportional to the stored error signal V.sub.comp. Specifically, in the embodiments, the stored error signal V.sub.comp is provided to a variable current generator M1, e.g. implemented with a FET, e.g. an n-channel FET, and a resistor Ra, configured to provide a current i.sub.S proportional to the stored error signal V.sub.comp. In various embodiments, the current i.sub.S is provided also at input to a current mirror M2/M3, e.g. implemented with two FETs, such as p-channel FET, thereby providing at an output of the current mirror M2/M3 the current i.sub.1, which is applied to a node 2144.

(61) Similarly, in the embodiment considered, the detector circuit 214 comprises a second variable current generator M4, e.g. implemented with a FET, e.g. an n-channel FET, and a resistor Rb, configured to generate a current i.sub.2 proportional to the current error signal V.sub.comp.

(62) Specifically, also the current generator M4 is connected to the node 2144, whereby the node 2144 provides a current i.sub.3 corresponding to the difference between the current 2, and the current i.sub.2, i.e. i.sub.3=i.sub.1−i.sub.2.

(63) Accordingly, in the embodiment considered, the current i.sub.3 corresponds to the control signal CTR being indicative of the difference between the stored and current value of the signal being indicative of the output current i.sub.out.

(64) For example, in the embodiment considered, the variable load 216 is implemented with a current mirror M5/M6, e.g. implemented with two FETs, such as n-channel FET, wherein the input (M5) of the current mirror receives the current i.sub.3 and the output (M6) of the current mirror, which thus provides a current i.sub.F proportional to the current i.sub.3, is connected between the terminals 202a and 202b.

(65) Accordingly, by adjusting the gain of the various current generators and current mirrors, the proportionally between the current i.sub.F and the variation of the output current i.sub.out may be set, e.g. in order to reproduce (approximately) the same proportionally between the error signal V.sub.comp and the average current I.sub.L provided by the inductance L in response to the respective switching of the switches Q1 and Q2 generated via the blocks 208 and 210.

(66) FIG. 9 shows a second embodiment of the detector circuit 214 and the variable load 216. Specifically, as mentioned before, the detector circuit 214 may be configured to reduce the signal CTR when the output load is static (step 1012).

(67) For example, in the embodiment considered, the detector circuit 214 comprises for this purpose a discharge circuit 2146 configured to selectively discharge the capacitor Cs. For example, in FIG. 9, the discharge circuit 2146 comprises an electronic switch SW2 and a current source 2148 connected in series between the output of the sample-and-hold circuit 2140/input of the variable current generator M1/Ra and ground GND. For example, also the electronic switch SW2 may be driven via the control circuit 2142.

(68) In various embodiments, the detector circuit and/or the variable load 216 may be configured to be selectively enabled via an enable circuit 2150. For example, in the embodiment considered, the enable circuit 2150 is implemented with an electronic switch S3 connected between the node 2144, i.e. the output of the detector circuit 214/the input of the variable load 216, and ground GND. For example, also the electronic switch SW3 may be driven via the control circuit 2142.

(69) Accordingly, in various embodiments the control circuit 2142 may be configured to monitor whether a negative transient of the output current i.sub.out occurs, and: during a normal operation (in the absence of a negative transient, e.g. the negative variations is below a given threshold), close the electronic switch SW1 (i.e. enable storage of the sample-and-hold circuit 2140) and the electronic switch SW3 (i.e. disable the variable load 216), and open the electronic switch SW2 (i.e. progressive reduction of the control signal CTR is disabled), thereby following the output current and keeping off the variable load 216, which in various embodiments corresponds to an active pull down; once a negative transient current load is detected (e.g. a negative variation exceeds a given threshold), open the electronic switch SW1 (i.e. maintain the value stored by the sample-and-hold circuit 2140) and open the electronic switch SW3 (i.e. enable the variable load 216), whereby the current U is linked to the stored output current and i.sub.2 to the current output current, and the current i.sub.F is proportional to the difference between these currents, i.e. i.sub.F=K(i.sub.1−i.sub.2), where K represents a gain factor; and once a new static condition is detected (in the absence of a transients, e.g. the variations are below a given threshold), close the electronic switch SW2, thereby reducing gradually the control signal CTR.

(70) FIG. 10 shows an embodiment of an over-current protection circuit for the (high-side) electronic switch Q1. Specifically, as shown in FIG. 3, the current I.sub.Q1 flowing through the electronic switch Q1 has a substantially linear behavior during the switch-on duration T.sub.ON1, wherein the current increases from a minimum value at the instant h to a maximum value at the instant t.sub.2. In the embodiment shown in FIG. 10, the circuit 50 is thus configured to generate a reference current i.sub.R having a similar behavior, i.e. the circuit 50 is configured to generate a reference current i.sub.R which increases linearly during the switch-on duration T.sub.ON1 from a minimum value at the instant U to a maximum value at the instant t.sub.2, i.e. during the period when the signal DRV is set to high.

(71) For example, in the embodiment considered, the circuit 50 comprises a ramp current generator 502,504 configured to generate a current ramp signal i.sub.Ramp as a function of the pulsed signal DRV. For example, in the embodiment considered, the ramp current generator 502, 504 comprises: a voltage ramp generator 502 configured to generate a ramp signal which is set to zero when the signal DRV is low, and then increased linearly when the signal DRV is high; and a variable current generator 504 configured to generate the current i.sub.Ramp as a function of the voltage ramp signal provided by the voltage ramp generator 502.

(72) In various embodiments, the ramp current i.sub.Ramp is provided to a node 520.

(73) Specifically, in various embodiments, the node 520 is also connected to a current generator 506 providing a constant offset current i.sub.Offset.

(74) In various embodiments, the node 520 is also connected to a further current generator 508 configured to determine a current i.sub.c as a function of the signal V.sub.comp, wherein the current i.sub.c is preferably proportional to the signal V.sub.comp. Specifically, in various embodiments, the current generator 508 uses a low-pass filtered version of the voltage V.sub.comp as determined e.g. via a low-pass filter 508.

(75) Accordingly, in various embodiments, the current i.sub.4 corresponds to:
i.sub.4=i.sub.c−i.sub.Off−i.sub.Ramp

(76) Accordingly, in various embodiments, the current i.sub.4 corresponds to a decreasing ramp signal.

(77) In the embodiment considered, the current i.sub.4 is then provided to a current limiter circuit 512 configured to generate the current i.sub.R by limiting the current i.sub.4 to a given maximum Value i.sub.max.

(78) As shown in FIG. 10, in various embodiments, the current i.sub.4 may be provided to the current limiter circuit 512 indirectly by generating a current i.sub.5 via a current mirror M7, M8, e.g. implemented with PMOS transistors.

(79) For example, FIG. 11 shows an embodiment of the current limiter circuit 512. Specifically, in the embodiment considered, the current limiter 512 is implemented with a Wilson current mirror, comprising three transistors, such as NMOS.

(80) Specifically, in the embodiment considered, the Wilson current mirror comprises: a first branch comprising a transistor M9 receiving the current i.sub.4 or i.sub.5; a second branch comprising two transistors M11 and M10 connected in series, wherein the gate terminal of the transistor M11 is connected to the drain terminal of the transistor M9, the drain terminal of the transistor M10 is connected to the source terminal of the transistor M11, and the gate and source terminals of the transistor M10 are connected to the gate and source terminals of the transistor M9, respectively.

(81) In various embodiments, a current limiter 518 may thus be connected in series with the second branch, thereby limiting the current flowing through the second branch to a maximum value i.sub.max.

(82) In the embodiment considered, a current mirror M10, M12 may then be used to generate the current in by mirroring the current flowing through the second branch.

(83) Accordingly, in various embodiments, the current i.sub.R corresponds to the current i.sub.4 when i.sub.4<i.sub.max and i.sub.max when i.sub.4>i.sub.max.

(84) In the embodiment considered, the reference current is provided to a reference transistor QR, preferably corresponding to a scaled version of the transistor Q1. For example, in the embodiment considered, the reference transistor QR is an n-channel FET, e.g. a NMOS, wherein the drain terminal is connected to the terminal 200a, the source terminal is connected to the reference current i.sub.R, and the gate terminal is connected to the drive signal DRV.sub.1. Specifically, by using a scaled version of the transistor Q1, also the reference current i.sub.R may be a scaled version of the expected current profile of the current I.sub.Q1.

(85) Thus, by comparing the currents flowing through the transistors Q1 and QR or the voltage at the transistors Q1 and QR, the circuit 50 may detect whether the current I.sub.Q1 remains below the limit indicated by the reference current i.sub.R. For example, in various embodiments, the voltage at the source terminals of the transistors Q1 and QR are fed to a comparator 514 configured to generate a signal OC indicating that the current flowing through the transistor Q1 exceeds the limit indicated by the current i.sub.R. For example, in this case, the transistor Q1 may be opened. For example, in the embodiment considered, the signal OC is fed via an OR gate (also receiving the signal provided by the comparator 2080) to the reset input of the flip-flop 2082.

(86) Of course, without prejudice to the principle of the invention, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present invention, as defined by the ensuing claims.