Extended hold-off time for SPAD quench assistance

Abstract

A single photon avalanche diode (SPAD) has a cathode coupled to a high voltage supply and an anode coupled to a first node. A photodetection circuit includes: a first n-channel transistor having a drain coupled to the first node, a source coupled to ground, and a gate coupled to a third node; a second n-channel transistor having a drain coupled to the first node, a source coupled to ground, and a gate coupled to a second node; and an inverter having an input coupled to the first node and an output coupled to an intermediate node. A current starved inverter has an input coupled to the intermediate node and an output coupled to the second node, a logic gate has inputs coupled to the intermediate node and the second node, and an output coupled to the third node.

Claims

1. A photodetection circuit, comprising: a single photon avalanche diode (SPAD) having a cathode coupled to a high voltage supply and an anode coupled to a first node; a first n-channel transistor having a drain coupled to the first node, a source coupled to ground, and a gate coupled to a third node; a second n-channel transistor having a drain coupled to the first node, a source coupled to ground, and a gate coupled to a second node; an inverter having an input coupled to the first node and an output coupled to an intermediate node; a current starved inverter having an input coupled to the intermediate node and an output coupled to the second node; and a logic gate having inputs coupled to the intermediate node and the second node, and an output coupled to the third node.

2. The photodetection circuit of claim 1, further comprising a third n-channel transistor having a drain directly electrically connected to the anode of the SPAD, a source directly electrically connected to the first node, and a gate coupled to an enable signal.

3. The photodetection circuit of claim 1, wherein the inverter comprises: a first p-channel transistor having a source coupled to a supply voltage, a drain coupled to the intermediate node, and a gate coupled to the first node; and a fourth n-channel transistor having a drain coupled to the intermediate node, a source coupled to ground, and a gate coupled to the first node.

4. The photodetection circuit of claim 1, wherein the current starved inverter comprises: a second p-channel transistor having a source coupled to a supply voltage, a drain, and a gate coupled to a tuning voltage; a third p-channel transistor having a source coupled to the drain of the second p-channel transistor, a drain coupled to the second node, and a gate coupled to the intermediate node; and a fifth n-channel transistor having a drain coupled to the second node, a source coupled to ground, and a gate coupled to the intermediate node.

5. The photodetection circuit of claim 1, further comprising a clamp diode having a cathode coupled to a SPAD turn-off signal and an anode coupled to the anode of the SPAD.

6. The photodetection circuit of claim 1, wherein the SPAD is fully depleted.

7. A photodetection circuit, comprising: a single photon avalanche diode (SPAD) having a first terminal coupled to a voltage supply, and second terminal coupled to a first node; a first transistor having a first conduction terminal coupled to the first node, and a control terminal coupled to output from a combinational logic circuit; a second transistor having a first conduction terminal coupled to the first conduction terminal of the first transistor and a control terminal coupled to a third node; an inverter having an input coupled to the first conduction terminal of the first transistor, and an output coupled to an intermediate node; and a starved inverter having an input coupled to the intermediate node and an output coupled to the third node.

8. The photodetection circuit of claim 7, further comprising an enable transistor having a first conduction terminal coupled to the first node, a second conduction terminal coupled to the first conduction terminal of the first transistor, and a control terminal coupled to receive an enable signal.

9. The photodetection circuit of claim 7, wherein the first terminal of the SPAD is a cathode and the second terminal of the SPAD is an anode.

10. The photodetection circuit of claim 7, wherein the voltage supply is a high voltage supply.

11. The photodetection circuit of claim 7, wherein the first transistor has a second conduction terminal coupled to a second voltage supply.

12. The photodetection circuit of claim 11, wherein the second voltage supply is a reference voltage supply.

13. The photodetection circuit of claim 7, wherein the starved inverter is starved of current by a current limiting device.

14. The photodetection circuit of claim 7, wherein the combinational logic circuit comprises a logic gate having a first input coupled to the intermediate node, a second input coupled to the third node, and an output coupled to the control terminal of the first transistor.

15. The photodetection circuit of claim 7, wherein the SPAD is fully depleted.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A is a schematic diagram of a prior art SPAD based photodetection circuit.

(2) FIG. 1B is a graph of anode voltage of the photodetection circuit of FIG. 1A over time in an ideal case, and in a real-world case where the SPAD is fully depleted.

(3) FIG. 1C is a schematic diagram of a first prior art SPAD based photodetection circuit with passive quenching.

(4) FIG. 1D is a graph of the anode voltage of the photodetection circuit of FIG. 1C over time, showing the increased recharge time over the design of FIG. 1A.

(5) FIG. 1E is a schematic diagram of a second prior art SPAD based photodetection circuit with passive quenching.

(6) FIG. 1F is a graph of the cathode voltage of the photodetection circuit of FIG. 1E over time, showing the increased recharge time over the design of FIG. 1A.

(7) FIG. 2 is a schematic diagram of a SPAD based photodetection circuit disclosed herein which fully quenches the SPAD.

(8) FIG. 3A is a graph showing voltages at nodes A, B, and C of the photodetection circuit of FIG. 2 in operation.

(9) FIG. 3B is a graph showing the voltage at the anode of the SPAD of the photodetection circuit of FIG. 2 in operation.

(10) FIG. 4 is a graphing showing the effect of different values of VHPF (different levels of current starvation of the starved inverter of FIG. 2) on the anode voltage of the SPAD, as well as the voltages at nodes A, B, and C.

DETAILED DESCRIPTION

(11) The following disclosure enables a person skilled in the art to make and use the subject matter disclosed herein. The general principles described herein may be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein.

(12) Now described is a photodetection circuit 10 with active quenching. The photodetection circuit 10 includes a fully depleted single photon avalanche diode (SPAD) 11 having a cathode connected to a high voltage VHV and an anode connected to node N. A clamp diode 12 has a cathode connected to a SPAD turnoff signal SPADOFF and an anode connected to node N.

(13) An n-channel transistor MN3 has its drain connected to node N, its source connected to node A, and its gate connected to the enable signal ENABLE. An n-channel transistor MN1 has its drain connected to node A, its source connected to ground, and its gate connected to the output of OR gate 13 at node C. An n-channel transistor MN2 has its drain connected to node A, its source connected to ground, and its gate connected to node B. The OR gate 13 has inputs coupled to node D and node B, and its output coupled to node C.

(14) A starved delayed buffer 15 is connected between nodes A and B, and is comprised of an inverter 16 having its input connected to node A and its output connected to node D, and a starved inverter 17 having its input connected to node D and an output connected to node B. The inverter 16 is comprised of: p-channel transistor MP1 having its source connected to a supply voltage VDD, its drain connected to the node D, and its gate connected to node A; and n-channel transistor MN4 having its drain connected to the node D, its source connected to ground, and its gate connected to node A. The starved inverter 17 is comprised of: p-channel transistor MP2 having its source connected to the supply voltage VDD, its drain connected to the source of p-channel transistor MP3, and its gate connected to the VHPF signal; p-channel transistor MP3 having its source connected to the drain of p-channel transistor MP2, its drain connected to node B, and its gate connected to the node D; and n-channel transistor MN5 having its drain connected to node B, its source connected to ground, and its gate connected to the node D.

(15) The photodetection circuit 10 is enabled by the ENABLE signal being at a logic high to turn on MN3. In operation, the photodetection circuit 10 alternates the RC constant at the anode of the SPAD 11 between a very low value (with enough quenching resistance that is set by the W/L ratio of MN1 and MN3) during quench, very high during hold-off, and low during recharge (higher than the very low RC value during quench, lower than the very high RC value during hold-off).

(16) In detail, with additional reference to FIGS. 3A-3B, when a photon is detected by the SPAD 11, a rising edge of the SPAD output signal at node A quickly occurs at time t1 because the RC constant at this point is very low. Once the rising edge reaches the threshold value of the inverter 16, a falling edge will appear at the node D. Keep in mind that the inverter 17 is starved of current because the bias voltage VHPF is set at a level which constrains the current through MP2, and therefore the available current at the source of MP3 is limited, causing the inverter 17 to have a slow response time to pull its output high.

(17) While the falling edge at the node D triggers the starved inverter 17, as explained, the fact that the inverter 17 is starved of current means that its output at node B rises slowly, as can be seen between times t1 and t2. Therefore, at the occurrence of the falling edge at the node D, the falling edge at the node D and the low voltage at node B cause the output of the OR gate 13 to go low between times t1 and t2, turning off MN1, forcing the RC constant high and maintaining the anode voltage of the SPAD 11 nearly constant, forming a nearly flat voltage plateau for a long hold off time. Once the voltage at node B rises to the threshold level of the OR gate 13 at time t2, node C will rise high, turning on MN1 fully. The fact that node B is at the threshold level of OR gate 13 (but has not reached its maximum) at t2 turns MN2 on but in linear mode (not saturation, so that it is not fully turned on) so that it acts as a resistor with a low resistance. This lowers the RC constant to lower than it was between times t1 and t2, but higher than it was prior to time t1, forming a low impedance path for rapid recharge of the SPAD 11, achieving a short dead time despite the long hold off time. This provides for the ability to fully quench the SPAD 11 while maintaining a short dead time, thereby allowing for a rapid photodetection rate.

(18) In the above description, when referring to the RC constant, C is the internal capacitance of the SPAD 11, while R is the total resistance formed by MN1 and MN3. Depending on the biasing condition of MN1, the total resistance R changes, and therefore RC changes.

(19) Note that VHPF can be tuned so as to tune the magnitude of current provided to MP3 (e.g., tune the level of current starvation of the starved inverter 17), which enables the tuning of the length of the hold off time, therefore allowing adaption of the photodetection circuit 10 to match variations in SPADs. As VHPF increases, the rise time of the voltage at node B increases, increasing the RC constant and therefore increasing the hold off time; conversely, as VHPF decreases, the rise time of the voltage at node B decreases, decreasing the RC constant and therefore decreasing the hold off time. This can be seen in FIG. 4, for example, where for example a VHPF of 0 V or 0.1 V provides for a short hold off time, but a VHPF of 0.5 V provides for a long hold off time.

(20) While the disclosure has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be envisioned that do not depart from the scope of the disclosure as disclosed herein. Accordingly, the scope of the disclosure shall be limited only by the attached claims.