Thin film transistor including a pair of auxiliary structures corresponding to source/drain and method of manufacturing the same

Abstract

A thin film transistor includes a pair of auxiliary structures facing each other on a substrate, an active layer including an organic semiconductor and continuously grown between the pair of auxiliary structures, a gate electrode on the substrate and overlapped by the active layer, and a source electrode and a drain electrode electrically connected to the active layer. A method of manufacturing the thin film transistor is disclosed.

Claims

1. A thin film transistor comprising a substrate; a pair of auxiliary structures on the substrate, the pair of auxiliary structures including a first auxiliary structure and a second auxiliary structure facing each other; the first auxiliary structure including a lower surface and an upper surface facing each other, the lower surface of the first auxiliary structure facing a surface of the substrate, the second auxiliary structure including a lower surface and an upper surface facing each other, the lower surface of the second auxiliary structure facing the surface of the substrate, an active layer on the substrate, the active layer including an organic semiconductor that is contiguous between the first auxiliary structure and a second auxiliary structure; a gate electrode overlapped by the active layer; and a source electrode and a drain electrode electrically connected to the active layer so a portion of the source electrode and a portion of the drain electrode are arranged overlying the active layer, wherein one edge of the active layer contacts at least a part of the upper surface of the first auxiliary structure and another edge of the active layer contacts at least a part of the upper surface of the second auxiliary structure, and the active layer is continuously formed between the first auxiliary structure and the second auxiliary structure.

2. The thin film transistor of claim 1, wherein a lower surface of the active layer contacts the first auxiliary structure and the second auxiliary structure, and an upper surface of the active layer contacts the source electrode and the drain electrode.

3. The thin film transistor of claim 1, wherein the active layer is a single crystal active layer.

4. The thin film transistor of claim 1, wherein the pair of auxiliary structures include at least one of a metal a semi-metal, an inorganic material, or an organic material.

5. The thin film transistor of claim 1, wherein an interval between the first auxiliary structure and the second auxiliary structure is greater than 0 m and less than or equal to about 10 m.

6. The thin film transistor of claim 1, wherein the organic semiconductor is a deposition-type organic semiconductor.

7. The thin film transistor of claim 1, wherein the organic semiconductor includes a structure represented by Chemical Formula 1 or 2: ##STR00007## wherein, in Chemical Formula 1 or 2, X.sub.1 and X.sub.2 are independently S, Se, or Te, and R.sub.1 to R.sub.4 are independently hydrogen, a substituted or unsubstituted C1 to C30 alkyl group, a substituted or unsubstituted C2 to C30 alkenyl group, a substituted or unsubstituted C6 to C30 aryl group, a substituted or unsubstituted C3 to C30 heteroaryl group, or a combination thereof.

8. An electronic device comprising: the thin film transistor of claim 1.

9. A thin film transistor comprising a substrate; a gate electrode on the substrate; a pair of auxiliary structures on the substrate, the pair of auxiliary structures including a first auxiliary structure spaced apart from a second auxiliary structure; the first auxiliary structure including a lower surface and an upper surface facing each other, the lower surface of the first auxiliary structure facing a surface of the substrate, the second auxiliary structure including a lower surface and an upper surface facing each other, the lower surface of the second auxiliary structure facing the surface of the substrate, an active layer on the substrate, the active layer including an organic semiconductor between the first auxiliary structure and the second auxiliary structure; a source electrode and a drain electrode electrically connected to the active layer so a portion of the source electrode and a portion of the drain electrode are arranged overlying the active layer; a gate insulating layer on the substrate, the gate insulating layer between the active layer and the gate electrode, the gate insulating layer extending between the gate electrode and the pair of auxiliary structures; and a surface treatment layer on the substrate, the surface treatment layer between the active layer and the gate insulating layer, the surface treatment layer between the first auxiliary structure and the second auxiliary structure, wherein one edge of the active layer contacts at least a part of the upper surface of the first auxiliary structure and another edge of the active layer contacts at least a part of the upper surface of the second auxiliary structure, and the active layer is continuously formed between the first auxiliary structure and the second auxiliary structure.

10. The thin film transistor of claim 9, wherein an interval between the pair of auxiliary structures is greater than 0 m and less than or equal to about 10 m.

11. The thin film transistor of claim 9, wherein the organic semiconductor includes a structure represented by Chemical Formula 1 or 2: ##STR00008## wherein, in Chemical Formula 1 or 2, X.sub.1 and X.sub.2 are independently S, Se, or Te, and R.sub.1 to R.sub.4 are independently hydrogen, a substituted or unsubstituted C1 to C30 alkyl group, a substituted or unsubstituted C2 to C30 alkenyl group, a substituted or unsubstituted C6 to C30 aryl group, a substituted or unsubstituted C3 to C30 heteroaryl group, or a combination thereof.

12. The thin film transistor of claim 9, wherein the pair of auxiliary structures include at least one of a metal, a semi-metal, an inorganic material, or an organic material.

13. The thin film transistor of claim 9, wherein the surface treatment layer includes at least one of a silane compound or a thiol compound.

14. An electronic device comprising the thin film transistor of claim 9.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a cross-sectional view showing a thin film transistor according to some example embodiments,

(2) FIG. 2 is a schematic view showing examples of selective deposition of an organic semiconductor in the thin film transistor of FIG. 1,

(3) FIGS. 3 to 7 are cross-sectional views showing a manufacturing method of the thin film transistor of FIG. 1,

(4) FIG. 8 is a cross-sectional view showing a thin film transistor according to some example embodiments,

(5) FIG. 9 is a 50 magnification photograph of the active layer region of the thin film transistor according to Example 1,

(6) FIG. 10 is a 1000 magnification photograph of the active layer region of the thin film transistor according to Example 1,

(7) FIG. 11 is a 50 magnification photograph of the active layer region of the thin film transistor according to Comparative Example 2,

(8) FIG. 12 is a 1000 magnification photograph of the active layer region of the thin film transistor according to Comparative Example 2,

(9) FIG. 13 is a 50 magnification photograph of the active layer region of the thin film transistor according to Comparative Example 3,

(10) FIG. 14 is a 1000 magnification photograph of the active layer region of the thin film transistor according to Comparative Example 3,

(11) FIG. 15 is a 50 magnification photograph of the active layer region of the thin film transistor according to Comparative Example 4,

(12) FIG. 16 is a 1000 magnification photograph of the active layer region of the thin film transistor according to Comparative Example 4, and

(13) FIG. 17 is a 1000 magnification photograph of the active layer region of the thin film transistor according to Comparative Example 5.

DETAILED DESCRIPTION

(14) Example embodiments will hereinafter be described in detail, and, based on the disclosure that follows, may be easily performed by those who have common knowledge in the related art. However, inventive concepts may be embodied in many different forms and is not to be construed as limited to the example embodiments set forth herein.

(15) When a definition is not otherwise provided, substituted refers to replacement of hydrogen of a compound by a halogen atom (e.g., F, Br, Cl, or I), a hydroxy group, an alkoxy group, a nitro group, a cyano group, an amino group, an azido group, an amidino group, a hydrazino group, a hydrazono group, a carbonyl group, a carbamyl group, a thiol group, an ester group, a carboxyl group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid or a salt thereof, a C1 to C20 alkyl group, a C2 to C20 alkenyl group, a C2 to C20 alkynyl group, a C6 to C30 aryl group, a C7 to C30 arylalkyl group, a C1 to C30 alkoxy group, a C1 to C20 heteroalkyl group, a C3 to C20 heteroarylalkyl group, a C3 to C30 cycloalkyl group, a C3 to C15 cycloalkenyl group, a C6 to C15 cycloalkynyl group, a C3 to C30 heterocycloalkyl group, and a combination thereof.

(16) As used herein, when specific definition is not otherwise provided, hetero refers to one including 1 to 3 heteroatoms selected from N, O, S, Se, and P.

(17) Hereinafter, thin film transistors according to some example embodiments are described.

(18) FIG. 1 is a cross-sectional view showing a thin film transistor according to some example embodiments and FIG. 2 is a schematic view showing examples of selective depositions of an organic semiconductor in the thin film transistor of FIG. 1.

(19) Referring to FIG. 1, a thin film transistor according to some example embodiments includes a substrate 110, a gate electrode 124, a gate insulating layer 140, a pair of auxiliary structures 131 and 132, a surface treatment layer 151, an active layer 154, a source electrode 173, and a drain electrode 175.

(20) The substrate 110 may be for example a transparent glass, an insulation substrate such as polymer, or a silicon wafer. The polymer may include for example polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyacrylate, polyimide, or a combination thereof, but is not limited thereto. Alternatively, the substrate 110 may be a conductive substrate (e.g., metal or metal alloy) that may function as the gate electrode, in which case the gate electrode 124 may be omitted.

(21) As shown in FIG. 1, the gate electrode 124 is formed on the substrate 110. The gate electrode 124 is connected to a gate line (not shown) for transferring a gate signal. The gate electrode 124 may be made of gold (Au), copper (Cu), nickel (Ni), aluminum (Al), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), an alloy thereof, or a combination thereof, but is not limited thereto. However, when the substrate 110 is a silicon wafer, the gate electrode 124 may be a doping region of the silicon wafer.

(22) A gate insulating layer 140 is formed on the gate electrode 124.

(23) The gate insulating layer 140 may be made of an organic material and/or an inorganic material. Examples of the organic material may include a compound such as a polyvinyl alcohol-based compound, a polyimide-based compound, a polyacryl-based compound, a polystyrene-based compound, a benzocyclobutane (BCB), and the like, and examples of the inorganic material may include a silicon nitride (SiN.sub.x) and a silicon oxide (SiO.sub.2). The gate insulating layer 140 may include for example one layer or two or more layers.

(24) A pair of auxiliary structures 131 and 132 facing each other are formed on the gate insulating layer 140. The pair of auxiliary structures 131 and 132 facing each other may have an island shape and may be disposed in plural along a row and/or a column on the gate insulating layer 140.

(25) The pair of auxiliary structures 131 and 132 faces each other with a desired (and/or alternatively predetermined) interval and provides a region where an organic semiconductor that will be described later is deposited. For example, the organic semiconductor may be selectively deposited at least a part of and/or around the pair of auxiliary structures 131 and 132 due to a mutual energy (interaction) difference between a region where the pair of auxiliary structures 131 and 132 are formed and the organic semiconductor and between a region where the pair of auxiliary structures 131 and 132 are not formed, that is, for example where the gate insulating layer 140 is exposed and the organic semiconductor.

(26) For example, the organic semiconductor may respectively start to grow from the surface of or around one of the pair of auxiliary structures 131 and 132 and the surface of or around the other of the pair of auxiliary structures 131 and 132 and meet each other between the pair of auxiliary structures 131 and 132 and thus form the active layer 154 having a desired (and/or alternatively predetermined) pattern.

(27) For example, referring to FIG. 2, when the organic semiconductor is deposited on the pair of auxiliary structures 131 and 132 and the gate insulating layer 140, the mutual energy (E.sub.MS.sup.{circle around (2)}) between the surface of one of the pair of auxiliary structures 131 and 132 and the organic semiconductor may differ from the mutual energy (E.sub.MS.sup.{circle around (1)}) between the surface of the gate insulating layer 140 and the organic semiconductor. For example, deposition selectivity of the organic semiconductor may be determined by a nucleation energy difference between a region for deposition and a region for non-deposition, and the nucleation energy difference may be larger, as the mutual energy (E.sub.MS.sup.{circle around (2)}) between one surface of the auxiliary structures 131 and 132 and the organic semiconductor has a larger difference from the mutual energy (EMS.sup.{circle around (1)}) between the surface of the gate insulating layer 140 and the organic semiconductor. Herein, the region where the organic semiconductor is not deposited is assumed as the surface of the gate insulating layer 140 but is not limited thereto and may be other layers.

(28) For example, the nucleation energy difference of the organic semiconductor may be expressed by Relationship Equation 1.

(29) $\begin{matrix} Nucleation Energy \frac{(-)}{} & [Relationship Equation 1] \end{matrix}$

(30) In Relationship Equation 1,

(31) Nucleation Energy is a difference between a region where the organic semiconductor is deposited and a region where the organic semiconductor is not deposited,

(32) E.sub.MS.sup.{circle around (1)} is mutual energy between the region where the organic semiconductor is not deposited and the organic semiconductor,

(33) E.sub.MS.sup.{circle around (2)} is mutual energy between one surface of the auxiliary structures 131 and 132 and the organic semiconductor, and

(34) is a deposition rate of the organic semiconductor.

(35) Referring to Relationship Equation 1, deposition selectivity of the organic semiconductor may be larger, as mutual energy (E.sub.MS.sup.{circle around (2)}) between one surface of the auxiliary structures 131 and 132 and the organic semiconductor and mutual energy (EMS.sup.{circle around (1)}) between a region where the organic semiconductor is not deposited like the surface of the gate insulating layer 140 has a larger difference and as the organic semiconductor is deposited at a slower deposition rate.

(36) The pair of auxiliary structures 131 and 132 may have a space of less than or equal to about 10 m. Within the range, the space may be for example in a range of about 2 m to about 10 m. When the pair of auxiliary structures 131 and 132 has a space within the range, the organic semiconductor may be formed into the active layer 154 having a desired (and/or alternatively predetermined) pattern through a consecutive growth between the pair of auxiliary structures 131 and 132.

(37) The surface of the pair of auxiliary structures 131 and 132 and/or the gate insulating layer 140 may be for example surface-treated. The surface treatment may change surface energy and further increase deposition selectivity of the organic semiconductor.

(38) The pair of auxiliary structures 131 and 132 may be for example a metal, a semi-metal, an inorganic material, and/or an organic material, and for example include one layer or two or more layers.

(39) The active layer 154 is formed on at least a part of the upper surface of the pair of auxiliary structures 131 and 132 and between the pair of auxiliary structures 131 and 132.

(40) The active layer 154 is overlapped with the gate electrode 124 and selectively formed on at least a part of the upper surface of and between the pair of auxiliary structures 131 and 132.

(41) The active layer 154 includes an organic semiconductor and may be a for example, a single crystal or single crystal-like active layer due to the organic semiconductor selectively grown as described above.

(42) The organic semiconductor may continuously grow between the pair of auxiliary structures 131 and 132.

(43) The active layer 154 may respectively contact at least a part of the pair of auxiliary structures 131 and 132, and specifically at least a part of the lower surface of the active layer 154 may respectively contact at least of a part of the pair of auxiliary structures 131 and 132.

(44) The active layer 154 may be continuously formed from one surface of the pair of auxiliary structures 131 and 132 to the other surface of the pair of auxiliary structures 131 and 132.

(45) For example, at least a part of the lower surface of the active layer 154 may respectively contact at least a part of the pair of auxiliary structures 131 and 132.

(46) The organic semiconductor may be for example a deposition-type organic semiconductor, for example a heteroacene compound.

(47) The organic semiconductor may be for example a compound represented by Chemical Formula 1 or 2, but is not limited thereto.

(48) ##STR00003##

(49) In Chemical Formula 1 or 2,

(50) X.sub.1 and X.sub.2 are independently S, Se, or Te, and

(51) R.sub.1 to R.sub.4 are independently hydrogen, a substituted or unsubstituted C1 to C30 alkyl group, a substituted or unsubstituted C2 to C30 alkenyl group, a substituted or unsubstituted C6 to C30 aryl group, a substituted or unsubstituted C3 to C30 heteroaryl group, or a combination thereof.

(52) The organic semiconductor may be for example represented by Chemical Formula 1a or 2a, but is not limited thereto.

(53) ##STR00004##

(54) In Chemical Formula 1a or 2a, R.sub.1 to R.sub.4 are the same as above.

(55) The organic semiconductor may be for example one of compounds of Group 1, but is not limited thereto.

(56) ##STR00005##

(57) In Group 1, Hex, Hep, and Oct are a hexyl group, a heptyl group, and an octyl group respectively.

(58) The surface treatment layer 151 is formed under the active layer 154. The surface treatment layer 151 may include a silane compound such as octadecyltrichlorosilane (ODTS) and/or a thiol compound, but is not limited thereto.

(59) The source electrode 173 and the drain electrode 175 are formed on the active layer 154. The source electrode 173 and the drain electrode 175 face each other with the active layer 154 therebetween. The source electrode 173 is electrically connected to the data line (not shown) transferring the data signal. The source electrode 173 and the drain electrode 175 may be made of gold (Au), copper (Cu), nickel (Ni), aluminum (Al), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), an alloy thereof, or a combination thereof.

(60) Hereinafter, a method of manufacturing a thin film transistor according to some example embodiments is described.

(61) FIGS. 3 to 7 are cross-sectional views showing a manufacturing method of the thin film transistor of FIG. 1.

(62) Referring to FIG. 3, a conductive layer is disposed on the substrate 110 and photo-etched to form the gate electrode 124. Subsequently, on the gate electrode 124, the gate insulating layer 140 is formed by depositing silicon oxide (SiO.sub.2), silicon nitride (SiNx), or an organic insulator.

(63) Then, referring to FIG. 4, a thin film 130 for auxiliary structures is formed on the whole surface of the gate insulating layer 140. The thin film 130 for auxiliary structures may include for example a metal, a semi-metal, an oxide, a nitride, and/or an organic material, and for example be formed through a deposition or solution process.

(64) Subsequently, referring to FIG. 5, a plurality of the pair of auxiliary structures 131 and 132 are formed on the thin film 130 for auxiliary structures by coating and patterning a photosensitive layer (not shown) to form a photosensitive pattern and then, by using the photosensitive pattern as a mask to photo-etch the thin film 130 for auxiliary structures.

(65) Then, referring to FIG. 6, the pair of auxiliary structures 131 and 132 may be for example surface-treated by oxygen plasma. Subsequently, on the gate insulating layer 140, the surface treatment layer 151 is formed. The surface treatment layer 151 may be selectively formed on the gate insulating layer 140 and for example include a silane compound such as octadecyltrichlorosilane (ODTS) and/or a thiol compound.

(66) Referring to FIG. 7, an organic semiconductor is thermally evaporated to form the active layer 154 overlapped with the gate electrode 124 and contiguous between the pair of auxiliary structures 131 and 132. The organic semiconductor is continuously grown between the pair of auxiliary structures 131 and 132. The organic semiconductor respectively starts to grow from one surface of or around the pair of auxiliary structures 131 and 132 and then, grows and meets between the pair of auxiliary structures 131 and 132 and thus may be selectively deposited in a region contacting at least a part of and around the pair of auxiliary structures 131 and 132.

(67) Herein, deposition selectivity of the organic semiconductor may be determined by a thermal evaporation condition of the organic semiconductor, for example, increased at a relatively high temperature and a relatively slow deposition rate during the thermal evaporation.

(68) For example, the thermally evaporating of the organic semiconductor may be performed at a substrate temperature of greater than or equal to about 85 C. and a deposition rate of less than about 0.1 /s. Herein, the substrate temperature means an actual temperature of a substrate during the thermally evaporating. The thermally evaporating may be performed at a deposition temperature of greater than or equal to about 125 C. in order to obtain the substrate temperature.

(69) For example, the thermally evaporating of the organic semiconductor may be performed at a substrate temperature of about 85 C. to about 100 C. and a deposition rate of about 0.005 /s to about 0.05 /s. The thermally evaporating may be performed at a deposition temperature of about 125 C. to about 145 C. in order to obtain the substrate temperature.

(70) The active layer 154 may be a single crystal or single crystal-like active layer by continuously growing the organic semiconductor.

(71) Next, referring to FIG. 1, a conductive layer is laminated on the active layer 154. Then, a photolithography and patterning operation (e.g., etching) may be performed to form a source electrode 173 and a drain electrode 175 from the conductive layer.

(72) Modifications to the method described in FIGS. 3 to 7 may be made. For example, if the substrate 110 is a conductive material (e.g., metal or metal alloy), then the substrate may be used as the gate electrode and the operation for forming the gate electrode 124 may be omitted. Alternatively, if the substrate is a semiconductor (e.g., silicon substrate), then the gate electrode 124 may be formed as a doped region in the semiconductor substrate 110.

(73) FIG. 8 is a cross-sectional view showing a thin film transistor according to some example embodiments.

(74) Referring to FIG. 8, a thin film transistor according to some example embodiments includes a substrate 110, a gate electrode 124, a gate insulating layer 140, a pair of auxiliary structures 131 and 132, a surface treatment layer 151, and an active layer 154 like the thin film transistor described in FIG. 1.

(75) However, the thin film transistor shown in FIG. 8 does not include a source electrode 173 and a drain electrode 175 separately. The pair of auxiliary structures 131 and 132 function as a source electrode and a drain electrode.

(76) Herein, the pair of auxiliary structures 131 and 132 may be for example made of a metal in order to play a role of a source electrode and a drain electrode.

(77) Although an organic thin film transistor having a bottom gate structure has been described as a an example thin film transistor, inventive concepts not limited thereto, and it may be applied to all organic thin film transistors such as a thin film transistor having a top gate structure and/or a thin film transistor having a double-gate structure (e.g., a top gate and a bottom gate).

(78) The thin film transistor may be applied to a switching or driving device of various electronic devices, and the electronic device may be, for example, a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an electrophoretic display device, a solar cell, or an organic sensor.

(79) Hereinafter, inventive concepts are described in more detail with reference to examples. However, these examples are non-limiting, and inventive concepts are not limited thereto.

(80) Manufacture of Thin Film Transistor

EXAMPLE 1

(81) A Ti (50 )/Au (350 ) metal layer is formed by sequentially depositing titanium (Ti) and gold (Au) on a silicon wafer substrate having a gate electrode formed therein and covered with 3000 -thick SiO.sub.2. On the metal layer, a photosensitive layer is coated and cured and then, patterned to form a pair of auxiliary structure. The surface of the pair of auxiliary structures is activated by performing oxygen plasma (100 W, 30 seconds). Subsequently, the substrate is dipped in a solution obtained by diluting octadecyltrichlorosilane (ODTS) in hexane to have 5 mM of a concentration and allowed to stand for one hour. Then, the substrate is taken therefrom, treated with hexane and ethanol to remove a non-reacted material, and heat-treated. Subsequently, 1000 -thick active layer is formed by thermally depositing the following organic semiconductor at a deposition temperature of 130 C. (a substrate temperature of 90 C.) at a deposition rate of 0.01 /s, ultimately manufacturing a thin film transistor.

(82) ##STR00006##

EXAMPLE 2

(83) A Ti (50 )/Au (350 ) metal layer is formed by sequentially depositing titanium (Ti) and gold (Au) on a silicon wafer substrate having a gate electrode formed therein and covered with 3000 -thick SiO.sub.2 over the gate electrode and substrate. On the metal layer, a photosensitive layer is coated and cured and then, patterned to form a pair of auxiliary structure. Subsequently, the surface of the pair of auxiliary structure is activated by performing oxygen plasma (100 W, 30 seconds). The substrate is dipped in a solution by diluting octadecyltrichlorosilane (ODTS) in hexane to have a concentration of 5 mM and allowed to stand for one hour. Subsequently, the substrate is taken therefrom, treated with hexane and ethanol to remove a non-reacted material, and heat-treated. Then, the semiconductor is thermally evaporated at a deposition temperature of 130 C. (a substrate temperature of 90 C.) at a deposition rate of 0.01 /s to form a 1000 -thick active layer. On the active layer, gold (Au) is deposited to be 1000 thick and treated through photolithography to form a source electrode and a drain electrode having a larger area than the auxiliary structure and ultimately, manufacture a thin film transistor.

Comparative Example 1

(84) A silicon wafer substrate having a gate electrode formed therein and covered with 3000 -thick SiO.sub.2 is exposed to O.sub.2 plasma (100 W, 30 seconds) and then, dipped in a octadecyltrichlorosilane solution diluted in hexane to have a concentration of 5 mMol and allowed to stand for 1 hour. Subsequently, the substrate is taken therefrom, treated with hexane and ethanol to remove a non-reacted material, and heat-treated. Then, the organic semiconductor is thermally evaporated to be 300 thick to form a thin film for an active layer, and a photosensitive layer is coated and cured and then, dry-etched to form an active layer. After removing the photosensitive layer, a source electrode and a drain electrode are formed by depositing gold (Au) to be 1000 thick and treating it through photolithography, ultimately manufacturing a thin film transistor.

Comparative Example 2

(85) A thin film transistor is manufactured according to the same method as Example 1 except for thermally depositing the organic semiconductor at a deposition temperature of 120 C. (a substrate temperature of 80 C.) at a deposition rate of 0.01 /s.

Comparative Example 3

(86) A thin film transistor is manufactured according to the same method as Example 1 except for thermally depositing the organic semiconductor at a deposition temperature of 150 C. (a substrate temperature of 105 C.) at a deposition rate of 0.05 /s.

Comparative Example 4

(87) A thin film transistor is manufactured according to the same method as Example 1 except for thermally depositing the organic semiconductor at a deposition temperature of 150 C. (a substrate temperature of 105 C.) at a deposition rate of 0.1 /s.

Comparative Example 5

(88) A thin film transistor is manufactured according to the same method as Example 1 except for thermally depositing the organic semiconductor at a deposition temperature of 150 C. (a substrate temperature of 105 C.) at a deposition rate of 0.01 /s.

Evaluation I

(89) A selective deposition of each active layer in the thin film transistors according to Example 1 and Comparative Examples 2 to 5 is evaluated.

(90) FIG. 9 is a 50 magnification photograph of the active layer region of the thin film transistor according to Example 1, FIG. 10 is a 1000 magnification photograph of the active layer region of the thin film transistor according to Example 1, FIG. 11 is a 50 magnification photograph of the active layer region of the thin film transistor according to Comparative Example 2, FIG. 12 is a 1000 magnification photograph of the active layer region of the thin film transistor according to Comparative Example 2, FIG. 13 is a 50 magnification photograph of the active layer region of the thin film transistor according to Comparative Example 3, FIG. 14 is a 1000 magnification photograph of the active layer region of the thin film transistor according to Comparative Example 3, FIG. 15 is a 50 magnification photograph of the active layer region of the thin film transistor according to Comparative Example 4, FIG. 16 is a 1000 magnification photograph of the active layer region of the thin film transistor according to Comparative Example 4, and FIG. 17 is a 1000 magnification photograph of the active layer region of the thin film transistor according to Comparative Example 5.

(91) Referring to FIGS. 9 and 10, the thin film transistor of Example 1 shows that an organic semiconductor is selectively deposited on an auxiliary structure and consecutively grows between a pair of auxiliary structure.

(92) On the contrary, referring to FIGS. 11 to 17, the thin film transistors according to Comparative Examples 2 to 5 do not show that an organic semiconductors is not selectively deposited on and auxiliary structure and thus deposited on the whole surface of a substrate (Comparative Examples 2 and 4) or not deposited at all (Comparative Examples 3 and 5).

Evaluation II

(93) Charge mobility of the thin film transistors according to Examples 1 and 2 and Comparative Example 1 is evaluated.

(94) The charge mobility is obtained by obtaining a graph having (I.sub.SD).sup.1/2 and V.sub.G as variables from a saturation region current equation and a slope in the graph.

(95) $I_{SD} = \frac{{WC}_{0}}{2 L} {(V_{G} - V_{T})}^{2}$ $\sqrt{I_{Sd}} = \sqrt{\frac{C_{0} W}{2 L}} (V_{G} - V_{T})$ $slope - \sqrt{\frac{C_{0} W}{2 L}}$ $_{FBT} - {(slope)}^{2} \frac{2 L}{C_{0} W}$

(96) In the equations, I.sub.SD is a source-drain current, or .sub.FET is charge mobility, C.sub.0 is electrostatic capacity of a gate insulating layer, W is a channel width, L is a channel length, V.sub.G is a gate voltage, and V.sub.T is a threshold voltage.

(97) The results are shown in Table 1.

(98) TABLE-US-00001 TABLE 1 Charge mobility (cm.sup.2/Vs) Example 1 10.2 Example 2 14.1 Comparative Example 1 2.1

(99) Referring to Table 1, the thin film transistors according to Examples 1 and 2 show higher charge mobility than the thin film transistor according to Comparative Example 1.

(100) While some example embodiments of inventive concepts have been described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the claims.

Thin film transistor including a pair of auxiliary structures corresponding to source/drain and method of manufacturing the same

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H10K10/84

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H10K10/486

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H10K10/484

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H10K10/80

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H01L51/05

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Abstract

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