Comparison circuit

Abstract

A comparison circuit includes a preliminary amplification circuit that amplifies a voltage difference between a first input voltage and a second input voltage and a latch circuit that compares magnitudes of the first input voltage and the second input voltage according to the amplified voltage difference and latch a comparison result. The preliminary amplification circuit converts the first input voltage and the second input voltage input with the falling edge timing of a clock signal into a first control signal and a second control signal, respectively that return from the reversal state at respective speeds corresponding to the first input voltage and the second input voltage. The latch circuit compares the first input voltage and the second input voltage according to the first control signal and the second control signal.

Claims

1. A comparison circuit comprising: a preliminary amplification circuit that amplifies a voltage difference between a first input voltage and a second input voltage; and a latch circuit that compares magnitudes of the first input voltage and the second input voltage according to the amplified voltage difference and latch a comparison result; wherein the preliminary amplification circuit converts the first input voltage and the second input voltage into a first control signal and a second control signal, respectively, that exhibit reversals with specific change timing of a clock signal and returns at speeds corresponding to respective magnitudes of the first input voltage and the second input voltage; and the latch circuit compares magnitudes of the first input voltage and the second input voltage according to the first control signal and the second control signal.

2. The comparison circuit according to claim 1, wherein the preliminary amplification circuit includes a first transistor, a second transistor, a first capacitor, and a second capacitor; respective source terminals of the first transistor and the second transistor are connected to one of a power supply voltage and a reference voltage; a drain terminal of the first transistor and one terminal of the first capacitor are connected to a first control signal terminal from which the first control signal is output to the latch circuit; a drain terminal of the second transistor and one terminal of the second capacitor are connected to a second control signal terminal from which the second control signal is output to the latch circuit; and the clock signal is supplied to another terminal of the first capacitor and another terminal of the second capacitor.

3. The comparison circuit according to claim 2, wherein a third transistor including a gate terminal to which the clock signal is supplied is connected to a node between the first transistor and the second transistor.

4. The comparison circuit according to claim 2, wherein the latch circuit includes fourth to ninth transistors that each has a channel polarity that is a first polarity; the latch circuit includes tenth to thirteenth transistors that each has a channel polarity that is a second polarity; respective source terminals of the fourth to ninth transistors are connected to one of the power supply voltage and the reference voltage; respective source terminals of the twelfth and thirteenth transistors are connected to another one of the power supply voltage and the reference voltage; respective drain terminals of the fourth, sixth, and tenth transistors are connected to a first output terminal; respective drain terminals of the fifth, seventh, and eleventh transistors are connected to a second output terminal; a source terminal of the tenth transistor and respective drain terminals of the eighth and twelfth transistors are interconnected to each other; a source terminal of the eleventh transistor and respective drain terminals of the ninth and thirteenth transistors are interconnected to each other; the first control signal terminal is connected to respective gates of the fourth, eighth, and twelfth transistors; and the second control signal terminal is connected to respective gates of the fifth, ninth, and thirteenth transistors.

5. The comparison circuit according to claim 4, further comprising: a fourteenth transistor including a gate terminal to which the first control signal terminal is connected, a drain terminal connected to the second output terminal, and a source terminal connected to respective source terminals of the fourth to seventh transistors; and a fifteenth transistor including a gate terminal to which the second control signal terminal is connected, a drain terminal connected to the first output terminal, and a source terminal connected to the respective source terminals of the fourth to seventh transistors.

6. The comparison circuit according to claim 5, wherein the fourteenth and fifteenth transistors are each a PMOS transistor.

7. The comparison circuit according to claim 5, wherein the fourteenth and fifteenth transistors are each an NMOS transistor.

8. The comparison circuit according to claim 4, wherein the fourth to ninth transistors are each a PMOS transistor that has a P channel polarity; and the tenth to thirteenth transistors are each an NMOS transistor that has an N channel polarity.

9. The comparison circuit according to claim 4, wherein at least a portion of the fourth to ninth transistors and the tenth to thirteenth transistors define an RS flip-flop.

10. The comparison circuit according to claim 4, wherein the thirteenth transistor approaches a conduction state faster than the twelfth transistor; and the fifth transistor approaches a non-conduction state faster than the fourth transistor.

11. The comparison circuit according to claim 4, wherein the first transistor, the second transistor, and the fourth to ninth transistors are each an NMOS transistor, and the tenth to thirteenth transistors are each a PMOS transistor.

12. The comparison circuit according to claim 2, wherein the first transistor is a PMOS transistor; and the second transistor is a PMOS transistor.

13. The comparison circuit according to claim 1, wherein the first control signal and the second control signal have waveforms that exhibit reversals to a low-level side with a falling edge timing of the clock signal and returns to a high-level side at speeds corresponding to magnitudes of the first input voltage and the second input voltage.

14. The comparison circuit according to claim 1, wherein the latch circuit operates in response to only the first control signal and the second control signal.

15. The comparison circuit according to claim 1, wherein the clock signal is the only clock signal supplied to the preliminary amplification circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a circuit diagram of a first comparison circuit in the related art.

(2) FIGS. 2A to 2C are timing charts representing voltage waveforms in respective portions in the first comparison circuit in the related art.

(3) FIG. 3 is a circuit diagram of a second comparison circuit in the related art.

(4) FIG. 4 is a circuit diagram of a third comparison circuit in the related art.

(5) FIGS. 5A to 5C are timing charts representing voltage waveforms in respective portions in the third comparison circuit in the related art.

(6) FIG. 6 is a circuit diagram of a comparison circuit according to a first preferred embodiment of the present invention.

(7) FIG. 7A is a timing chart representing a clock signal in the comparison circuit according to the first preferred embodiment of the present invention, FIG. 7B is a timing chart representing a voltage V.sub.x at a node x and a voltage V.sub.y at a node y, and FIG. 7C is a timing chart representing the voltage waveform of a voltage V.sub.out1 at an output terminal out1 and the voltage waveform of a voltage V.sub.out2 at an output terminal out2.

(8) FIG. 8 is a circuit diagram of a comparison circuit that is a modification of the first preferred embodiment of the present invention.

(9) FIG. 9A is a timing chart representing a clock signal in the comparison circuit that is the modification of the first preferred embodiment of the present invention, FIG. 9B is a timing chart representing a voltage V.sub.x at a node x and a voltage V.sub.y at a node y, and FIG. 9C is a timing chart representing the voltage waveform of a voltage V.sub.out1 at an output terminal out1 and the voltage waveform of a voltage V.sub.out2 at an output terminal out2.

(10) FIG. 10 is a circuit diagram of a comparison circuit according to a second preferred embodiment of the present invention.

(11) FIG. 11 is a circuit diagram of a comparison circuit that is a modification of the second preferred embodiment of the present invention.

(12) FIG. 12 is a circuit diagram of a comparison circuit according to a third preferred embodiment of the present invention.

(13) FIG. 13A is a timing chart representing a clock signal in the comparison circuit according to the third preferred embodiment of the present invention, FIG. 13B is a timing chart representing a voltage V.sub.x at a node x, a voltage V.sub.y at a node y, and a voltage VB at a node B, and FIG. 13C is a timing chart representing the voltage waveform of a voltage V.sub.out1 at an output terminal out1 and the voltage waveform of a voltage V.sub.out2 at an output terminal out2.

(14) FIG. 14 is a circuit diagram of a comparison circuit that is a modification of the third preferred embodiment of the present invention.

(15) FIG. 15A is a timing chart representing a clock signal in the comparison circuit that is a modification of the third preferred embodiment of the present invention, FIG. 15B is a timing chart representing a voltage V.sub.x at a node x, a voltage V.sub.y at a node y, and a voltage VB at a node B, and FIG. 15C is a timing chart representing the voltage waveform of a voltage V.sub.out1 at an output terminal out1 and the voltage waveform of a voltage V.sub.out2 at an output terminal out2.

(16) FIG. 16 is a circuit diagram of a comparison circuit according to a fourth preferred embodiment of the present invention.

(17) FIG. 17 is a circuit diagram of a comparison circuit that is a modification of the fourth preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(18) Preferred embodiments of the present invention will be described in detail below with reference to the drawings.

(19) A comparison circuit according to a first preferred embodiment of the present invention will be described below.

(20) FIG. 6 is a circuit diagram of a comparison circuit 41A according to a first preferred embodiment of the present invention.

(21) The comparison circuit 41A includes a preliminary amplification circuit 42A that dynamically amplifies a voltage difference between a first input voltage V.sub.in1 input into a first input terminal in1 and a second input voltage V.sub.in2 input into a second input terminal in2 and a latch circuit 43A that compares the magnitudes of the first input voltage V.sub.in1 and the second input voltage V.sub.in2 according to the amplified voltage difference and latches a result of the comparison.

(22) The preliminary amplification circuit 42A converts the first input voltage V.sub.in1 and the second input voltage V.sub.in2 which are input with the specific change timing of a clock signal CLK shown in FIG. 7A, the falling edge timing of the clock signal CLK in the first preferred embodiment, into a first control signal V.sub.x and a second control signal V.sub.y shown in FIG. 7B, respectively. These drawings show signal waveforms obtained in the case where the first input voltage V.sub.in1 is higher than the second input voltage V.sub.in2 (V.sub.in1>V.sub.in2). The first control signal V.sub.x appears at a node x corresponding to a first control signal terminal. The second control signal V.sub.y appears at a node y corresponding to a second control signal terminal. The first control signal V.sub.x and the second control signal V.sub.y have waveforms that exhibit reversals to the low-level side with the falling edge timing of the clock signal CLK and returns to the high-level side at speeds corresponding to the magnitudes of the first input voltage V.sub.in1 and the second input voltage V.sub.in2. The latch circuit 43A compares the first input voltage V.sub.in1 and the second input voltage V.sub.in2 with each other according to the first control signal V.sub.x and the second control signal V.sub.y. FIG. 7C shows a result of the comparison. As the result of the comparison, a first output voltage V.sub.out1 is output to a first output terminal out1 and a second output voltage V.sub.out2 is output to a second output terminal out2.

(23) In the first preferred embodiment, the preliminary amplification circuit 42A includes a first transistor M1, a second transistor M2, a first capacitor C.sub.D1, and a second capacitor C.sub.D2. The respective source terminals of the first transistor M1 and the second transistor M2 are connected to a power supply voltage V.sub.DD. The drain terminal of the first transistor M1 and one terminal of the first capacitor C.sub.D1 are connected to the node x from which the first control signal V.sub.x is output to the latch circuit 43A. The drain terminal of the second transistor M2 and one terminal of the second capacitor C.sub.D2 are connected to the node y from which the second control signal V.sub.y is output to the latch circuit 43A. The clock signal CLK is supplied to the other terminals of the first capacitor C.sub.D1 and the second capacitor C.sub.D2. The first transistor M1 and the second transistor M2 in the preliminary amplification circuit 42A are formed of PMOS transistors. The first input voltage V.sub.in1 and the second input voltage V.sub.in2 are applied to the gates of the PMOS transistors, respectively.

(24) The latch circuit 43A includes a fourth transistor M4 to a ninth transistor M9 having a first channel polarity and a tenth transistor M10 to a thirteenth transistor M13 having a second channel polarity. In the latch circuit 43A, the fourth transistor M4 to the ninth transistor M9 are preferably, for example, PMOS transistors having a P channel polarity and the tenth transistor M10 to the thirteenth transistor M13 are preferably, for example, NMOS transistors having an N channel polarity. The components excluding the eighth transistor M8 and the ninth transistor M9, that is, the fourth transistor M4 to the seventh transistor M7 and the tenth transistor M10 to the thirteenth transistor M13 define an RS flip-flop.

(25) The respective source terminals of the fourth transistor M4 to the ninth transistor M9 are connected to the power supply voltage V.sub.DD. The respective source terminals of the twelfth transistor M12 and the thirteenth transistor M13 are connected to a reference voltage V.sub.SS. The respective drain terminals of the fourth transistor M4, the sixth transistor M6, and the tenth transistor M10 are connected to the first output terminal out1. The respective drain terminals of the fifth transistor M5, the seventh transistor M7, and the eleventh transistor M11 are connected to the second output terminal out2. The source terminal of the tenth transistor M10 and the respective drain terminals of the eighth transistor M8 and the twelfth transistor M12 are interconnected to each other. The source terminal of the eleventh transistor M11 and the respective drain terminals of the ninth transistor M9 and the thirteenth transistor M13 are interconnected to each other. The node x is connected to the respective gates of the fourth transistor M4, the eighth transistor M8, and the twelfth transistor M12. The node y is connected to the respective gates of the fifth transistor M5, the ninth transistor M9, and the thirteenth transistor M13.

(26) With the falling edge timing of the clock signal CLK, the first control signal V.sub.x that returns from the reversal state at a speed corresponding to the magnitude of the first input voltage V.sub.in1 appears at the node x between the first transistor M1 and the first capacitor C.sub.D1. The second control signal V.sub.y that returns from the reversal state at a speed corresponding to the magnitude of the second input voltage V.sub.in2 appears at the node y between the second transistor M2 and the second capacitor C.sub.D2. Accordingly, the voltage difference between the first control signal V.sub.x and the second control signal V.sub.y is a resultant obtained by causing a small number of elements to amplify the difference between the first input voltage V.sub.in1 and the second input voltage V.sub.in2.

(27) That is, with the falling edge timing of the clock signal CLK, the voltages at the nodes x and y exhibit reversals to decrease as shown in FIG. 7B. Subsequently, since the gate potential of the first transistor M1 is higher than the gate potential of the second transistor M2 when the first input voltage V.sub.in1 is higher than the second input voltage V.sub.in2, the current flowing between the source and drain of the first transistor M1 is smaller than the current flowing between the source and drain of the second transistor M2. The first capacitor C.sub.D1 is therefore charged with a smaller current than the second capacitor C.sub.D2. The voltage of the first control signal V.sub.x that appears at the node x is lower than the voltage of the second control signal V.sub.y that appears at the node y as shown in FIG. 7B.

(28) Before the clock signal CLK falls, the voltages at the nodes x and y are at the high level and the first output voltage V.sub.out1 and the second output voltage V.sub.out2 are the result of the last comparison. However, when the voltages at the nodes x and y are brought into the low level with the falling edge timing of the clock signal CLK, the fourth transistor M4 and the fifth transistor M5 are turned on and the twelfth transistor M12 and the thirteenth transistor M13 are turned off in the latch circuit 43A. Accordingly, a node N1 (that is, the first output voltage V.sub.out1) and a node N2 (that is, the second output voltage V.sub.out2) are brought into the high level, so that the latch circuit 43A is reset. At that time, the ON operations of the eighth transistor M8 and the ninth transistor M9 make the drain voltages of the twelfth transistor M12 and the thirteenth transistor M13 high, respectively to fix the potentials of them.

(29) Subsequently, the first capacitor C.sub.D1 and the second capacitor C.sub.D2 are charged with impedances depending on the first input voltage V.sub.in1 and the second input voltage V.sub.in2, respectively, so that a voltage V.sub.y at the node y is higher than a voltage V.sub.x at the node x. Accordingly, the thirteenth transistor M13 approaches the conduction state faster than the twelfth transistor M12 and the fifth transistor M5 approaches the non-conduction state faster than the fourth transistor M4. The voltage at the node N2 approaches the low level faster than the voltage at the node N1. This situation is subjected to positive feedback by the sixth transistor M6, the tenth transistor M10, the seventh transistor M7, and the eleventh transistor M11. As a result, as shown in FIG. 7C, the node N1 (that is, the first output voltage V.sub.outd is stably held at the high level and the node N2 (that is, the second output voltage V.sub.out2) is stably held at the low level. This state is latched by the latch circuit 43A.

(30) The sequence of these operations is performed only with the falling edge timing of the clock signal CLK and is not performed with the rising edge timing of the clock signal CLK. Similar operations are performed with the next falling edge timing of the clock signal CLK. When there is no change in the magnitude relationship between the first input voltage V.sub.in1 and the second input voltage V.sub.in2, the levels of the first output voltage V.sub.out1 and the second output voltage V.sub.out2 are maintained with the rising edge timing of the clock signal CLK as shown in FIG. 7C.

(31) In the comparison circuit 41A according to the first preferred embodiment, the preliminary amplification circuit 42A generates the first control signal V.sub.x and the second control signal V.sub.y with the falling edge timing of the clock signal CLK. The latch circuit 43A compares the first input voltage V.sub.in1 and the second input voltage V.sub.in2 with each other according to the first control signal V.sub.x and the second control signal V.sub.y and latches a result of the comparison. The first control signal V.sub.x and the second control signal V.sub.y generated by the preliminary amplification circuit 42A return from the reversal state at speeds corresponding to the first input voltage V.sub.in1 and the second input voltage V.sub.in2, respectively, so that the latch circuit 43A is latched in a state based on the result of the comparison between the first input voltage V.sub.in1 and the second input voltage V.sub.in2.

(32) After the latch circuit 43A has latched the result of the comparison between the magnitudes of the first input voltage V.sub.in1 and the second input voltage V.sub.in2 with the falling edge timing of the clock signal CLK, the latch circuit 43A holds this latch state until the new first control signal V.sub.x and the new second control signal V.sub.y are input with the next falling edge timing of the clock signal CLK. The result of the comparison between the first input voltage V.sub.in1 and the second input voltage V.sub.in2 which is output from the latch circuit 43A therefore does not change with the rising edge timing of the clock signal CLK. As a result, the comparison circuit 41A can be connected to a logic circuit that operates in response to the same or substantially the same clock signal as the comparison circuit without a half latch circuit at a stage subsequent to the comparison circuit which is needed in the related art.

(33) Since the latch circuit 43A operates in response to the first control signal V.sub.x and the second control signal V.sub.y output from the preliminary amplification circuit 42A, only one type of the clock signal CLK supplied to the preliminary amplification circuit 42A is needed. Accordingly, there is no need to set an appropriate delay time between a first clock signal supplied to a preliminary amplification circuit and a second clock signal supplied to a latch circuit, similar to a comparison circuit in the related art, to sequentially operate the preliminary amplification circuit 42A and the latch circuit 43A with appropriate timings. A problem in the related art in which a through-current increases because of the inappropriate setting of a delay time between clock signals therefore does not arise. Since an excessive through-current does not flow, the power consumption of the comparison circuit 41A can be reduced.

(34) In the comparison circuit 41A according to the first preferred embodiment, the latch circuit 43A includes a small number of elements, the fourth transistor M4 to the ninth transistor M9 that are PMOS transistors and the tenth transistor M10 to the thirteenth transistor M13 that are NMOS transistors.

(35) FIG. 8 is a circuit diagram of a comparison circuit 41B that is a modification of the comparison circuit 41A according to the first preferred embodiment. FIGS. 9A to 9C are timing charts representing voltage changes in respective portions in the comparison circuit 41B shown in FIG. 8. In FIGS. 8 and 9, the same reference numerals are used to identify portions already described with reference to FIGS. 6 and 7 or equivalent portions, and the description thereof will be omitted.

(36) The comparison circuit 41B according to the present modification differs from the comparison circuit 41A according to the first preferred embodiment in the channel polarities of the first transistor M1, the second transistor M2, and the fourth transistor M4 to the thirteenth transistor M13 and the directions of application of the power supply voltage V.sub.DD and the reference voltage V.sub.SS. In addition, the comparison circuit 41B differs from the comparison circuit 41A according to the first preferred embodiment in that the specific change timing of the clock signal CLK is rising edge timing. The remaining configuration of the comparison circuit 41B is the same as, or similar to, the comparison circuit 41A according to the first preferred embodiment.

(37) In the comparison circuit 41A according to the first preferred embodiment, the first transistor M1 and the second transistor M2 in the preliminary amplification circuit 42A are PMOS transistors, the fourth transistor M4 to the ninth transistor M9 in the latch circuit 43A are PMOS transistors, and the tenth transistor M10 to the thirteenth transistor M13 in the latch circuit 43A are NMOS transistors. In the comparison circuit 41B according to the present modification, the first transistor M1 and the second transistor M2 in a preliminary amplification circuit 42B are preferably NMOS transistors, the fourth transistor M4 to the ninth transistor M9 in a latch circuit 43B are preferably NMOS transistors, and the tenth transistor M10 to the thirteenth transistor M13 in the latch circuit 43B are preferably PMOS transistors. The power supply voltage V.sub.DD in the comparison circuit 41A according to the first preferred embodiment is replaced by the reference voltage V.sub.SS in the comparison circuit 41B according to the present modification and the reference voltage V.sub.SS in the comparison circuit 41A according to the first preferred embodiment is replaced by the power supply voltage V.sub.DD in the comparison circuit 41B according to the present modification. With the rising edge timing of the clock signal CLK, the output of the latch circuit 43B is reset to the low level.

(38) In the comparison circuit 41B, the first control signal V.sub.x and the second control signal V.sub.y have waveforms that exhibit returns from the reversal state at speeds corresponding to the first input voltage V.sub.in1 and the second input voltage V.sub.in2 input with the rising edge timing of the clock signal CLK as shown in FIGS. 9(a) and 9(b). The voltages at the nodes x and y exhibit reversals to increase with the rising edge timing of the clock signal CLK. Subsequently, since the gate potential of the first transistor M1 is higher than the gate potential of the second transistor M2 when the first input voltage V.sub.in1 is higher than the second input voltage V.sub.in1, the current flowing between the drain and source of the first transistor M1 is larger than the current flowing between the drain and source of the second transistor M2. The amount of discharge of the first capacitor C.sub.D1 is therefore larger than that of the second capacitor C.sub.D2. The voltage of the first control signal V.sub.x that appears at the node x is lower than the voltage of the second control signal V.sub.y that appears at the node y as shown in FIG. 9B.

(39) Before the clock signal CLK rises, the voltages at the nodes x and y are at the low level and the first output voltage V.sub.out1 and the second output voltage V.sub.out2 are the result of the last comparison. However, when the voltages at the nodes x and y are brought into the high level with the rising edge timing of the clock signal CLK, the fourth transistor M4 and the fifth transistor M5 are turned on and the twelfth transistor M12 and the thirteenth transistor M13 are turned off in the latch circuit 43B. Accordingly, the node N1 (that is, the first output voltage V.sub.out1) and the node N2 (that is, the second output voltage V.sub.out2) are brought into the low level, so that the latch circuit 43B is reset. At that time, the ON operations of the eighth transistor M8 and the ninth transistor M9 make the drain voltages of the twelfth transistor M12 and the thirteenth transistor M13 low, respectively to fix the potentials thereof.

(40) Subsequently, the first capacitor C.sub.D1 and the second capacitor C.sub.D2 are discharged with impedances depending on the first input voltage V.sub.in1 and the second input voltage V.sub.in2, respectively, so that the voltage V.sub.y at the node y is higher than the voltage V.sub.x at the node x. Accordingly, the thirteenth transistor M13 approaches the non-conduction state faster than the twelfth transistor M12 and the fifth transistor M5 approaches the conduction state faster than the fourth transistor M4. The voltage at the node N2 approaches the low level faster than the voltage at the node N1. This situation is subjected to positive feedback by the sixth transistor M6, the tenth transistor M10, the seventh transistor M7, and the eleventh transistor M11. As a result, as shown in FIG. 9C, the node N1 (that is, the first output voltage V.sub.out1) is stably held at the high level and the node N2 (that is, the second output voltage V.sub.out2) is stably held at the low level. This state is latched by the latch circuit 43B.

(41) The sequence of these operations is performed only with the rising edge timing of the clock signal CLK and is not performed with the falling edge timing of the clock signal CLK. Similar operations are performed with the next rising edge timing of the clock signal CLK. When there is no change in the magnitude relationship between the first input voltage V.sub.in1 and the second input voltage V.sub.in2, the levels of the first output voltage V.sub.out1 and the second output voltage V.sub.out2 are maintained with the falling edge timing of the clock signal CLK as shown in FIG. 9C.

(42) With the comparison circuit 41B according to the present modification, an operational effect similar to that obtained with the comparison circuit 41A according to the first preferred embodiment can be obtained.

(43) FIG. 10 is a circuit diagram of a comparison circuit 51A according to a second preferred embodiment of the present invention. In FIG. 10, the same reference numerals are used to identify portions already described with reference to FIG. 6 or equivalent portions, and the description thereof will be omitted.

(44) The comparison circuit 51A differs from the comparison circuit 41A according to the first preferred embodiment only in that a latch circuit 53A includes a fourteenth transistor M14 and a fifteenth transistor M15. The remaining configuration of the comparison circuit 51A is the same as, or similar to, the comparison circuit 41A according to the first preferred embodiment.

(45) The fourteenth transistor M14 includes a gate terminal to which the node x is connected, a drain terminal to which the second output terminal out2 is connected, and a source terminal to which the respective source terminals of the fourth transistor M4 to the seventh transistor M7 are connected. The fifteenth transistor M15 includes a gate terminal to which the node y is connected, a drain terminal to which the first output terminal out1 is connected, and a source terminal to which the respective source terminals of the fourth transistor M4 to the seventh transistor M7 are connected.

(46) In the comparison circuit 41A according to the first preferred embodiment, the first control signal V.sub.x and the second control signal V.sub.y are input from the preliminary amplification circuit 42A to the latch circuit 43A with the falling edge timing of the clock signal CLK, so that the latch circuit 43A is reset. After that, the kickback of an electric charge corresponding to the first output voltage V.sub.out1 and the kickback of an electric charge corresponding to the second output voltage V.sub.out2 are transmitted to the fourth transistor M4 and the fifth transistor M5, respectively. The difference between the kickback of the electric charge transmitted to the fourth transistor M4 and the kickback of the electric charge transmitted to the fifth transistor M5 affects the following amplification operation of the preliminary amplification circuit 42A. That is, the comparison between the first input voltage V.sub.in1 and the second input voltage V.sub.in2 performed by the comparison circuit 41A may be affected by a result of the comparison performed with the last falling edge timing of the clock signal CLK.

(47) However, in the comparison circuit 51A according to the second preferred embodiment, since a voltage based on a result of the last comparison is applied from the second output terminal out2 to the drain terminal of the fourteenth transistor M14, an electric charge based on the result of the last comparison output from the second output terminal out2 exerts an effect upon the node x that is subject to the influence of an electric charge based on a result of the last comparison output from the first output terminal out1 from the fourth transistor M4. Since a voltage based on a result of the last comparison is applied from the first output terminal out1 to the drain terminal of the fifteenth transistor M15, an electric charge based on the result of the last comparison output from the first output terminal out1 exerts an effect upon the node y that is subject to the influence of an electric charge based on a result of the last comparison output from the second output terminal out2 from the fifth transistor M5. Accordingly, each of the nodes x and y is subject to the influences of the results of the last comparison output from the first output terminal out1 and the second output terminal out2.

(48) The voltages output from the first output terminal out1 and the second output terminal out2 as the results of the last comparison are opposite in voltage level. The effects of the results of the last comparison upon the nodes x and y are the same or substantially the same and cancel each other. Accordingly, the first control signal V.sub.x and the second control signal V.sub.y output from the preliminary amplification circuit 42A to the latch circuit 53A with the next falling edge timing of the clock signal CLK reflect the relative reduction in the last comparison result. The comparison between voltages performed by the comparison circuit 51A is therefore less susceptible to the last comparison result. The effect of the last comparison result is reduced.

(49) FIG. 11 is a circuit diagram of a comparison circuit 51B that is a modification of the comparison circuit 51A according to the second preferred embodiment. In FIG. 11, the same reference numerals are used to identify portions already described with reference to FIGS. 8 and 10 or equivalent portions, and the description thereof will be omitted.

(50) The comparison circuit 51B according to the present modification differs from the comparison circuit 51A according to the second preferred embodiment in the channel polarities of the first transistor M1, the second transistor M2, and the fourth transistor M4 to the fifteenth transistor M15 and the directions of application of the power supply voltage V.sub.DD and the reference voltage V.sub.SS. In addition, the comparison circuit 51B differs from the comparison circuit 51A according to the second preferred embodiment in that the specific change timing of the clock signal CLK is the rising edge timing of the clock signal CLK. The remaining configuration of the comparison circuit 51B is the same as, or similar to, the comparison circuit 51A according to the second preferred embodiment.

(51) In the comparison circuit 51A, the first transistor M1 and the second transistor M2 in the preliminary amplification circuit 42A are PMOS transistors, the fourth transistor M4 to the ninth transistor M9, the fourteenth transistor M14, and the fifteenth transistor M15 in the latch circuit 53A are PMOS transistors, and the tenth transistor M10 to the thirteenth transistor M13 in the latch circuit 53A are NMOS transistors. In the comparison circuit 51B according to the present modification, the first transistor M1 and the second transistor M2 in the preliminary amplification circuit 42B are preferably NMOS transistors, the fourth transistor M4 to the ninth transistor M9, the fourteenth transistor M14, and the fifteenth transistor M15 in the latch circuit 53B are preferably NMOS transistors, and the tenth transistor M10 to the thirteenth transistor M13 are preferably PMOS transistors. The power supply voltage V.sub.DD in the comparison circuit 51A according to the second preferred embodiment is replaced by the reference voltage V.sub.SS in the comparison circuit 51B according to the present modification. The reference voltage V.sub.SS in the comparison circuit 51A according to the second preferred embodiment is replaced by the power supply voltage V.sub.DD in the comparison circuit 51B that is this modification. With the rising edge timing of the clock signal CLK, the output of a latch circuit 53B is reset to the low level.

(52) With the comparison circuit 51B according to the present modification, an operational effect similar to that obtained with the comparison circuit 51A according to the second preferred embodiment can be obtained.

(53) FIG. 12 is a circuit diagram of a comparison circuit 61A according to a third preferred embodiment of the present invention. In FIG. 12, the same reference numerals are used to identify portions already described with reference to FIG. 6 or equivalent portions, and the description thereof will be omitted.

(54) The comparison circuit 61A according to the third preferred embodiment differs from the comparison circuit 41A according to the first preferred embodiment only in that a preliminary amplification circuit 62A includes a third transistor M3. The remaining configuration of the comparison circuit 61A is the same as, or similar to, the comparison circuit 41A according to the first preferred embodiment. The third transistor M3 is connected to the node between the first transistor M1 and the second transistor M2. A clock signal is supplied to the gate terminal of the third transistor M3.

(55) FIGS. 13A to 13C are timing charts representing voltage changes in respective portions in the comparison circuit 61A shown in FIG. 12. In FIGS. 13A to 13C, the same reference numerals are used to identify portions already described with reference to FIGS. 7A to 7C or equivalent portions, and the description thereof will be omitted.

(56) In the comparison circuit 61A according to the third preferred embodiment, the third transistor M3 simultaneously operates when the first transistor M1 and the second transistor M2 operate with the falling edge timing of the clock signal CLK. At that time, the voltage at a node B at the drain of the third transistor M3 decreases because of the on-resistance of the third transistor M3 as shown in FIG. 13B. Voltages applied to the respective source terminals of the first transistor M1 and the second transistor M2 therefore decrease. The peak values of a current flowing through the first transistor M1 in accordance with the first input voltage V.sub.in1 and a current instantaneously flowing through the second transistor M2 in accordance with the second input voltage V.sub.in2 with the falling edge timing of the clock signal CLK are therefore significantly reduced. Accordingly, the power consumption of the comparison circuit 61A can be reduced.

(57) FIG. 14 is a circuit diagram of a comparison circuit 61B that is a modification of the comparison circuit 61A according to the third preferred embodiment. FIGS. 15A to 15C are timing charts representing voltage changes in respective portions in the comparison circuit 61B shown in FIG. 14. In FIGS. 14 and 15, the same reference numerals are used to identify portions already described with reference to FIGS. 8, 12, and 13 or equivalent portions, and the description thereof will be omitted.

(58) The comparison circuit 61B according to the present modification differs from the comparison circuit 61A according to the third preferred embodiment in the channel polarities of the first transistor M1 to the thirteenth transistor M13 and the directions of application of the power supply voltage V.sub.DD and the reference voltage V.sub.SS. In addition, the comparison circuit 61B differs from the comparison circuit 61A according to the third preferred embodiment in that the specific change timing of the clock signal CLK is the rising edge timing of the clock signal CLK. The remaining configuration of the comparison circuit 61B is the same as, or similar to, the comparison circuit 61A according to the third preferred embodiment.

(59) In the comparison circuit 61A according to the third preferred embodiment, the first transistor M1 to the third transistor M3 in the preliminary amplification circuit 62A are preferably PMOS transistors, the fourth transistor M4 to the ninth transistor M9 in the latch circuit 43A are preferably PMOS transistors, and the tenth transistor M10 to the thirteenth transistor M13 in the latch circuit 43A are preferably NMOS transistors. In the comparison circuit 61B according to the present modification, the first transistor M1 to the third transistor M3 in a preliminary amplification circuit 62B are preferably NMOS transistors, the fourth transistor M4 to the ninth transistor M9 in the latch circuit 43B are preferably NMOS transistors, the tenth transistor M10 to the thirteenth transistor M13 in the latch circuit 43B are preferably PMOS transistors. The power supply voltage V.sub.DD in the comparison circuit 61A according to the third preferred embodiment is replaced by the reference voltage V.sub.SS in the comparison circuit 61B according to the present modification. The reference voltage V.sub.SS in the comparison circuit 61A according to the third preferred embodiment is replaced by the power supply voltage V.sub.DD in the comparison circuit 61B according to the present modification. With the rising edge timing of the clock signal CLK, the output of the latch circuit 43B is reset to the low level.

(60) In the comparison circuit 61B, the third transistor M3 simultaneously operates when the first transistor M1 and the second transistor M2 operate with the rising edge timing of the clock signal CLK. At that time, the voltage at the node B at the drain of the third transistor M3 increases because of the on-resistance of the third transistor M3 as shown in FIG. 15B. Voltages applied to the respective source terminals of the first transistor M1 and the second transistor M2 therefore decrease. The peak values of a current flowing through the first transistor M1 in accordance with the first input voltage V.sub.in1 and a current instantaneously flowing through the second transistor M2 in accordance with the second input voltage V.sub.in2 with the falling edge timing of the clock signal CLK are therefore significantly reduced. Accordingly, the power consumption of the comparison circuit 61B can be reduced. With the comparison circuit 61B that is a modification, an operational effect similar to that obtained with the comparison circuit 61A according to the third preferred embodiment can be obtained.

(61) FIG. 16 is a circuit diagram of a comparison circuit 71A according to a fourth preferred embodiment of the present invention. In FIG. 16, the same reference numerals are used to identify portions already described with reference to FIGS. 10 and 12 or equivalent portions, and the description thereof will be omitted.

(62) The comparison circuit 71A according to the fourth preferred embodiment differs from the comparison circuit 51A according to the second preferred embodiment only in that the preliminary amplification circuit 62A includes the third transistor M3, similar to the comparison circuit 61A according to the third preferred embodiment. The remaining configuration of the comparison circuit 71A is the same as, or similar to, the comparison circuit 51A according to the second preferred embodiment.

(63) With the comparison circuit 71A according to the fourth preferred embodiment in which the preliminary amplification circuit 62A includes the third transistor M3, an operational effect similar to that obtained with the comparison circuit 61A according to the third preferred embodiment can be obtained.

(64) FIG. 17 is a circuit diagram of a comparison circuit 71B that is a modification of the comparison circuit 71A according to the fourth preferred embodiment of the present invention. In FIG. 17, the same reference numerals are used to identify portions already described with reference to FIGS. 11 and 14 or equivalent portions, and the description thereof will be omitted.

(65) The comparison circuit 71B according to the present modification differs from the comparison circuit 51B according to the modification of the second preferred embodiment only in that the preliminary amplification circuit 62B includes the third transistor M3, similar to the comparison circuit 61B according to the modification of the third preferred embodiment. Another implementation of the comparison circuit 71B is the same as, or similar to, the comparison circuit 51B that is a modification of the second preferred embodiment.

(66) With the comparison circuit 71B according to the present modification in which the preliminary amplification circuit 62B includes the third transistor M3, an operational effect similar to that obtained with the comparison circuit 61A according to the third preferred embodiment can be obtained.

INDUSTRIAL APPLICABILITY

(67) By using the comparison circuits 41A, 41B, 51A, 51B, 61A, 61B, 71A and 71B that are comparison circuits according to the respective preferred embodiments or the above-described modifications in comparators in A/D converters that convert an analog signal into a digital signal, they can contribute to the speedup and lower power consumption of entire systems of digital-analog mixed LSIs.

(68) While preferred embodiments of the present invention have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The scope of the present invention, therefore, is to be determined solely by the following claims.