Stacked III-V semiconductor diode

Abstract

A stacked III-V semiconductor diode having an n.sup. layer having a first surface, a second surface, a dopant concentration of 10.sup.12 N/cm.sup.3 to 10.sup.17 N/cm.sup.3 and a layer thickness of 50 m to 1,000 m, a p.sup.+ layer, which is integrally connected to the first surface and has a dopant concentration of 5.Math.10.sup.18 N/cm.sup.3 to 5.Math.10.sup.20 N/cm.sup.3, an n.sup.+ layer, which is integrally connected to the second surface and has a dopant concentration of at least 10.sup.19 N/cm.sup.3. The p.sup.+ layer, the n.sup. layer and the n.sup.+ layer each having a monolithic design and each being made up of a GaAs compound. The dopant concentration of the n.sup. layer having a first value on the first surface and a second value on the second surface, and the second value of the dopant concentration being greater than the first value at least by a factor between 1.5 and 2.5.

Claims

1. A stacked III-V semiconductor diode comprising: a n.sup. layer having a first surface, a second surface opposite the first surface, a dopant concentration of 10.sup.12 N/cm.sup.3 to 10.sup.17 N/cm.sup.3 and a layer thickness of 50 m to 1,000 m; a p.sup.+ layer integrally connected to the first surface of the n.sup. layer or an intermediate layer disposed between the n.sup. layer and the p.sup.+ layer, the p.sup.+ layer having a dopant concentration of 5.Math.10.sup.18 N/cm.sup.3 to 5.Math.10.sup.20 N/cm.sup.3; a n+ layer integrally connected to the second surface if the n.sup. layer has a dopant concentration of at least 10.sup.19 N/cm.sup.3, wherein the p.sup.+ layer, the n.sup. layer and the n.sup.+ layer each have a monolithic design and include a GaAs compound or consist of a GaAs compound, the n.sup. layer being a GaAs layer, wherein the n.sup.+ layer or the p.sup.+ layer is a substrate layer, wherein the dopant concentration of the n.sup. layer has a first value on the first surface formed in a direction of the p.sup.+ layer and a second value on the second surface adjacent to the n.sup.+ layer, and wherein the second value of the dopant concentration is greater than the first value by a factor of at least 1.5 or by a factor of at least 2 or by a factor of at least 2.5.

2. The stacked III-V semiconductor diode according to claim 1, wherein the dopant concentration of the n.sup. layer has a stepped curve from the first value to the second value in parallel to the layer thickness of the n.sup. layer, the stepped curve including at least one step.

3. The stacked III-V semiconductor diode according to claim 1, wherein the dopant concentration of the n.sup. layer has a continuous curve from the first value to the second value in parallel to the layer thickness of the n.sup. layer.

4. The stacked III-V semiconductor diode according to claim 3, wherein the continuous curve has a constant slope.

5. The stacked III-V semiconductor diode according to claim 1, wherein the p.sup.+ layer is a substrate having a layer thickness of 50 m to 500 m, and the n.sup.+ layer has a layer thickness of less than 30 m.

6. The stacked III-V semiconductor diode according to claim 1, wherein the n.sup.+ layer is a substrate having a layer thickness of 50 m to 400 m, and wherein the p.sup.+ layer has a layer thickness greater than 2 m.

7. The stacked III-V semiconductor diode according to claim 1, wherein the p.sup.+ layer includes zinc.

8. The stacked III-V semiconductor diode according to claim 1, wherein the n.sup.+ layer and/or the n.sup. layer includes chromium and/or silicon and/or palladium and/or tin.

9. The stacked III-V semiconductor diode according to claim 1, wherein a total height of a stacked layer structure, made up of the p.sup.+ layer, the n.sup. layer and the n.sup.+ layer, is no more than 150 m to 500 m.

10. The stacked III-V semiconductor diode according to claim 1, wherein a stacked layer structure, made up of the p.sup.+ layer, the n.sup. layer and the n.sup.+ layer, has a rectangular or square surface with edge lengths between 1 mm and 10 mm, the n.sup.+ layer covering the first contact layer, and the n.sup. layer completely or partially covering the n.sup.+ layer.

11. The stacked III-V semiconductor diode according to claim 1, wherein a stacked layer structure, made up of the p.sup.+ layer, the n.sup. layer and the n.sup.+ layer, has an oval or circular surface, the n.sup.+ layer covering the first contact layer, and the n.sup. layer completely or partially covering the n.sup.+ layer.

12. The stacked III-V semiconductor diode according to claim 1, wherein a semiconductor bond is formed between the p.sup.+ layer and the n.sup. layer or between the intermediate layer and the n.sup. layer.

13. The stacked III-V semiconductor diode according to claim 1, wherein the n+ layer or the p+ layer is a GaAs layer.

14. The stacked III-V semiconductor diode according to claim 1, wherein the n+ layer or the p+ layer is a GaAs layer.

15. A stacked III-V semiconductor diode comprising: a n.sup. layer having a first surface, a second surface opposite the first surface, a dopant concentration of 10.sup.12 N/cm.sup.3 to 10.sup.17 N/cm.sup.3 and a layer thickness of 50 m to 1,000 m; a p.sup.+ layer integrally connected to the first surface of the n.sup. layer or an intermediate layer disposed between the n.sup. layer and the p.sup.+ layer, the p.sup.+ layer having a dopant concentration of 5.Math.10.sup.18 N/cm.sup.3 to 5.Math.10.sup.20 N/cm.sup.3; a n+ layer integrally connected to the second surface if the n.sup. layer has a dopant concentration of at least 10.sup.19 N/cm.sup.3, wherein the p.sup.+ layer, the n.sup. layer and the n.sup.+ layer each have a monolithic design and include a GaAs compound or consist of a GaAs compound, wherein the n.sup.+ layer or the p.sup.+ layer is a substrate layer, wherein the dopant concentration of the n.sup. layer has a first value on the first surface formed in a direction of the p.sup.+ layer and a second value on the second surface adjacent to the n.sup.+ layer, wherein the second value of the dopant concentration is greater than the first value by a factor of at least 1.5 or by a factor of at least 2 or by a factor of at least 2.5, and wherein an intermediate layer is formed between the p.sup.+ layer and the n.sup. layer.

16. A stacked III-V semiconductor diode comprising: a n.sup. layer having a first surface, a second surface opposite the first surface, a dopant concentration of 10.sup.12 N/cm.sup.3 to 10.sup.17 N/cm.sup.3 and a layer thickness of 50 m to 1,000 m; a p.sup.+ layer integrally connected to the first surface of the n.sup. layer or an intermediate layer disposed between the n.sup. layer and the p.sup.+ layer, the p.sup.+ layer having a dopant concentration of 510.sup.18 N/cm.sup.3 to 5.Math.10.sup.20 N/cm.sup.3; a n+ layer integrally connected to the second surface if the n.sup. layer has a dopant concentration of at least 10.sup.19 N/cm.sup.3, wherein the p.sup.+ layer, the n.sup. layer and the n.sup.+ layer each have a monolithic design and the n layer being a GaAs layer, wherein the n.sup.+ layer or the p.sup.+ layer is a substrate layer, wherein the dopant concentration of the n.sup. layer has a first value adjacent to the first surface and a second value on the second surface adjacent to the n.sup.+ layer, and wherein the second value of the dopant concentration is greater than the first value by a factor of at least 1.5 or by a factor of at least 2 or by a factor of at least 2.5.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein:

(2) FIG. 1 shows a schematic view of a first specific embodiment of a stacked III-V semiconductor diode according to the invention;

(3) FIG. 2 shows a schematic top view of a specific embodiment of a stacked III-V semiconductor diode according to the invention;

(4) FIG. 3 shows a schematic view of a specific embodiment of a dopant concentration according to the invention over a layer thickness of an n.sup. layer of a semiconductor diode according to the invention; and

(5) FIG. 4 shows a schematic view of another specific embodiment of a dopant concentration according to the invention over a layer thickness of an n.sup. layer of a semiconductor diode according to the invention.

DETAILED DESCRIPTION

(6) The illustrations in FIGS. 1 and 2 show a side view and a top view of a first specific embodiment of a stacked III-V semiconductor diode 10 according to the invention. Semiconductor diode 10 comprises a stack 100, which includes three semiconductor layers as well as a first contact layer 20 and a second contact layer 22.

(7) The first semiconductor layer is a p.sup.+ layer 12 designed as a substrate, having an upper side, an underside and a dopant concentration of 5.Math.10.sup.18 N/cm.sup.3 to 5.Math.10.sup.20 N/cm.sup.3. The second semiconductor diode is an n.sup. layer 14, which has a first surface 14.1, a second surface 14.2 opposite the first surface, a dopant concentration of 10.sup.12 N/cm.sup.3 to 10.sup.17 N/cm.sup.3 and a layer thickness D2 between 50 and 1000 m. The third semiconductor layer is an n.sup.+ layer 16, which has an upper side, an underside and a dopant concentration of at least 10.sup.19 N/cm.sup.3.

(8) An optional intermediate layer, preferably designed as a p.sup. layer, is not illustrated. The optional intermediate layer is formed between n.sup. layer 14 and p.sup.+ layer 12.

(9) The three semiconductor layers include a GaAs compound or are made up of a GaAs compound. Alternatively, n.sup.+ layer 16 is designed as a substrate on which first n.sup. layer 14 and then the p.sup.+ layer are generated.

(10) First contact layer 20 is disposed on an upper side of n.sup.+ layer 16, i.e. on an upper side of stack 100, and integrally and electrically conductively connected to n.sup.+ layer 16.

(11) Second contact layer 22 is disposed on an underside of p.sup.+ layer 12, i.e. on an underside of stack 100, and integrally and electrically conductively connected to p.sup.+ layer 12.

(12) Stack 100 made up of the three semiconductor layers has a rectangular circumference with a first edge length L1 and a second edge length L2. According to the illustrated exemplary embodiment, contact layers 20 and 22 also have a rectangular design with shorter edge lengths. n+ layer 16 surrounds first contact layer 20 and completely or partially covers n.sup. layer 14. p.sup.+ layer 12 has a dopant concentration K1, dopant concentration K1 having an essentially constant value in the range of 5.Math.10.sup.18-5.Math.10.sup.20 N/cm.sup.3 within the entire layer.

(13) n.sup.+ layer 12 has a dopant concentration K3, which also has an essentially constant value within the entire layer. The value of dopant concentration K3 of n.sup.+ layer 12 is at least 10.sup.19 N/cm.sup.3.

(14) In contrast, n.sup. layer 14 has a varying dopant concentration K2. Dopant concentration K2 of n.sup. layer 14 has a first value W1 on first surface 14.1 of n.sup. layer 14 adjacent to p.sup.+ layer 12 and a second value W2 on second surface 14.2 of n.sup. layer 14 adjacent to n.sup.+ layer 16, first value W1 and second value W2 both being in a range from 10.sup.12 N/cm.sup.3 to 10.sup.17 N/cm.sup.3, and second value W2 of dopant concentration K1 being greater than first value W1 by a factor between 1.5 and 2.5. Dopant concentration K2 of n.sup. layer 14 thus increases along layer thickness D2 of n.sup. layer 14.

(15) In the illustration in FIG. 3, a curve of dopant concentration K2 of p.sup. layer 14 in parallel to layer thickness D2 of n.sup. layer 14 is illustrated schematically according to a first specific embodiment. Dopant concentration K2 of n.sup. layer 14 has first value W1 on first surface 14.1, whose position is marked as x1, and second value W2 on second surface 14.2, whose position is market x2. Dopant concentration K2 increases in a stepped manner between first surface 14.1 and second surface 14.2, or between positions x1 and x2, i.e. dopant concentration K2 has a stepped curve, the stepped curve in the illustrated exemplary embodiment having three steps.

(16) For example, first value W1 is 5.Math.10.sup.14 N/cm.sup.3, and second value W2 is 1.Math.10.sup.16 N/cm.sup.3.

(17) In the illustration in FIG. 4, an alternative curve of dopant concentration K2 of n.sup. layer 14 in parallel to layer thickness D2 of n.sup. layer 14 is illustrated schematically according to a first specific embodiment. The dopant concentration increases between first value W1 and second value W2 along layer thickness D2 continuously and with a constant slope, i.e. dopant concentration K2 of n.sup. layer 14 has a continuous curve with a constant slope.

(18) The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims: