METHOD FOR DESIGNING AN APPLICATION TASK ARCHITECTURE OF AN ELECTRONIC CONTROL UNIT WITH ONE OR MORE VIRTUAL CORES

Abstract

Disclosed is a method for designing an application task architecture for an electronic control unit based on an AUTOSAR operating system that is adaptable to a plurality of microcontrollers. Prior to association with a microcontroller, the method involves developing the application task architecture by using at least one virtual core different from the one or more cores of the microcontroller, the various tasks being assigned respectively to the at least one virtual core, and associating the at least one virtual core with the one or more cores of the microcontroller so as to allocate tasks assigned to the at least one virtual core to the core or among the cores of the microcontroller.

Claims

1. A method for designing an application task architecture for an electronic control unit (1) based on an AUTOSAR operating system that is adaptable to a plurality of microcontrollers (5, 5a), including one or more cores (C0, C1, C2) as processing members working in parallel for the execution of various tasks (T10-T14, T20-T24, T30-T34) of the operating system by the electronic control unit (1), a basic software layer being used to connect with a selected microcontroller (5, 5a) forming part of the electronic control unit (1), various tasks (T10-T14, T20-T24, T30-T34) of the operating system to be executed by the electronic control unit (1) being allocated by the application task architecture to the one or more cores (C0, C1, C2) of the selected microcontroller (5, 5a), wherein, prior to association with a selected microcontroller (5, 5a), the method involves developing the application task architecture by using at least one virtual core (A0, A1, A2) different from the one or more cores (C0, C1, C2) of the microcontroller (5, 5a), the various tasks (T10-T14, T20-T24, T30-T34) being assigned respectively to said at least one virtual core (A0, A1, A2), and associating said at least one virtual core (A0, A1, A2) with the one or more cores (C0, C1, C2) of the selected microcontroller (5, 5a) so as to allocate tasks (T10-T14, T20-T24, T30-T34) assigned to said at least one virtual core (A0, A1, A2) to the core or among the cores (C0, C1, C2) of the selected microcontroller (5, 5a).

2. The design method as claimed in claim 1, wherein the selected microcontroller (5, 5a) is a multicore (C0, C1, C2) microcontroller, the application task architecture comprising a plurality of virtual cores (A0, A1, A2).

3. The design method as claimed in claim 2, wherein the tasks (T10-T14, T20-T24, T30-T34) assigned to a virtual core (A0, A1, A2) are allocated to one and the same core (C0, C1, C2) of the selected microcontroller (5, 5a).

4. The design method as claimed in claim 2, wherein, when the selected microcontroller (5, 5a) comprises at least two separate groups of cores (C0, C1, C2) connected by a bridge, a group of virtual cores (A0, A1, A2) is produced for each group of cores (C0, C1, C2) of the microcontroller (5, 5a), the groups of virtual cores (A0, A1, A2) being independent of one another.

5. The design method as claimed in claim 2, wherein, when the selected microcontroller (5, 5a) comprises at least one core having secure and non-secure portions, forming a checker core (C0 or C1), a virtual core (A0) is designated to be associated with this checker core (C0 or C1) of the selected microcontroller (5, 5a).

6. A method for integrating a multicore microcontroller (5, 5a) into an electronic control unit (1) based on an AUTOSAR operating system comprising a basic software layer (4) designed in accordance with a design method as claimed in claim 1, wherein, for each core (C0, C1, C2) of the microcontroller (5, 5a), the core's characteristics are determined in relation to the core's capability to carry out a control through redundant execution of the software, the core's security level, the core's capability to start up the microcontroller (5, 5a), the core's capability to access input and output peripherals of the microcontroller, and each core (C0, C1, C2) of the microcontroller (5, 5a) is associated with the virtual core (A0, A1, A2) to which the core is closest in terms of characteristics.

7. The integration method as claimed in claim 6, wherein an order of priority among the characteristics is established, the capability of carrying out a control being highest priority.

8. The integration method as claimed in claim 6, wherein a core affinity is established both for a virtual core and for a core of the microcontroller, the affinity relating to the integration onto a real core of the microcontroller, the integration onto a virtual core, the integration onto one and the same core as a given task, the integration onto a core on which the checker core is active or which is the preferred core for access to the peripherals or a core with a given level of security.

9. An electronic control unit (1) based on an AUTOSAR operating system comprising an application software layer (2), a basic software layer (4) and a microcontroller (5, 5a), an application task architecture, integrated into the application software layer (2), the basic software layer (4) being used to connect with the microcontroller (5, 5a) forming part of the electronic control unit (1), various tasks (T10-T14, T20-T24, T30-T34) to be performed by the electronic control unit (1) being allocated by the application task architecture to one or more cores (C0, C1, C2) of the microcontroller (5, 5a), wherein the application task architecture of the electronic control unit (1) is designed in accordance with a method as claimed in claim 1.

10. The electronic control unit (1) as claimed in claim 9, wherein the microcontroller (5, 5a) comprises three cores (C0, C1, C2).

11. A motor vehicle comprising at least one electronic control unit (1) based on an AUTOSAR operating system as claimed in claim 9.

12. The method as claimed in claim 3, wherein, when the selected microcontroller (5, 5a) comprises at least two separate groups of cores (C0, C1, C2) connected by a bridge, a group of virtual cores (A0, A1, A2) is produced for each group of cores (C0, C1, C2) of the microcontroller (5, 5a), the groups of virtual cores (A0, A1, A2) being independent of one another.

13. The design method as claimed in claim 3, wherein, when the selected microcontroller (5, 5a) comprises at least one core having secure and non-secure portions, forming a checker core (C0 or C1), a virtual core (A0) is designated to be associated with this checker core (C0 or C1) of the selected microcontroller (5, 5a).

14. The design method as claimed in claim 4, wherein, when the selected microcontroller (5, 5a) comprises at least one core having secure and non-secure portions, forming a checker core (C0 or C1), a virtual core (A0) is designated to be associated with this checker core (C0 or C1) of the selected microcontroller (5, 5a).

15. The integration method as claimed in claim 7, wherein a core affinity is established both for a virtual core and for a core of the microcontroller, the affinity relating to the integration onto a real core of the microcontroller, the integration onto a virtual core, the integration onto one and the same core as a given task, the integration onto a core on which the checker core is active or which is the preferred core for access to the peripherals or a core with a given level of security.

16. An electronic control unit (1) based on an AUTOSAR operating system comprising an application software layer (2), a basic software layer (4) and a microcontroller (5, 5a), an application task architecture, integrated into the application software layer (2), the basic software layer (4) being used to connect with the microcontroller (5, 5a) forming part of the electronic control unit (1), various tasks (T10-T14, T20-T24, T30-T34) to be performed by the electronic control unit (1) being allocated by the application task architecture to one or more cores (C0, C1, C2) of the microcontroller (5, 5a), wherein the application task architecture of the electronic control unit (1) is designed in accordance with a method as claimed in claim 2.

17. An electronic control unit (1) based on an AUTOSAR operating system comprising an application software layer (2), a basic software layer (4) and a microcontroller (5, 5a), an application task architecture, integrated into the application software layer (2), the basic software layer (4) being used to connect with the microcontroller (5, 5a) forming part of the electronic control unit (1), various tasks (T10-T14, T20-T24, T30-T34) to be performed by the electronic control unit (1) being allocated by the application task architecture to one or more cores (C0, C1, C2) of the microcontroller (5, 5a), wherein the application task architecture of the electronic control unit (1) is designed in accordance with a method as claimed in claim 3.

18. An electronic control unit (1) based on an AUTOSAR operating system comprising an application software layer (2), a basic software layer (4) and a microcontroller (5, 5a), an application task architecture, integrated into the application software layer (2), the basic software layer (4) being used to connect with the microcontroller (5, 5a) forming part of the electronic control unit (1), various tasks (T10-T14, T20-T24, T30-T34) to be performed by the electronic control unit (1) being allocated by the application task architecture to one or more cores (C0, C1, C2) of the microcontroller (5, 5a), wherein the application task architecture of the electronic control unit (1) is designed in accordance with a method as claimed in claim 4.

19. An electronic control unit (1) based on an AUTOSAR operating system comprising an application software layer (2), a basic software layer (4) and a microcontroller (5, 5a), an application task architecture, integrated into the application software layer (2), the basic software layer (4) being used to connect with the microcontroller (5, 5a) forming part of the electronic control unit (1), various tasks (T10-T14, T20-T24, T30-T34) to be performed by the electronic control unit (1) being allocated by the application task architecture to one or more cores (C0, C1, C2) of the microcontroller (5, 5a), wherein the application task architecture of the electronic control unit (1) is designed in accordance with a method as claimed in claim 5.

20. An electronic control unit (1) based on an AUTOSAR operating system comprising an application software layer (2), a basic software layer (4) and a microcontroller (5, 5a), an application task architecture, integrated into the application software layer (2), the basic software layer (4) being used to connect with the microcontroller (5, 5a) forming part of the electronic control unit (1), various tasks (T10-T14, T20-T24, T30-T34) to be performed by the electronic control unit (1) being allocated by the application task architecture to one or more cores (C0, C1, C2) of the microcontroller (5, 5a), wherein the microcontroller (5, 5a) has been integrated into the electronic control unit (1) in accordance with an integration method as claimed in claim 6.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Other features, aims and advantages of the present invention will become apparent on reading the detailed description that follows and on examining the appended drawings given by way of non-limiting examples, and in which:

[0041] FIG. 1 is a schematic representation of a cross-sectional view of an electronic control unit based on an AUTOSAR operating system that may be used in the context of the present invention;

[0042] FIG. 2 is a schematic representation of a cross-sectional view of an application task architecture forming part of an electronic control unit based on an AUTOSAR operating system according to the invention, two microcontrollers being shown with this application task architecture including virtual cores.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0043] In what follows, the microcontroller illustrated in the figures and described below comprises three cores. This is not limiting and the present invention may relate to a single-core microcontroller or a multicore microcontroller with a number of cores other than three.

[0044] The mention of a core without qualification refers to a real core of the microcontroller.

[0045] With reference to FIGS. 1 and 2, the present invention relates to a method for designing an application task architecture for an electronic control unit 1 based on an AUTOSAR operating system that is adaptable to a plurality of microcontrollers 5, 5a, a microcontroller 5, 5a being selected to be associated with the software portion of the electronic control unit 1 based on an AUTOSAR operating system formed by the application software layer 2 integrating the application task architecture, the basic software layer 4 and the runtime environment layer 3.

[0046] The basic software layer 4 may include system services, namely the electronic control unit 1, memories, communication services. The basic software layer 4 includes a module for abstraction of the onboard system, a module for abstraction of communication with the microcontroller 5, 5a and a module for abstraction of the microcontroller 5, 5a in terms of input and output communication.

[0047] These abstraction modules are different from the virtual cores A0, A1, A2 proposed by the invention which will be described later, being in the application task architecture integrated into the application software layer 2. The basic software layer 4 also includes microcontroller 5, 5a drivers, memory drivers, communication drivers and input and output communication drivers.

[0048] The microcontroller 5, 5a includes one or more cores C0, C1, C2 as processing members working in parallel for the processing of various tasks T10-T14, T20-T24, T30-T34 by the electronic control unit 1. The references T10-T14, T20-T24, T30-T34 group together each of the different tasks. Five tasks are shown per core in FIG. 2, but this number is not limiting and may be higher or lower.

[0049] The tasks form, per core, sets of tasks with well defined properties. Relationships between the tasks may be established for certain tasks, such as parallel, or conversely chained, executions.

[0050] As mentioned above, the application task architecture is used to connect with the selected microcontroller 5, 5a forming part of the electronic control unit 1, various tasks T10-T14, T20-T24, T30-T34 to be executed by the electronic control unit 1 being allocated by the application task architecture to the one or more cores C0, C1, C2 of the selected microcontroller 5, 5a.

[0051] According to the invention, prior to association with a selected microcontroller 5, 5a, when designing the software architecture for the electronic control unit 1 based on an AUTOSAR operating system, the method involves developing the application task architecture by using at least one virtual core A0, A1, A2 different from the one or more cores C0, C1, C2 of the microcontroller 5, 5a. This allows abstraction of the one or more cores C0, C1, C2 of the microcontroller 5, 5a.

[0052] With reference to FIG. 2, the various tasks T10-T14, T20-T24, T30-T34 to be distributed to the one or more cores C0, C1, C2 of the microcontroller 5, 5a are assigned respectively to the one or more virtual cores A0, A1, A2. It follows that the application task architecture is initially developed completely independently of the cores C0, C1, C2 of the microcontroller. This makes it possible to build an application task architecture which will remain common to all of the different microcontrollers 5, 5a and which will not need to be re-updated when the application task architecture has to be adapted to another microcontroller 5, 5a with the same number of cores C0, C1, C2 as the microcontroller 5, 5a for which the application task architecture was developed.

[0053] A generic architecture is thus created which gives an insight into the validity of the portion relative to the application software layer 2 and to the application task architecture.

[0054] Next, the one or more virtual cores A0, A1, A2 are associated with the one or more cores C0, C1, C2 of the selected microcontroller 5, 5a so as to allocate tasks T10-T14, T20-T24, T30-T34 previously assigned to said at least one virtual core A0, A1, A2 to the core or among the cores C0, C1, C2 of the selected microcontroller 5, 5a. A virtual core A0, A1, A2 corresponds to a core of the microcontroller C0, C1, C2.

[0055] The present invention makes it possible to share the same application task architecture between electronic control units 1 with different microcontrollers 5, 5a having cores C0, C1, C2 exhibiting different properties, for example not having the same security level.

[0056] The virtual cores A0, A1, A2 may be used when integrating different applications into a system with one core or with a plurality of multiple cores C0, C1, C2, which may be achieved according to the invention independently of the microcontroller 5, 5a used.

[0057] In FIG. 2, which illustrates the non-limiting case of two microcontrollers 5, 5a with three cores C0, C1, C2, tasks T10-T14, T20-T24, T30-T34 have been distributed across three virtual cores A0, A1, A2. Two microcontrollers 5, 5a are shown with different distributions of real cores C0, C1, C2 for accomplishing these tasks T10-T14, T20-T24, T30-T34. The virtual cores A0, A1, A2 will therefore not be associated with the same arrangement of real cores C0, C1, C2 in the two cases but with the real core which best matches a specific virtual core A0, A1, A2 and which may occupy a different position in the arrangement of the three cores C0, C1, C2 in the given microcontroller 5, 5a.

[0058] The virtual core A0 may correspond to a high-security core that is able to perform the function of checker core. The remaining two other virtual cores bear the references A1 and A2.

[0059] Solely by way of non-limiting illustration, for a first microcontroller with the reference 5, the checker core is the core with the reference C0, which is also used to start up the microcontroller 5, while for a second microcontroller with the reference 5a, the checker core is the core with the reference C1, different from the startup core which is the core C0. Therefore, for this second microcontroller 5a, it is the core C1 which is associated with the virtual core A0. Adapting the application task architecture implemented for the first microcontroller 5 to the second microcontroller 5a only requires making provision for a modification in the step of associating the virtual cores A0, A1, A2 with a respective core C0, C1, C2 of the microcontroller 5, 5a, the rest of the architecture being retained, which is a substantial advantage afforded by the present invention.

[0060] There may be microcontrollers with the possibility of selecting a checker core from among a plurality of cores capable of performing this role, the user having this possibility to make a selection. The checker core selected in this way is associated with the virtual core dedicated to checking.

[0061] As a non-limiting example of a set of virtual cores A0, A1, A2 adapted to a specific microcontroller 5, 5a, reference may be made to a virtual core A0 made input- and output-secure with secure partitions or otherwise, a non-secure virtual communication core and a non-secure alternative core, which correspond, respectively, to real cores of a triple-core microcontroller 5, 5a, which is a non-limiting example of a multicore microcontroller 5, 5a in the context of the present invention.

[0062] Thus, when the selected microcontroller 5, 5a has multiple cores C0, C1, C2, the application task architecture may comprise a plurality of virtual cores A0, A1, A2, with the same number of virtual cores A0, A1, A2 as cores C0, C1, C2 of the microcontroller 5, 5a. The tasks T10-T14, T20-T24, T30-T34 assigned to a virtual core A0, A1, A2 may be assigned to the same core C0, C1, C2 of the selected microcontroller 5, 5a.

[0063] Increasing numbers of microcontrollers 5, 5a have groups of cores C0, C1, C2 working in parallel. When the microcontroller 5, 5a selected to form part of the electronic control unit 1 based on an AUTOSAR operating system comprises at least two separate groups of cores C0, C1, C2 connected by a bridge, a group of virtual cores A0, A1, A2 is produced for each group of cores C0, C1, C2 of the microcontroller 5, 5a, the groups of virtual cores A0, A1, A2 being independent of one another. For example, for n or more groups of three cores C0, C1, C2 in a microcontroller 5, 5a, groups A0, A1, A2, then B0, B1, B2 and so on until the nth letter may be produced, which is not shown in FIG. 2.

[0064] A virtual core A0, A1, A2 may therefore be defined by two characters. The first character, for example A, indicates, in a non-limiting manner, the domain of application, while the second character is the number associated with the virtual core A0, A1, A2 in its domain of application, for example from 1 to 3, which is non-limiting.

[0065] The tasks T10-T14, T20-T24, T30-T34 may be classified as acquisition tasks with communication between the application task architecture and the application software layer 2 such as acquisitions and associated diagnostics or commands passing from the application layer to the basic layer 4, for example information on new data from the application layer 2 transmitted to the basic layer 4. In practice, one and the same task may contain both command control and acquisition.

[0066] Tasks T10-T14, T20-T24, T30-T34 may be distributed across a plurality of virtual cores A0, A1, A2. The tasks T10-T14, T20-T24, T30-T34 may be classed according to their periodic or random character or according to their durations of execution and distributed across the virtual cores A0, A1, A2 according to these criteria.

[0067] When the selected microcontroller 5, 5a comprises at least one core C0 or C1 having secure and non-secure portions, a first virtual core A0 may be designated to be associated with this secure core C0 or C1 of the selected microcontroller 5, 5a, this first virtual core being the core A0 previously illustrated in FIG. 2 virtually having secure and non-secure portions. Such a virtual core A0 may therefore be associated with a checker core in the microcontroller.

[0068] The invention also relates to a method for integrating a multicore microcontroller 5, 5a into an electronic control unit 1 based on an AUTOSAR operating system comprising an application task architecture designed in accordance with such a design method.

[0069] For each core C0, C1, C2 of the microcontroller 5, 5a, its characteristics in relation to its capability to carry out a control through parallel execution of the simultaneous identical tasks T10-T14, T20-T24, T30-T34, its security level, its capability to start up the microcontroller 5, 5a and its capability for input and output communication with the application task architecture are determined.

[0070] This corresponds to the specifications given by the supplier of the microcontroller 5, 5a. The supplier may propose several combinations of specific cores for one and the same microcontroller, the user of the microcontroller being able to choose one core from a plurality of cores capable of becoming a checker core, a startup core or an input and output communication core.

[0071] With each core C0, C1, C2 of the microcontroller 5, 5a, a virtual core A0, A1, A2 to which it is closest in terms of characteristics is associated, each virtual core A0, A1, A2 having been virtually designed to virtually include such characteristics as are required for the operation of the microcontroller.

[0072] From among all of these characteristics, an order of priority among the characteristics may be established, the capability of carrying out a control being highest priority. For example, in FIG. 2, the core C0 of the first microcontroller 5 is secure and capable of performing the function of checker core, but it is also capable of starting up the microcontroller 5, while the core C1 of the second microcontroller 5a is secure and capable of performing the function of checker core, but it is not capable of performing startup. Association with a virtual core A0, A1, A2 will be carried out for both cores C0, C1, C2 of the two microcontrollers 5, 5a with a secure virtual core A0 having priority.

[0073] For any functionality to be integrated, there is the possibility to specify, in the design phase, a core affinity, the core being able to be virtual or real.

[0074] This core affinity will be verified, in a tool-based manner, when integrating onto the various projects.

[0075] For example, the core affinity may be expressed in various ways such as the integration onto a real core of the microcontroller, the integration onto a virtual core, the integration onto one and the same core as a given function, the integration onto a core on which the checker core is active or which is the preferred core for access to the peripherals or a core with a given level of security, etc.

[0076] This last formulation is the most advantageous since it is based on an abstraction principle, being positioned in relation to a characteristic of the core instead of in relation to a given core. The invention lastly relates to an electronic control unit 1 based on an AUTOSAR operating system comprising an application software layer 2 integrating an application task architecture and a microcontroller 5 or 5a, the application task architecture being used for the integration of the microcontroller 5 or 5a into the the electronic control unit 1, various tasks T10-T14, T20-T24, T30-T34 to be performed by the electronic control unit 1 being allocated by the application task architecture to one or more cores C0, C1, C2 of the microcontroller 5 or 5a.

[0077] The application task architecture for the electronic control unit 1 is designed in accordance with a design method such as described above in which the microcontroller 5, 5a has been integrated into the electronic control unit 1 based on an AUTOSAR operating system in accordance with an integration method such as described above.