THERMALLY PROTECTED VARISTOR

Abstract

A thermally protected varistor includes a varistor chip, a temperature fuse, and a lead line, wherein the varistor chip includes a first conductive layer and a second conductive layer, and the lead line includes a first lead line, a second lead line, and a third lead line. One end of the first lead line is connected to the first conductive layer, and the other end of the first lead line is led out. A first end of the temperature fuse is led out as the second lead line, and a second end of the temperature fuse is connected to the second conductive layer. One end of the third lead line is connected to the second conductive layer, and the other end of the third lead line is led out. The temperature fuse is an axial temperature fuse and is tightly attached to the varistor chip.

Claims

1. A thermally protected varistor, comprising a varistor chip, a temperature fuse, and a lead line, wherein the varistor chip comprises a first conductive layer and a second conductive layer, and the lead line comprises a first lead line, a second lead line and a third lead line; a first end of the first lead line is connected to the first conductive layer, and a second end of the first lead line is led out; a first end of the temperature fuse is led out as the second lead line, and a second end of the temperature fuse is connected to the second conductive layer; a first end of the third lead line is connected to the second conductive layer, and a second end of the third lead line is led out; and the temperature fuse is tightly attached to the varistor chip.

2. The thermally protected varistor according to claim 1, wherein, the varistor chip is square.

3. The thermally protected varistor according to claim 1, wherein, the third lead line and the temperature fuse are connected to different positions of the second conductive layer.

4. The thermally protected varistor according to claim 1, wherein, the third lead line and the temperature fuse are soldered to each other and are connected to a same position of the second conductive layer.

5. The thermally protected varistor according to claim 4, wherein, a welding place of the third lead line and the temperature fuse is flat.

6. The thermally protected varistor according to claim 1, wherein, the second end of the temperature fuse is integrated with the third lead line.

7. The thermally protected varistor according to claim 1, wherein, the second lead line is directly led out in a straight line.

8. The thermally protected varistor according to claim 1, wherein, the second lead line is led out at a right angle around two adjacent side surfaces of the varistor chip.

9. The thermally protected varistor according to claim 1, wherein, a packaging material covers the varistor chip and the temperature fuse, and the lead line is led out from the packaging material as a pin.

10. The thermally protected varistor according to claim 9, wherein, the packaging material is provided with a visible window on the temperature fuse, an insulating outer casing is transparent or translucent, and a state of a fusible alloy is observed through the visible window.

11. The thermally protected varistor according to claim 9, wherein, a casing is arranged at an outside of the packaging material.

12. The thermally protected varistor according to claim 11, wherein, a thermally insulating member is arranged between the packaging material and the casing.

13. The thermally protected varistor according to claim 1, wherein, the varistor chip comprises an upper end surface, a lower end surface opposite to the upper end surface in a thickness direction, and a side end surface connecting the upper end surface and the lower end surface; and the temperature fuse is tightly attached to the side end surface of the varistor chip.

14. The thermally protected varistor according to claim 2, wherein, the third lead line and the temperature fuse are connected to different positions of the second conductive layer.

15. The thermally protected varistor according to claim 2, wherein, the third lead line and the temperature fuse are soldered to each other and are connected to a same position of the second conductive layer.

16. The thermally protected varistor according to claim 2, wherein, the second end of the temperature fuse is integrated with the third lead line.

17. The thermally protected varistor according to claim 2, wherein, the second lead line is directly led out in a straight line.

18. The thermally protected varistor according to claim 2, wherein, the second lead line is led out at a right angle around two adjacent side surfaces of the varistor chip.

19. The thermally protected varistor according to claim 2, wherein, a packaging material covers the varistor chip and the temperature fuse, and the lead line is led out from the packaging material as a pin.

20. The thermally protected varistor according to claim 1, wherein, the temperature fuse is an axial temperature fuse.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG. 1 is a schematic diagram showing the structure of a thermally protected varistor according to Embodiment 1 of the present invention;

[0023] FIG. 2 is a schematic diagram showing the structure of a thermally protected varistor according to Embodiment 2 of the present invention; and

[0024] FIG. 3 is a schematic diagram showing the structure of a thermally protected varistor according to Embodiment 3 of the present invention.

[0025] In the figures: [0026] 1. Varistor chip [0027] 11. First conductive layer [0028] 12. Second conductive layer [0029] 2. Temperature fuse [0030] 21. Fusible alloy [0031] 22. Fluxing agent [0032] 23. Insulating outer casing [0033] 24. Sealing resin [0034] 3. Packaging material [0035] 4. Lead line [0036] 41. First lead line [0037] 42. Second lead line [0038] 43. Third lead line

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0039] The present invention is further described in detail below with reference to the embodiments and the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention, and should not be regarded as specific limitations on the present invention.

Embodiment 1

[0040] As shown in FIG. 1, a thermally protected varistor includes the square varistor chip 1, and the varistor chip 1 includes the first conductive layer 11 and the second conductive layer 12. The lead line 4 is provided for connecting and leading out, wherein the lead line includes the first lead line 41, the second lead line 42 and the third lead line 43. One end of the first lead line 41 is soldered to the first conductive layer 11 of the varistor chip 1, and the other end of the first lead line 41 is led out as a pin. The axial temperature fuse 2 is tightly attached to an upper end surface of the varistor chip 1, and includes the fusible alloy 21. The fluxing agent 22 is coated on the outside of the fusible alloy 21. The fusible alloy 21 and the fluxing agent 22 are wrapped by the insulating outer casing 23 made of glass. The insulating outer casing 23 is sealed with the sealing resin 24. The first end of the temperature fuse 2 extends at a right angle along a right side end surface of the varistor chip 1 as the second lead line 42, and extends out from a lower side surface of the varistor chip 1 as a pin. This arrangement can increase the length of the second electrode 42 led out from the temperature fuse 2 without increasing the volume of the product. In this way, the safety of the product through wave soldering can be improved. The second end of the temperature fuse 2 and the third lead line 43 are welded together, and are welded to the second conductive layer 12 together.

[0041] The packaging material 3 covers the varistor chip 1 and the temperature fuse 2, and is provided with a notch at the temperature fuse 2 as a visible window. The temperature fuse can be directly observed through the notch, and the conditions of the fusible alloy 21 are observed through the transparent insulating outer casing. The first lead line 41, the second lead line 42 and the third lead line 43 are led out from the packaging material 3 as pins, respectively. A current flows from the first lead line 41 through the varistor chip 1 by the first conductive layer 11, and after the current flows out of the second conductive layer 12, a part of the current is led out through the third lead line 43, and a part of the current flows to the temperature fuse 2 and then is led out through the second lead line 42.

Embodiment 2

[0042] As shown in FIG. 2, the structure of the thermally protected varistor is substantially similar to that of Embodiment 1, except that the second end of the temperature fuse 2 is integrated with the third lead line 43. The third lead line 43 obliquely crosses the upper surface of the varistor chip 1 and is tightly attached to the upper surface of the varistor chip 1.

Embodiment 3

[0043] As shown in FIG. 3, the structure of the thermally protected varistor is substantially similar to that of Embodiment 2, except that the temperature fuse 2 is tightly attached to the right end surface of the varistor chip 1. One end of the second lead line 42 is soldered to the temperature fuse 2, and the other end of the second lead line 42 is directly led out of the lower side of the varistor chip 1 in a straight line as a pin.

[0044] It should be understood that the above embodiments of the present invention are merely examples for clearly illustrating the present invention, rather than limiting the implementations of the present invention. For those of ordinary skill in the art, based on the above description, other variations or changes in different forms can also be made. It is not possible to exhaustively list all implementations herein. Any obvious variations or changes derived from the technical solutions of the present invention shall fall within the scope of protection of the present invention.