Method of determining thermal impedance of a sintering layer and a measurement system

Abstract

Some embodiments are directed to a method of determining a sintering thermal impedance of a sintering layer by: providing a substrate having a predetermined substrate thermal impedance and disposing the sintering layer on the substrate forming with the sintering layer a stack. Placing at least one semiconductor die, that includes a semiconductor element with at least two element electrodes on the sintering layer. Injecting an electrical current through the at least two element electrodes for measuring a temperature sensitive parameter of the semiconductor element. Heating the stack with a predetermined heat power and determining, while sintering, a semiconductor element temperature from the measured temperature sensitive parameter. Measuring a stack temperature and determining a stack thermal impedance by subtracting the semiconductor element temperature from the stack temperature and dividing by the predetermined heat power, and subtracting the predetermined substrate thermal impedance from the stack thermal impedance.

Claims

1. A method of determining a sintering thermal impedance of a sintering layer, the method comprising: providing a substrate having a predetermined substrate thermal impedance, disposing the sintering layer on the substrate, the substrate and the sintering layer forming a stack, placing at least one semiconductor die on the sintering layer, the semiconductor die having a semiconductor element which includes at least two element electrodes, injecting an electrical current through the at least two element electrodes for measuring a temperature sensitive parameter of the semiconductor element, heating the stack for sintering the sintering layer with a predetermined heat power, determining, while sintering, a semiconductor element temperature from the measured temperature sensitive parameter, measuring a stack temperature, determining a stack thermal impedance by subtracting the semiconductor element temperature from the stack temperature to obtain a temperature difference and dividing the temperature difference by the predetermined heat power, and determining the sintering thermal impedance by subtracting the predetermined substrate thermal impedance from the stack thermal impedance.

2. The method according to claim 1, wherein the substrate is at least partially electrically conductive and includes a substrate electrode, and wherein injecting the electrical current is performed via the substrate electrode by electrically coupling one of the element electrodes to the substrate electrode via the sintering layer.

3. The method according to claim 1, wherein while heating the stack, a compression force is applied on semiconductor die against the substrate.

4. The method according to claim 1, wherein measuring the stack temperature includes directly measuring a substrate temperature at a front side of the substrate where the sintering layer is disposed or at a back side of the substrate opposite to a front side of the substrate where the sintering layer is disposed.

5. The method according to claim 1, wherein measuring the stack temperature includes using a thermocouple having a sensing temperature electrode thermally coupled to the substrate.

6. The method according to claim 1, further including placing a further semiconductor die on the sintering layer, the further semiconductor die including a further semiconductor element including at least two corresponding further element electrodes for injecting a current therein and measuring a corresponding further temperature sensitive parameter of the further semiconductor element.

7. The method according to claim 6, further comprising: determining, while sintering, a further semiconductor element temperature from the measured further temperature sensitive parameter, determining a further stack thermal impedance by subtracting the further semiconductor element temperature from the stack temperature and dividing by the predetermined heat power, and determining the further sintering thermal impedance by subtracting the predetermined substrate thermal impedance from the further stack thermal impedance.

8. A measurement system for determining a sintering thermal impedance of a sintering layer, the sintering layer being disposed on a substrate for bonding a semiconductor die to the substrate, the semiconductor die including a semiconductor element, the sintering layer and the substrate forming a stack, the substrate having a predetermined substrate thermal impedance and the semiconductor element including at least two element electrodes, the measurement system including: a current source for injecting an electrical current through the at least two element electrodes for measuring a temperature sensitive parameter of the semiconductor element, a heat source for heating the stack for sintering the sintering layer with a predetermined heat power; a first measurement device configured to determine a semiconductor element temperature from the temperature sensitive parameter; a second measurement device configured to measure a stack temperature; and a processing device configured to: determine a stack thermal impedance by subtracting the semiconductor element temperature from the stack temperature to obtain a temperature difference and dividing the temperature difference by the predetermined heat power, and determine the sintering thermal impedance by subtracting the predetermined substrate thermal impedance from the stack thermal impedance.

9. The measurement system according to claim 8, further including a controller configured to stop heating the stack when the sintering thermal impedance has reached a predetermined value.

10. The measurement system according to claim 8, further including a mechanical interface for supporting the substrate, the mechanical interface being thermally coupled to the substrate.

11. The measurement system according to claim 8, wherein the substrate is at least partially electrically conductive and includes a substrate electrode, and wherein one of the device electrodes is electrically connected to the substrate electrode via the sintering layer.

12. The measurement system according to claim 8, wherein the semiconductor element is one of devices: diode, Bipolar Junction transistors, Insulated Gate Bipolar Transistor, Metal Oxide Semiconductor Field Effect Transistor device.

13. The measurement system according to claim 8, wherein the temperature sensitive parameter is one of parameters selected out of: a forward direct voltage, a saturation voltage, a turn on voltage, a threshold voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) These and other aspects of the presently disclosed subject matter are apparent from and will be elucidated with reference to the embodiments described hereinafter. In the drawings,

(2) FIG. 1 schematically shows a flow diagram of a method of determining a sintering thermal impedance of a sintering layer,

(3) FIG. 2 schematically shows a substrate,

(4) FIG. 3 schematically shows a sintering layer on top of a substrate,

(5) FIG. 4 schematically shows a semiconductor die placed on a substrate with a sintering layer via a pick and place tool,

(6) FIG. 5 schematically shows a measurement system for determining a sintering thermal impedance of a sintering layer according to an embodiment,

(7) FIG. 6 schematically shows a measurement system for determining a sintering thermal impedance of a sintering layer according to another embodiment.

(8) It should be noted that items which have the same reference numbers in different figures, have the same structural features and the same functions, or are the same signals. Where the function and/or structure of such an item has been explained, there is no necessity for repeated explanation thereof in the detailed description.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

(9) FIG. 1 schematically shows a flow diagram 500 of a method of determining a sintering thermal impedance of a sintering layer.

(10) FIGS. 2 to 5 schematically show step by step of an embodiment of the method.

(11) The method will be hereinafter described with reference to the flow diagram 500 and the FIGS. 2 to 5.

(12) In FIG. 2 a substrate 20 is provided. Providing the substrate 510 is the first step of the flow diagram 500 shown in FIG. 1. The substrate 20 has a predetermined substrate thermal impedance. The thermal impedance may be for example known from the manufacturer of the substrate 20.

(13) Thermal impedance is defined as a ratio of the time function of a temperature difference divided by applied heat power and is measured in Kelvin per Watt [K/W]. The static value of the thermal impedance is the thermal resistance. Thermal resistance may be used to calculate true constant quantities, as well as average temperatures of periodic functions.

(14) The substrate 20 may be manufactured of multiple layers of thermally conductive, electrically insulating materials (e.g. ceramics), and highly electrically conductive materials (e.g. metals such as copper or aluminium). In the example shown in FIG. 2, the substrate 20 includes three layers, two high electrically conductive layers 5 and 10 sandwiched between a thermally conductive, electrically insulating layer of ceramic 15. Examples of ceramics include, but are not limited to Aluminium Nitride (AlN), Aluminium Oxide (Al.sub.2O.sub.3), and Silicon Nitride (Si.sub.3N.sub.4). Another example of ceramic material is Si.sub.3N.sub.4.

(15) Typically, in the relevant field, such substrates are termed as Direct Bonded Copper (DBC) substrates, or Active Metal Bonding/Brazing (AMB) substrates. Moreover, suitable substrates are described in a paper Comparison of Silicon Nitride DBC and AMB Substrates for different applications in power electronics of Manfred Goetz et al, pp 57-65, PCIM Europe conference, Nuremberg, 14-16 May 2013, published by VDE Verlag, Berlin. The article of Goetz et al is incorporated as a reference.

(16) The substrate 20 may further include other electronic elements including elements made up of a semiconductor material, such as, but not limited to silicon, silicon carbide, gallium arsenide, gallium nitride, diamond based semiconductor material, or other appropriate semiconductor materials. Examples of other appropriate semiconductor materials include, but not limited to resistors, capacitors, inductors, sensors, integrated circuits (for example, a driving circuitry), or other appropriate electronic elements.

(17) In FIG. 3 a sintering layer 25 is disposed on the substrate 20. This corresponds to method step 520 in flow diagram 500. The sintering layer 25 and the substrate form together a stack 21 of layers.

(18) The sintering layer may include a mixture of conductive powder, for example silver powder and a solvent. By heating the sintering layer, the solvent is removed from the mixture so as to cause the solvent to evaporate. Other metallic powders than silver powder may be used: for example gold, tungsten, or the like.

(19) The sintering layer 25 may be made of electrically conductive material and/or thermally conductive material.

(20) In FIG. 4 a semiconductor die 30 including a semiconductor element 40 is placed on the sintering layer 25. This corresponds to method step 530 in flow diagram 500. The semiconductor element 40 includes at least two device electrodes 45 and 47. The semiconductor element 40 may be integrated in the semiconductor die 30.

(21) The semiconductor die 30 may be placed on the substrate by a pick and place tool 50 for picking the semiconductor die 30 and placing it on the substrate 20 at the desired location.

(22) The semiconductor element 40 may be a transistor, a Field Effect Transistor (FET), a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a thyristor, an insulated-gate bipolar transistor (IGBT), a diode or another appropriate switching or non-switching semiconductor element.

(23) When the switching semiconductor element 40 is a transistor, the switching semiconductor element 40 may include a wide band gap semiconductor material. Optionally, the wide band gap semiconductor material includes, but not limited to silicon carbide (SiC), gallium nitride (GaN) or diamond.

(24) The semiconductor die 30, which is bonded to the substrate 20 by sintering, forms an integrated circuit device 150. The integrated circuit device 150 may include additional components which may be assembled on the same substrate 20.

(25) The pick and place tool 50 may include a suction duct (not shown) connected to suction means, for example including a vacuum pump (not shown). By enabling the vacuum pump, pick and place tool 50 may suction the semiconductor die 30 from a first die side opposite to a second die side placed in contact with the sintering layer 25. Pick and place tool 50 may further include a moving mechanical means (not shown) to pick the semiconductor die 30 up from one location, for example a semiconductor wafer containing many semiconductor dice, and placing the semiconductor die 30 to the desired location on the substrate 20. The mechanical means may be manually controlled or automatically, e.g. electrically, controlled.

(26) An electrical current is injected by current source 60 through the at least two element electrodes 45 and 47 for measuring a temperature sensitive parameter of the semiconductor element 40. This corresponds to method step 540 in flow diagram 500.

(27) In one embodiment, shown in FIG. 4, the substrate 20 has a substrate electrode 48. One of the device electrode 47 is electrically connected to the substrate electrode 48 via the sintering layer 25. The device electrode 47 may be located on a backside of the semiconductor die 30, i.e. on a side of the semiconductor die 30 which is placed in contact with the sintering layer 25. Vertical integrated semiconductor elements may have one of the device electrodes 45 arranged at the top side of the semiconductor die 30 and the other device electrode 47 may be arranged at the backside of the semiconductor die 30. The device electrode 45 may be contacted by a corresponding electrode (not shown in FIG. 4) of the pick and place tool 50 and be electrically connected to the current source 60 through it.

(28) However, the semiconductor element 40 of the presently disclosed subject matter is not limited to vertical integrated semiconductor elements. The semiconductor element 40 may be a horizontally integrated semiconductor element in which case the at least two element electrodes may be both located on the top side of the semiconductor die 30.

(29) The temperature sensitive parameter of the semiconductor element 40 is a physical parameter of the semiconductor element 40 and depends on the type of semiconductor element used.

(30) For example, for a diode, the temperature sensitive parameter may be a forward direct voltage of the diode. The relationship of the forward direct voltage of a diode versus the temperature is well known. The forward direct voltage is typically dropping 2 mV per degree Celsius. By knowing this relationship the temperature can be extracted.

(31) For an IGBT, the corresponding temperature sensitive parameter may be a collector emitter saturation voltage Vcesat. For a MOSFET, the corresponding temperature sensitive parameter may be a drain-source on voltage Vdson or a threshold voltage Vth.

(32) FIG. 5 schematically shows a first embodiment of a measurement system 100 for determining a sintering thermal impedance of a sintering layer 25.

(33) The sintering layer 25 is disposed on a substrate 20 for bonding a semiconductor element 40 to the substrate 20. The substrate 20 has a predetermined substrate thermal impedance. The semiconductor element 40 includes at least two element electrodes 45 and 47 for measuring a temperature sensitive parameter of the semiconductor element 40. The semiconductor element 40 may be integrated in a semiconductor die 30 which is placed on the substrate 20 via pick and place tool 50.

(34) The measurement system 100 includes a current source 60 for injecting an electrical current through the at least two element electrodes 45 and 47, a heat source 70 for heating the stack 21 for sintering the sintering layer 25 with a predetermined heat power, a first measurement device 65 configured to determine an element temperature from the temperature sensitive parameter, a second measurement device 75 configured to measure a stack temperature, and a processing device 78. The processing device 78 is configured to determine a stack thermal impedance by subtracting the element temperature from the stack temperature to obtain a temperature difference and dividing the temperature difference by the predetermined heat power. The processing device 78 is further configured to determine the sintering thermal impedance by subtracting the predetermined substrate thermal impedance from the stack thermal impedance.

(35) As schematically shown in FIG. 5, the stack 21 is heated by the heat source 70 for sintering the sintering layer 25 with a predetermined heat power. Heating the stack 21 corresponds to method step 550 in flow diagram 500.

(36) Optionally a compression force F.sub.c may be applied on the semiconductor die 30 by pick and place tool 50. With reference to FIG. 1, applying the compression force F.sub.c corresponds to optional method step 550 shown in flow diagram 500. The compression force F.sub.c has a vertical direction and maintains the semiconductor die 30 in place on the sintering layer 25 against the substrate 20. Predetermined heat power and a value of the compression force F.sub.c are controlled according to the desired sintering requirements. The heat source 70 may be a laser beam, or any other suitable heat source, for example an oven or a furnace. While the stack 21 is heated, a constant current is injected through the at least two device electrodes 45 and 47 of the semiconductor element 40.

(37) While sintering, a temperature of the semiconductor element is determined from the measured temperature sensitive parameter. This corresponds to step 560 of flow diagram 500. For example, for a diode, the forward direct voltage may be monitored by the first measurement device 65, e.g. a voltmeter. From the measured forward direct voltage, the temperature of the semiconductor element 40 and therefore of the semiconductor die 30 is determined.

(38) At the same time, the temperature of the stack 21 is measured, preferably in proximity of the substrate 20, for example at a top side or back side of the substrate 20. This corresponds to method step 565 in flow diagram 500. The temperature can for example be measured at the top side of the substrate 20 by a second measurement device 75, e.g. a thermocouple, or thermometer device.

(39) A thermocouple is a material arrangement including two different materials, e.g. two wires made of different metals. A differential voltage appears between both materials, this is the so-called Seebeck effect. This differential voltage is proportional to the temperature. Thermocouples are common in many thermal systems for measuring the temperature locally inside the system. A thermocouple is usually measuring a volume temperature when it is inserted within a piece of material. A joint between the two different materials of the thermocouple is sensitive to the temperature. The joint is a sensing temperature electrode of the thermocouple and it is where the temperature is actually measured.

(40) In the embodiment shown in FIG. 5, the stack 21 is directly heated from the bottom of the substrate 20 by the heat source 70.

(41) When the second measurement device 75 is a thermocouple, its sensing temperature electrode may be thermally coupled to the substrate 20.

(42) Once the element temperature is determined and the stack temperature is measured, a stack thermal impedance can be determined by the processing device 78.

(43) Determining the stack thermal impedance 570 is shown in flow diagram 500. The stack thermal impedance is determined by subtracting the semiconductor element temperature from the stack temperature and dividing the result by the predetermined heat power. The following equation shows how the stack thermal impedance Z.sub.th,s is determined:

(44) $\begin{array}{cc}{Z}_{\mathrm{th},s}=\frac{T_s-T_{\mathrm{el}}}{P_{\mathrm{heat}}},& \left(1\right)\end{array}$
where Z.sub.th,s is the stack thermal impedance, T.sub.s is the stack temperature, T.sub.el is the semiconductor element temperature and P.sub.heat is the predetermined heat power.

(45) From the thermal impedance Z.sub.th,s of the stack 21, the sintering thermal impedance Z.sub.th,sint of the sintering layer 25 can be determined by subtracting the predetermined substrate thermal impedance from the stack thermal impedance:
Z.sub.th,sint=Z.sub.th,sZ.sub.th,sub(2),
where Z.sub.th,sub is the predetermined substrate thermal impedance. Determining the sintering thermal impedance corresponds to method step 580 in flow diagram 500.

(46) FIG. 6 schematically shows a second embodiment of a measurement system 200. Measurement system 200 differs from measurement system 100 in that measurement system 200 further includes a mechanical interface 80 for supporting the substrate 20 and a controller 95 for controlling the heat source 70 and optionally the pick and place tool 50.

(47) The mechanical interface 80 is thermally coupled to the substrate 20.

(48) In the measurement system 200, a stack 22 including the substrate 20, the sintering layer 25 and the mechanical interface 80 is formed.

(49) The stack 22 is heated by the heat source 70 via the mechanical interface 80.

(50) The mechanical interface 80 may be made of an electrically insulating and thermally conductive material, for example ceramic. However, other type of materials suitable for supporting the stack 22 and transferring heat between the heat source 70 and the stack 21 may be used.

(51) The mechanical interface 80 provides mechanical support for the stack 21. The mechanical interface 80 provides thermal protection for the stack 21. With the mechanical interface 80 arranged at the bottom of the stack 21, the stack 21 and the substrate 20 are protected from direct heating by the heat source 70. The mechanical interface 80 may prevent heat from either deforming the stack 21 or modifying physical properties of the stack 21.

(52) The mechanical interface 80 may have a gap 85 arranged therein in which a thermocouple 90 is arranged.

(53) The sensing temperature electrode of the thermocouple 90 is thermally coupled to the substrate via the mechanical interface 80. Temperature of the stack 22 can be measured by the thermocouple 90.

(54) The controller 95 is configured to stop heating the stack 22 when the sintering thermal impedance determined as described with reference to FIG. 6 and equation (2) has reached a predetermined value.

(55) With reference to FIG. 5, the stack thermal impedance is the thermal impedance of the stack 21 which includes the thermal impedance of the substrate 20 and the thermal impedance of the sintering layer 25. The substrate 20 and the sintering layer 25 are thermally arranged in series. Hence the thermal impedance of the stack 21 is the sum of the thermal impedance of the substrate 20 and the thermal impedance of the sintering layer 25, respectively.

(56) With reference to FIG. 6, the stack thermal impedance is the thermal impedance of the stack 22 which includes the thermal impedance of the substrate 20, the thermal impedance of the sintering layer 25 and the thermal impedance of the mechanical interface 80. The substrate 20, the sintering layer 25 and the mechanical interface 80 are thermally arranged in series. Hence the thermal impedance of the stack 22 is the sum of the thermal impedance of the mechanical interface 80, the thermal impedance of the substrate 20, and the thermal impedance of the sintering layer 25, respectively. However, the substrate 20 and the mechanical interface are both made of high thermally conductive materials. The predetermined substrate thermal impedance can in the embodiment shown in FIG. 6 be approximated to the sum of thermal impedance of the substrate 20 and the thermal impedance of the mechanical interface 80.

(57) With the inventive method described, the thermal impedance of the sintering layer 25 can be determined. Further, better accuracy can be achieved with respect to the conventional art document US2010/0176098 which uses an optical method, because the inventive method determines the thermal impedance of the sintering layer 25 while conventional art US2010/0176098 can only determine a surface temperature of the semiconductor die.

(58) With the inventive method, the thermal impedance of the sintering layer 25 is determined in the sintering layer 25 at a location corresponding to the location of the semiconductor element 40.

(59) In the method described, the thermal impedance of the sintering layer 25 is determined while sintering is occurring.

(60) The inventive method allows real-time monitoring of the evolution of the thermal impedance of the sintering layer 25 while thermal conductivity of the sintering layer increases while sintering is occurring. This effect cannot be reached by conventional art optical methods measuring only surface temperatures. These conventional art optical methods may only give an approximate measure of the temperature of the sintering layer at thermal equilibrium, i.e. when the sintering layer has already reached the desired temperature and thus with a substantial delay. The inventive method can thus better monitor the quality of the sintering during sintering. This is beneficial for a large number of applications where for example sintering is performed in two or more phases.

(61) In a first phase a pre-sintering may be performed in which the heat source 70 heats the stack 21 or 22 and optionally the compression force F.sub.c is applied on the semiconductor die 30 for a predetermined period of time.

(62) Heating the stack 21 or 22 may be stopped after the predetermined period of time. For example, heating the stack 20 or 21 and optionally applying the compression force F.sub.c may be stopped when the determined sintering thermal impedance has reached a predetermined value.

(63) With reference to FIG. 6 the controller 95 may be coupled to the heat source 70, processing device 78 and optionally to the pick and place tool 50. The controller 75 may be configured to receive the sintering thermal impedance from the processing device 78 and to control the heat source 70 and the pick and place tool 50. The controller 95 may be configured for stopping heating the stack 20 and optionally stopping applying the compressing force F.sub.c on the semiconductor die 30 when the sintering thermal impedance has reached the predetermined value.

(64) This predetermined value of the sintering thermal impedance should be sufficient to allow the semiconductor die 30 to withstand certain minimal pull and shear strength requirements such that the device can be handled during further assembly of the device.

(65) For example, the predetermined value of the sintering thermal impedance may be 0.05 C. per watt or lower.

(66) With reference to FIG. 1, heating the stack 550 may be performed until the predetermined value of the sintering thermal impedance is reached. When the sintering thermal impedance has reached the predetermined value, heating the stack may be stopped 590, e.g. by the controller 95 as shown in FIG. 6.

(67) The predetermined value of the sintering thermal impedance may correspond to a first predetermined shear and/or pull strength of the semiconductor die. The first predetermined shear and/or pull strength of the semiconductor die may be minimal to guarantee sufficient bonding between the semiconductor die and the substrate.

(68) Assembly of the device 150 may consist of several thermal cycles in which different parts are mounted or soldered in subsequent assembly phases. During these subsequent assembly phases the device is handled in the assembly line.

(69) By performing pre-sintering in the first phase, i.e. by heating the stack until the predetermined value of the sintering thermal impedance is reached, thermal stress is limited to the amount to ensure that the minimal pull and shear strength requirements are satisfied.

(70) The device is not thermally overstressed which improves lifetime of the device. Further, if the sintering thermal impedance cannot achieve the predetermined value, this may be an indication of a defective contact between the substrate 20 and the semiconductor die 30 or defective material of the sintering layer 25. In both cases the assembled device may be scrapped from the production line, avoiding that a defective device may be further handled during assembly. With the described method, assembly yield can thus be improved and costs of assembly decreased.

(71) In a second phase, a full sintering may be performed. The second phase can be performed by heating the stack for obtaining a sintering thermal impedance value corresponding to a second predetermined shear and/or pull strength of the semiconductor die. The second predetermined shear and/or pull strength may be higher than the first predetermined shear and/or pull strength. The second predetermined shear and/or pull strength may be sufficiently high for final assembly requirements. In the second phase, heating the stack may be performed with the same heat source 70 which may be re-activated for an additional time period or by heating with a different heat source 70, for example with an oven or furnace.

(72) Multiple semiconductor dice may be placed on the sintering layer 25.

(73) For example, in an embodiment, the method of determining the sintering thermal impedance may further include placing a further semiconductor die on the sintering layer 25 or further sintering layer. The further semiconductor die may include a further semiconductor element which includes at least two corresponding further element electrodes for injecting a current therein and measuring a corresponding further temperature sensitive parameter of the further semiconductor element.

(74) In this embodiment, while sintering, a further semiconductor element temperature can be determined from the further temperature sensitive parameter. The thermal impedance of the stack can be determined by subtracting the further semiconductor element temperature from the stack temperature to obtain a further temperature difference and dividing the further temperature difference by the predetermined heat power. Finally, the sintering thermal impedance of the sintering layer can be determined at a location corresponding to the further semiconductor element by subtracting the predetermined substrate thermal impedance from the stack thermal impedance.

(75) The further semiconductor element may be integrated in the further semiconductor die.

(76) In this way the sintering thermal impedance of the sintering layer may be determined at a location of multiple semiconductor dice. The yield of complex assembly technology where multiple semiconductor dice are bonded to the substrate can be improved.

(77) In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. Use of the verb include and its conjugations does not exclude the presence of elements or steps other than those stated in a claim. The article a or an preceding an element does not exclude the presence of a plurality of such elements. The presently disclosed subject matter may be implemented by means of hardware including several distinct elements, and by means of a suitably programmed computer. In the device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.