Method and system providing Fourier transform based signal processing with reduced computational complexity
10848358 ยท 2020-11-24
Inventors
Cpc classification
H04L27/2651
ELECTRICITY
G06F17/142
PHYSICS
International classification
G06F17/14
PHYSICS
Abstract
According to an aspect of the present invention, a signal processor comprises an N-point phase FFT transformer operative to perform a FFT like transformation according to a first relation
wherein angle [x(n)] representing the phase of the signal x(n). In that, a plurality of butterfly units with each butterfly unit in the plurality of butterfly units comprises an adder, subtractor and a multiplier, wherein the adder, the subtractor and multiplier receive a phase only signals with a signal amplitude less than unity. The butterfly units are arranged in plurality of stages to perform the operation as in the first relation.
Claims
1. A signal processor comprising: A first converter to convert an input signal x(n) with an amplitude and a phase to a phase only signal; and an N-point phase FFT transformer operative to convert the phase only signal to an output signal Y[k] according to a first relation:
2. The signal processor of claim 1, further comprising a plurality of butterfly units with each butterfly unit in the plurality of butterfly units comprising an adder, subtractor and a multiplier, wherein the plurality of butterfly units configured to operate on the phase only signal, wherein the first converter converting the amplitude of the input signal to a value less than or equal to unity in the phase only signal.
3. The signal processor of claim 2, wherein the plurality of butterfly units are arranged in a plurality of stages to perform the operation as in the first relation, wherein the adder, the subtractor and the multiplier are configured to operate with lesser number of bits for the phase only signal as against the number of bits required to perform respective operation for the input signal.
4. The signal processor of claim 3, wherein the input signal is a complex signal and the signal processor further comprising a second convertor configured to convert a real signal to the input signal.
Description
BRIEF DESCRIPTION OF DRAWINGS
(1)
(2)
(3)
(4)
(5)
(6)
(7)
DETAILED DESCRIPTION OF THE PREFERRED EXAMPLES
(8)
(9) The signal source 110 provides an input signal for processing. The input signal comprises an amplitude, frequency and phase part. The input signal may carry information in at least one of its amplitude, frequency and phase. The input signal may be in the analog, discrete and/or in digital form. For example, the input signal may be presented as n number of samples per second or k bits binary values of the samples. Input signal may comprise an in-phase and quadrature phase component, real and imaginary part (a complex signal) or real part.
(10) The signal source 110 comprises sensors that generate electrical signals from physical and environmental conditions around it like microphone, camera, thermistors, baseband signal generator, modulator, frequency translator, receiver receiving RF signals from wireless and wired medium, antenna, other signal processing elements that provide a processed signal (like filters, amplifier, converters etc.,).
(11) The signal processor 120 processes the input signal received from the signal source 110 to generate an output signal suitable for performing a desired operation in the target circuitry. In one embodiment the signal processor 120 performs an FFT operation on the input signal. The signal processor 120 may be implanted as digital logic circuit with multipliers, adders, registers, etc., or on a processor executing sequence of instruction to perform the FFT operation.
(12) The target circuitry 130 comprises a transmitter, transmitting antenna, display, memory, graphical devices, transducers, speakers, external interface terminals, and other signal processing units performing further signal processing sequence of processing desired as part of the system. The target circuitry 130 receives the output signal from the signal processor 120 to perform next sequence of operation like transmit, display, render, store and further process, for example. The manner in which the FFT operation in the signal processor 120 may be implemented with reduced computational complexity is further described below.
(13)
(14)
In that, the X.sub.p() represents the Phase only Fourier transform with other notation representing the corresponding standard notation used in regular Fourier transform relation. Alternatively, the Phase Fourier transform may be represented for a complex signal as:
(15)
and for the real signal the Phase Fourier transform may be represented as:
(16)
in that the x(t) is a complex input signal, {tilde over (x)}(t) is the complex envelop of a real input signal and angle representing the phase of the signal x(t) or {tilde over (x)}(t). For example, if x(t) is real signal like x(t)=a.sub.1 cos .sub.1t+a.sub.2 cos .sub.2t, then {tilde over (x)}(t)=(a.sub.1 cos .sub.1t+a.sub.2 cos .sub.2t)+j(a.sub.1 sin .sub.1t+a.sub.2 sin .sub.2t), and the angle
(17)
Further, when x(t) is the input signal in the time domain that is represented as the summation of a set of exponential (sinusoidal) signals of different frequency as:
x(t)=.sub.k=1.sup.Ka.sub.kexp.sup.j.sup.
then the phase Fourier Transform may be represented (neglecting higher order values in the magnitude) as:
(18)
(19) Accordingly, the magnitude of the Phase only Fourier transform X.sub.p() shows the peaks proportional to the amplitude a.sub.k for each tone at frequency .sub.k similar to conventional Fourier transform. The manner in which the N-point Phase FFT may be implemented in conjunction with the Phase Fourier transform in an embodiment is further described below.
(20)
(21)
(22) The multiplier 430 performs a complex multiplication operation using a complex multiplication factor as in the relation (6) and the adder 410 and subtractor 420 operate to perform the summation and subtraction operation respectively before the multiplication operation is performed on the output of the subtraction. Accordingly, it may be readily seen that, the magnitude of the result of the multiplication is limited to a maximum of unity, and the result of the summation does not grow beyond additional one bit for each butterfly stage.
(23) In contrast, in a conventional FFT, the amplitude part of the sinusoidal components (in the input signal) increases the dynamic range of the signal at the output of the adder and subtractor and thus result in higher precision for the multiplier that follows to multiply the result of the subtraction with the
(24)
(twiddle factor) in the summation, thus the result of the multiplication operation and addition operation may require higher number of bits for representation.
(25) The reduction in the computational complexity is further illustrated with an example input signal as x(n)=a.sub.1e.sup.j.sup.
(26)
In contrast, the conventional FFT is computed as:
(27)
It may be readily appreciated that the N-point phase FFT in relation 7 requires less precession or dynamic range for multiplication and addition than the relation 8. Accordingly, the multiplier 330 may be implemented with the less dynamic range. For example, if each phase components are represented by 10 bits, then relation 7 may be implemented with 21 bits to store intermediate values as against 31 or more bits required in case of relation 8. The manner in which Phase FFT may be employed for complex and real signals is further described below.
(28) In one embodiment the input signal provided to the N-point phase FFT is first converted to phase only signal.
(29)
(30)
(31) Similarly,
(32) While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present disclosure should not be limited by any of the above-discussed embodiments, but should be defined only in accordance with the following claims and their equivalents.