Chopper stabilized amplifier

Abstract

There is provided a chopper stabilized amplifier with an input bias current reduced. The chopper stabilized amplifier includes a main amplifier and a correction circuit. The correction circuit includes a second gm amplifier of a full differential type. A first selector and the second gm amplifier are coupled to each other without DC blocking capacitors. The differential input state of the second gm amplifier is configured with a depletion-type transistor.

Claims

1. A chopper stabilized amplifier comprising: a non-inverting input pin configured to receive a first voltage; an inverting input pin configured to receive a second voltage; a main amplifier configured to generate an output signal according to an error between the first voltage and the second voltage; and a correction circuit, wherein the main amplifier includes: a first gm amplifier installed as a differential input stage and configured to generate a first current signal, the first gm amplifier having a non-inverting input terminal connected to the non-inverting input pin and an inverting input terminal connected to the inverting input pin; and an output stage configured to receive the first current signal and generate the output signal of the main amplifier, wherein the correction circuit includes: a second gm amplifier of a full differential type configured to amplify a potential difference between a non-inverting input terminal and an inverting input terminal and output a differential current signal from an inverting output terminal and a non-inverting output terminal; an integration circuit configured to integrate a differential input current which is input to a non-inverting input terminal and an inverting input terminal, sample/hold the integrated differential input current at a predetermined cycle, and generate a differential voltage signal; a first selector installed at a preceding stage of the second gm amplifier and configured to switch between (i) a first state where the non-inverting input pin and the inverting input pin are connected with the inverting input terminal and the non-inverting input terminal of the second gm amplifier, respectively, and (ii) a second state where the non-inverting input pin and the inverting input pin are connected with the non-inverting input terminal and the inverting input terminal of the second gm amplifier, respectively; a second selector installed at a subsequent stage of the second gm amplifier and configured to switch between (i) a first state where the inverting output terminal and the non-inverting input terminal of the second gm amplifier are connected with the inverting input terminal and the non-inverting input terminal of the integration circuit, respectively, and (ii) a second state where the inverting output terminal and the non-inverting input terminal of the second gm amplifier are connected with the non-inverting input terminal and the inverting input terminal of the integration circuit, respectively; and a third gm amplifier configured to convert the differential voltage signal generated by the integration circuit into a second current signal and overlap the second current signal with the first current signal, and wherein the second gm amplifier has a depletion-type differential input pair.

2. The chopper stabilized amplifier of claim 1, wherein the integration circuit includes: an integrator configured to generate the differential voltage signal by integrating the differential input current input to the non-inverting input terminal and the inverting input terminal; and a sample/hold circuit configured to sample/hold the differential voltage signal generated by the integrator.

3. The chopper stabilized amplifier of claim 1, wherein both the first gm amplifier and the third gm amplifier are of a full differential type, and the second current signal that is differential is overlapped with the first current signal that is differential.

4. The chopper stabilized amplifier of claim 1, wherein the first selector and the second selector are controlled based on a first clock signal.

5. The chopper stabilized amplifier of claim 4, wherein the integration circuit is controlled to be in a hold state at an edge timing of a second clock signal.

6. The chopper stabilized amplifier of claim 4, wherein the integration circuit is controlled to perform a sampling operation in a period during which the first clock signal is stable.

7. The chopper stabilized amplifier of claim 1, wherein the second gm amplifier includes a first transistor and a second transistor that are depletion-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) whose sources are connected in common to a tail current source, and outputs currents flowing through the first transistor and the second transistor, respectively.

8. The chopper stabilized amplifier of claim 2, wherein the integrator includes: a third MOSFET having a source connected to a fixed voltage line and a gate to which one current signal in a differential type current signal pair is input from the second selector; a fourth MOSFET having a source connected to the fixed voltage line and a gate to which the other current signal in the differential type current signal pair is input from the second selector; a first capacitor installed between the gate and a drain of the third MOSFET; and a second capacitor installed between the gate and a drain of the fourth MOSFET.

9. The chopper stabilized amplifier of claim 2, further comprising a common mode feedback circuit configured to adjust a bias state of the second gm amplifier such that a midpoint voltage between two output voltages of the integrator approaches a target voltage.

10. The chopper stabilized amplifier of claim 1, wherein the chopper stabilized amplifier is integrated on a single semiconductor substrate.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a circuit diagram of a chopper stabilized amplifier reviewed by the present inventors.

(2) FIG. 2 is a circuit diagram of a conventional chopper stabilized amplifier.

(3) FIG. 3A is a waveform diagram showing an example of the operation of the chopper stabilized amplifier of FIG. 2.

(4) FIG. 3B is a diagram showing clocks CK.sub.1 and CK.sub.2 used in the chopper stabilized amplifier of FIG. 1.

(5) FIG. 4A is an operation waveform diagram of the chopper stabilized amplifier of FIG. 2.

(6) FIG. 4B is a diagram showing a relationship between an input voltage and an input bias current of the chopper stabilized amplifier of FIG. 2.

(7) FIG. 5 is a circuit diagram of a chopper stabilized amplifier according to an embodiment.

(8) FIG. 6 is a circuit diagram showing a configuration example of a correction circuit.

(9) FIG. 7 is a diagram showing a relationship between an input voltage and an input bias current of the chopper stabilized amplifier of FIG. 5.

(10) FIG. 8A is a circuit diagram of a voltage follower circuit using a chopper stabilized amplifier.

(11) FIG. 8B is a circuit diagram of a differential amplifier using a chopper stabilized amplifier.

(12) FIG. 9A is a diagram showing input/output characteristics of the voltage follower circuit of FIG. 8A.

(13) FIG. 9B is a diagram showing input/output characteristics of the differential amplifier of FIG. 8B.

(14) FIG. 10 is a circuit diagram of a correction circuit according to a modification.

DETAILED DESCRIPTION

(15) Embodiments of the present disclosure will be now described in detail with reference to the drawings. Like or equivalent components, members, and processes illustrated in each drawing are given like reference numerals and a repeated description thereof will be properly omitted. Further, the embodiments are presented by way of example only, and are not intended to limit the present disclosure, and any feature or combination thereof described in the embodiments may not necessarily be essential to the present disclosure.

(16) In the present disclosure, a state where a member A is connected to a member B includes a case where the member A and the member B are physically directly connected or even a case where the member A and the member B are indirectly connected through any other member that does not affect an electrical connection state between the members A and B or does not impair functions and effects achieved by combinations of the members A and B.

(17) Similarly, a state where a member C is installed between a member A and a member B includes a case where the member A and the member C or the member B and the member C are indirectly connected through any other member that does not affect an electrical connection state between the members A and C or the members B and C or does not impair function and effects achieved by combinations of the members A and C or the members B and C, in addition to a case where the member A and the member C or the member B and the member C are directly connected.

(18) FIG. 5 is a circuit diagram of a chopper stabilized amplifier 1 according to an embodiment. The chopper stabilized amplifier 1 of FIG. 5 is obtained by removing the capacitors C3 and C4 from the chopper stabilized amplifier 1R of FIG. 2. Further, a differential input pair of a second gm amplifier 22 is configured with depletion-type transistors instead of the generally used enhancement-type transistors.

(19) FIG. 6 is a circuit diagram showing a configuration example of the correction circuit 20. The third gm amplifier 40 is not shown in FIG. 6.

(20) A current mirror circuit 60 receives a reference current I.sub.REF as an input and generates a plurality of currents proportional to the reference current I.sub.REF. The current mirror circuit 60 includes a tail current source 62 and constant current sources 64 and 66.

(21) The second gm amplifier 22 includes a first transistor M11 and a second transistor M12, which are a differential input pair. The first transistor M11 and the second transistor M12 are depletion-type PMOS transistors whose sources are connected to a tail current source 62 and to which a tail current I.sub.T is supplied. A current flowing through the first transistor M11 corresponds to the current I.sub.3N in FIG. 2 and a current flowing through the second transistor M12 corresponds to the current I.sub.3P in FIG. 2.

(22) An integrator 26 mainly includes third and fourth transistors M13 and M14, which are NMOS transistors, and first and second capacitors C1 and C2. The sources of the third and fourth transistors M13 and M14 are connected to a fixed voltage line (ground line). A pair of differential type current signals I.sub.4P and I.sub.4N from the second selector 32 is input to the gates of the third transistor M13 and the fourth transistor M14, respectively. The first capacitor C1 is installed between the gate and the drain of the third transistor M13 and the second capacitor C2 is installed between the gate and the drain of the fourth transistor M14. The third transistor M13 and the fourth transistor M14 are biased with equal currents I.sub.B1 and I.sub.B2 by the constant current sources 64 and 66, respectively.

(23) A common mode feedback circuit 50 adjusts the bias state of the second gm amplifier 22 such that a midpoint voltage V.sub.COM1 between the two output voltages V.sub.6P and V.sub.6N of the integrator 26 approaches the target voltage V.sub.REF. That is, the midpoint voltage V.sub.COM1 of the output voltages V.sub.6P and V.sub.6N is generated by resistors R11 and R12. Further, the midpoint voltage V.sub.REF between the power supply voltage VDD and the ground voltage VSS is generated by resistors R31 and R32 and is supplied to one input terminal of a differential amplifier 52.

(24) The sample/hold circuit 28 includes switches SW41 to SW48 and capacitors C41, C42, and C43. Each switch of FIG. 4 is a CMOS switch (transfer gate), and NMOS and PMOS transistors are controlled by complementary clocks CK.sub.A1 and CK.sub.A2 (CK.sub.B1 and CK.sub.B2). Each clock signal is shown in FIG. 3A.

(25) The above is a configuration of the chopper stabilized amplifier 1 according to the embodiment. Subsequently, the advantages thereof will be described.

(26) FIG. 7 is a diagram showing a relationship between the input voltage and the input bias current of the chopper stabilized amplifier 1 of FIG. 5. The characteristics of the chopper stabilized amplifier 1 of FIG. 5 are indicated by a solid line, and the characteristics of the conventional chopper stabilized amplifier 1R shown in FIG. 2 are indicated by an alternate long-and-short dashed line, for comparison. According to the chopper stabilized amplifier 1 of FIG. 5, since the DC blocking capacitors C3 and C4 of FIG. 2 are omitted, the input bias current can be reduced. Specifically, the input bias current is 110 pA to 60 pA in the conventional chopper stabilized amplifier 1R, whereas the input bias current is reduced to 50 pA to 10 pA in the chopper stabilized amplifier 1 of FIG. 5.

(27) In addition, the capacitors C3 and C4 are unnecessary, and the circuit area can be reduced. Assuming that the capacitance value of each capacitor is 20 pF, the capacitance of 40 pF in total can be reduced. Further, the capacitors affect a semiconductor manufacturing process, and their area is about 90 m450 m so that the effect on the chip area is not small. The capacitance values of the capacitors C3 and C4 are designed according to the chopper frequency. The capacitance values of the capacitors C3 and C4 may be several hundreds of pF according to the chopper frequency, and the larger capacitance values show more remarkable reduction in the chip area.

(28) In the related art, it is necessary to design the capacitance values of the capacitors C3 and C4 according to the circuit operation frequency (chopper frequency). In contrast, with the chopper stabilized amplifier 1 according to the embodiment, it is possible to design a circuit independent from the chopper frequency.

(29) Further, since the resistors R21 and R22 for bias are unnecessary, the circuit area can be further reduced. For example, when the resistors R21 and R22 are composed of a combination of four resistors of 500 k, their area is about 50 m20 m, thereby contributing to a reduction in the chip area though not as large as the capacitors.

(30) Subsequently, further advantages of the chopper stabilized amplifier 1 will be described. Simulation results of evaluating the characteristics of several circuits constructed by using the chopper stabilized amplifier 1 will be described. FIG. 8A is a circuit diagram of a voltage follower circuit using the chopper stabilized amplifier 1, and FIG. 8B is a circuit diagram of a differential amplifier using the chopper stabilized amplifier 1. FIG. 9A is a diagram showing input/output characteristics of the voltage follower circuit of FIG. 8A, and FIG. 9B is a diagram showing input/output characteristics of the differential amplifier of FIG. 8B.

(31) In FIG. 9A and FIG. 9B, the characteristics of the chopper stabilized amplifier 1 according to the embodiment are indicated by a solid line, whereas the characteristics of a comparative technique are indicated by a broken line. The comparative technique is a circuit in which the differential input pair of the second gm amplifier 22 is configured as an enhancement type in the configuration of FIG. 5.

(32) As shown in FIG. 9A, in the comparative technique using the enhancement type, when the input voltage V.sub.IN exceeds 4V, the inverted output V.sub.OUTN deviates from the ideal characteristics. In contrast, in the embodiment using the depletion type, the inverted output V.sub.OUTN maintains the ideal characteristics within the full range of 0 to 5V.

(33) In addition, as shown in FIG. 9B, in the comparative technique using the enhancement type, when the input voltage V.sub.IN exceeds 3.9V, the offset voltage increases. In contrast, in the embodiment using the depletion type, the offset voltage can be brought close to zero within the full range of 0 to 5V.

(34) The present disclosure has been described above by way of embodiments. The disclosed embodiments are exemplary only and it should be understood by those skilled in the art that various modifications to combinations of elements or processes may be made and such modifications fall within the scope of the present disclosure. Such modifications will be described below.

(35) (First Modification)

(36) It has been illustrated in the embodiment that both the first gm amplifier 12 and the third gm amplifier 40 have a differential output type. However, their outputs may be single-ended. In this case, by setting the output of the third gm amplifier 40 to a push-pull type, the positive/negative offset voltage V.sub.OS1 can be cancelled.

(37) (Second Modification)

(38) The configuration of the integration circuit 24 is not limited to that shown in FIG. 2. For example, the sample/hold circuit 28 may be integrated with the integrator 26. A circuit in which the integrator and the sample/hold circuit are integrated is often used in the field of sensors and the like to utilize the technique thereof.

(39) (Third Modification)

(40) FIG. 10 is a circuit diagram of the correction circuit 20 according to a modified embodiment. The correction circuit 20 may be understood as a configuration in which the top and bottom are inverted by exchanging the P channel transistor and the N channel transistor of the correction circuit 20 of FIG. 6.

(41) According to the present disclosure in some embodiments, it is possible to provide a chopper stabilized amplifier with a more simplified configuration.

(42) While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the embodiments described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures.