Method of operating a controller, corresponding circuit and device

Abstract

A PWM signal generator to provide a supply current to an electrical load generates PWM signals at a first frequency, the PWM signals having a duty cycle. Operating the generator involves receiving a set point signal indicative of a target average value for the supply current, sensing a sensing signal indicative of a current actual value of the supply current, performing a closed-loop control of the supply current targeting the target value for the supply current via a controller such as a PID Controller which controls the duty cycle of the PWM signals generated by the PWM signal generator as a function of the offset of the sensing signal with respect to the set point signal.

Claims

1. A method of controlling a PWM signal generator configured to provide a supply current to an electrical load, the PWM signal generator generating PWM signals at a first frequency, the PWM signals having a duty cycle, the method comprising: receiving a set point signal indicative of a target value for said supply current; sensing a sensing signal indicative of a current value for said supply current; and performing a closed-loop control of said supply current targeting said target value for said supply current via a controller controlling the duty cycle of the PWM signals generated by the PWM signal generator as a function of an offset of the sensing signal with respect to the set point signal.

2. The method of claim 1, comprising forwarding the sensing signal to said controller in the absence of averaging processing applied to said sensing signal.

3. The method of claim 1, comprising generating a discrete-time version of the sensing signal and controlling the duty cycle of the PWM signals generated by the PWM signal generator as a function of the offset of said discrete-time version of the sensing signal with respect to the set point signal.

4. The method of claim 1, wherein the controller comprises at least one signal processing branch operating on discrete-time signals at a second frequency, wherein the method comprises selecting said second frequency as a multiple of said first frequency.

5. The method of claim 4, comprising selecting said second frequency at least one order of magnitude and preferably about three orders of magnitude higher than said first frequency.

6. The method of claim 4, wherein the controller comprises a PID controller including an integral branch and a derivative branch operating on discrete-time signals.

7. The method of claim 1, wherein the controller is a digital controller and the method comprises forwarding to said controller said sensing signal in digital form.

8. A circuit, comprising: a PWM signal generator configured to provide a supply current to an electrical load, the PWM signal generator generating PWM signals with a first frequency, the PWM signals having a duty cycle; a controller configured to receive an offset signal indicative of the offset of a sensing signal indicative of a current value for said supply current with respect to a set point signal indicative of a target value for said supply current; and the controller configured to perform a closed-loop control of said supply current targeting said target value for said supply current by controlling the duty cycle of the PWM signals generated by the PWM signal generator as a function of said offset signal.

9. The circuit of claim 8, further comprising an electrical load coupled to said PWM signal generator to receive said supply current.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) One or more embodiments will now be described, by way of example only, with reference to the annexed figures wherein:

(2) FIG. 1 is a block diagram of a feedback-loop control arrangement of a PWM signal generator;

(3) FIG. 2 is a circuit diagram of an exemplary implementation, with possible variations, of the arrangement of the FIG. 1;

(4) FIG. 3 is a block diagram of a feedback-loop control arrangement of a PWM signal generator as per the present disclosure;

(5) FIG. 4 is a circuit diagram of an exemplary implementation, with possible variations, of a possible implementation of the arrangement of the FIG. 3; and

(6) FIGS. 5A, 5B and 6 are time diagrams exemplary of possible operation of embodiments.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(7) In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

(8) Reference to an embodiment or one embodiment in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as in an embodiment or in one embodiment that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

(9) The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

(10) In FIGS. 1 and 2, reference numeral 10 indicates as a whole a circuit arrangement which implements a closed-loop control strategy in a PWM driver arrangement of a load L, such as an inductive load.

(11) A solenoid (for use, e.g. in a braking or transmission system in a vehicle, not visible in the figures as a whole) may be exemplary of such a load L, which may be represented as the series connection of an inductor Ls and a resistor Rs.

(12) It will be otherwise appreciated that reference to a load L comprising a solenoid and/or to a possible application in the automotive field is merely for exemplary purposes and is not to be construed, even indirectly, in a limiting sense of the embodiments.

(13) In an arrangement as exemplified herein, the load L is driven via a power driver circuit D receiving a supply voltage VS.

(14) As exemplified in FIG. 1, the load L may be coupled between the supply voltage VS and the output of the power driver circuit D and be traversed by a current I.sub.S.

(15) As exemplified in FIG. 2, the load L may be coupled between the output of the power driver circuit D at a voltage V.sub.LOAD and ground GND and be traversed by a current I.sub.LOAD.

(16) In arrangements as exemplified in FIGS. 1 and 2, the driver stage D is in turn driven via a Pulse-Width Modulated signal PWM as generated by a PWM signal generator 12 associated with a controller circuit 14.

(17) As exemplified in FIG. 2, the controller 14 may comprise a Proportional-Integral-Derivative (PID) controller in turn comprising, in a manner known to those of skill in the art:

(18) a proportional branch 141 with an associated (proportional) gain K.sub.P,

(19) an integral branch 142, with an associated (integral) gain K.sub.3 and including an integrator circuit block 142A, and

(20) a derivative branch 143, with an associated (derivative) gain K.sub.D and including a derivative circuit block 143A.

(21) The outputs from the branches 141, 142 and 143 are summed at a summation node 144 and applied as a control signal PID to one input of the PWM signal generator 12.

(22) Again in a manner known to those of skill in the art the PWM signal generator 12 may essentially comprise a comparator circuit whose other input is supplied with a ramp signal Ramp by a ramp generator 16 which generates a triangular (saw-tooth) signal with a period T.sub.PWM. The period of the ramp signal defines the period of the PWM signal generated by the generator 12 with a frequency f.sub.PWM (f.sub.PWM=1/T.sub.PWM).

(23) Reference 18 indicates a summation node which receives at a first input (with a first sign, for instance positive) a set point signal SP indicative of a desired (average) value for the current through the load L.

(24) Reference 20 denotes a sensing arrangement which may include a current sense amplifier (CSA) 20a coupled to the output from the driver D. The sensing arrangement 20 may thus be sensitive to the value of the current through the load L, that is, I.sub.S (FIG. 1) or I.sub.LOAD (FIG. 2).

(25) As exemplified in FIG. 1, the sensing arrangement 20 may include a current sense amplifier 20a which sensesin any manner known to those of skill in the artthe current through the load L (for instance I.sub.S, in the case of FIG. 1) and generates therefrom a scaled-down version I.sub.X of I.sub.S (for instance I.sub.X=I.sub.S/256o) which is supplied to an analog-to-digital converter (ADC) 20b.

(26) An essentially similar arrangement can be adopted in the solution exemplified in FIG. 2 to generate Ix as a scaled-down version of I.sub.LOAD.

(27) In arrangements as exemplified in FIGS. 1 and 2, the sensing current I.sub.X (however generated), possibly converted to a digital format at 20b, can be supplied to an averaging circuit 22 to generate a corresponding average signal.

(28) For instance, as exemplified in FIG. 2, the averaging circuit can comprise a (digital) integrator 22a operated at a frequency f.sub.CK and providing an average (integrated) value of N subsequent samples of the signal from the analog-to-digital converter 20b, such a value possibly down-sampled at a frequency f.sub.PWM corresponding to the frequency of the PWM signal from the generator 12 at a down-sampling circuit block 22b.

(29) As exemplified in FIGS. 1 and 2, the average signal thus obtained is supplied to the summation node 18 where the feedback signal is combined (with an opposed sign, e.g. negative, and thus subtracted) from the set point signal SP with the combined (difference) from the node 18 input to the (e.g., PID) controller 14.

(30) The signal PID from the controller 14 is applied to the (first) input of the comparator 12 to vary the duty cycle of the PWM signal from the PWM generator 12 so that the value of the duty cycle is controlled in a closed loop arrangement using the set point signal SP as a target so that the (average) value of the load current (I.sub.S or I.sub.LOAD) can be set to a desired value as expressed by the signal SP (from a respective source such as a system microcontroller, not visible in the figures).

(31) FIGS. 1 and 2 are thus exemplary of a closed-loop control arrangements 10 comprising:

(32) an analogue portion 10A (right side of the figures) which facilitates generating a signal (I.sub.X, for instance) indicative of the current I.sub.S, I.sub.LOAD through the load L,

(33) a digital portion (left side of the figures) where such a signal indicative of the current in the load, converted to digital in 20b, is supplied to the averaging circuit 22 and then forwarded as a feedback signal towards the summation node 18 and the (e.g., PID) controller 14 with the associated PWM signal generator.

(34) The feedback loop thus provided facilitates closed-loop control of the load current I.sub.S, I.sub.LOAD with a target given by the set point value SP.

(35) It will be otherwise appreciated that arrangements as exemplified in FIGS. 1 and 2 are substantially conventional in the art, which makes it unnecessary to provide a more detailed description herein.

(36) In arrangements as exemplified in FIGS. 1 and 2 both the averaging stage 22 and the integral and derivative branches of the PID controller 14 (namely 142 and 143) are intended to be clocked (essentially, updated) at the same frequency of the PWM signal, f.sub.PWM=1/T.sub.PWM.

(37) In arrangements as exemplified in FIGS. 1 and 2 the internal signals and the output signal PID from the controller 14 are updated (only) once at each cycle of the PWM signal of duration T.sub.PWM.

(38) Stated otherwise, in arrangements as exemplified in FIGS. 1 and 2, the internal, input and output signals of the controller 13 are practically constant within each interval corresponding to the period T.sub.PWM of the PWM signal.

(39) It is noted that computation of the average value in the circuit block 22 (in the integrator 22a of FIG. 2, for instance) involves a delay or latency in the feedback control loop equal to one cycle T.sub.PWM of the PWM signal.

(40) It is observed that such a delay or latency may penalize the response speed of the control-loop.

(41) Correspondingly low values for the coefficients K.sub.P, K.sub.1 and K.sub.D are thus adopted in the controller 14 in order to facilitate frequency stability. For instance, it is observed that selecting for the coefficients K.sub.P, K.sub.1, K.sub.D values which facilitate keeping overshoot (undershoot) under 10% with respect to a typical specification value may result in a delay of 15 mS in the response to a (positive or negative) step in the set point SP before the controlled entity (that is the average value of the current through the load) returns within a range of e.g., 1% of the desired value.

(42) Similarly one may observe that in an arrangement as exemplified in FIGS. 1 and 2 a positive/negative step from 10 V to 15 V (or from 15 V to 10 V) in the supply voltage VS may result in a transient current of +35% (23%) over a time interval of 6 mS (10 mS).

(43) In one or more embodiments, those issues may be addressed by resorting to an arrangement as exemplified in FIGS. 3 and 4.

(44) In FIGS. 3 and 4 parts or elements like parts or elements already discussed in connection with FIGS. 1 and 2 are indicated by like references, so that a corresponding detailed description will not be repeated here for brevity.

(45) This applies, for instance (but not exclusively) to operation of the PWM signal generator 12 and control of the duty cycle of the PWM signal from the signal generator as a function of the signal PID from the controller 14.

(46) Also, as exemplified in FIG. 3, the load L may be coupled between the supply voltage VS and the output of the power driver circuit D and be traversed by a current I.sub.S; as exemplified in FIG. 4, the load L may be coupled between the output of the power driver circuit D at a voltage V.sub.LOAD and ground GND and be traversed by a current I.sub.LOAD.

(47) In one or more embodiments as exemplified in FIGS. 3 and 4 the averaging circuit 22 is removed from the control-loop so that the output signal from the sensing arrangement 20 (for instance the digital signal from the analog-to-digital converter 20b) is supplied to the (negative sign) input of the summation node 18 without being subjected to averaging.

(48) For the sake of completeness, FIG. 4 exemplifies certain embodiments where, while removed from the feedback loop, the averaging circuit 22 (e.g., 22a, 22b) is retained arranged (outside) the control-loop to provide an averaged version of the signal from the sensing arrangement 20 (20a, 20b) as possibly desirable for other purposes (which per se may not be related to embodiments).

(49) Still in connection with the representation of FIGS. 3 and 4, it will be appreciated that the load L (with the driver stage D associated therewith) may represent a distinct element from embodiments.

(50) In brief, in an arrangement as exemplified in FIGS. 3 and 4, the internal signals as well as the output signal PID from the controller 14 may be updated continuously, that is within each cycle of the PWM signal with a frequency f.sub.CK (1 MHz, for instance) which may be substantially higher than the frequency f.sub.PWM of the PWM signal (1 KHz, for instance).

(51) The values indicated (which, of course, are in no way mandatory) are exemplary of a possible selection of a frequency f.sub.CK which is significantly higher than the frequency f.sub.PWM. For instance, as exemplified herein, the frequency f.sub.CK can be selected at a value which is at least one order and optionally (about) three orders of magnitude higher than the frequency f.sub.PWM (that is f.sub.CK/f.sub.PWM=103).

(52) This may be regarded as a sort of oversampling applied to the internal signals, the input signal and the output signal of the PID control arrangement so that these signals may vary (extensively) within each period T.sub.PWM of the PWM signal.

(53) Removing the averaging arrangement 22 (22a, 22b) from the control loop (by possibly locating it outside the control loop as exemplified in FIG. 4) and consequently updating the signals in the PID control arrangement with a frequency (possibly much) higher than the frequency of the PWM signal dispenses with the delay or latency (equal to one cycle of the PWM signal) exhibited in arrangement as exemplified in FIGS. 1 and 2.

(54) This facilitates selecting for the coefficients K.sub.P, K.sub.1 and K.sub.D fairly high values without detriment to frequency stability. This in turn facilitates a faster response to transients in the set point signal (SP) and improved rejection to undesired variations in the supply signal (VS).

(55) For instance, in one or more embodiments as exemplified herein, selecting for the coefficients K.sub.P, K.sub.1, K.sub.D values which facilitate keeping overshoot (undershoot) under 10% with respect to a typical specification value, may result in a delay of 4 mS in the response to a (positive or negative) step in the set point SP before the controlled entity (that is the average value of the current through the load) returns within a range of e.g., 1% of the desired value. This response to an input step is approximately three times faster than the corresponding performance observed in an arrangement as shown in FIGS. 1 and 2.

(56) Similarly, one may observe that in one or more embodiments as exemplified in FIGS. 3 and 4 a positive/negative step from 10 V to 15 V (or from 15 V to 10 V) applied to the supply voltage VS may result in a transient current of +3% (4%) over a time interval of 3 mS (2 mS).

(57) Possible performance of embodiments are exemplified herein is presented in FIGS. 5A, 5B and 6 which show over time abscissa scales in ms:

(58) a possible time behavior of a load current I.sub.LOAD (FIG. 4) and its average value I.sub.AVERAGE (OS=overshoot) in the presence of a normalized upward step in the set point value SP (FIG. 5A);

(59) a corresponding behavior of the PID current from the controller 14 and the ramp signal R.sub.amp to the PWM generator 12 (FIG. 5B);

(60) a possible time behavior of a load current I.sub.S (FIG. 3) in the presence of a square wave variation between 0.5 and 1 in the set point value SP showing overshoot/undershoot confined within 10% (FIG. 6).

(61) One or more embodiments as exemplified in FIGS. 3 and 4 thus facilitate improving performance in respect of perturbations (on VS) with a sensitivity ten times lower over time durations three times shorter in comparison with conventional arrangements.

(62) As exemplified herein, a method of controlling a PWM signal generator (e.g., 12) configured (see, e.g., the power driver D) to provide a supply current (e.g., I.sub.S in FIG. 3 or I.sub.LOAD in FIG. 4) to an electrical load (e.g., L), the PWM signal generator generating PWM (Pulse-Width-Modulation) signals at a first frequency (e.g., f.sub.PWM), the PWM signals having a duty cycle (that is the ratio of the on time to the sum of the on time and the off time) may comprise:

(63) receiving a set point signal (e.g., SP) indicative of a target (e.g., average) value for said supply current;

(64) sensing (e.g., 20; 20a, 20b) a sensing signal (e.g., I.sub.X) indicative of a current (actual) value for said supply current;

(65) performing a closed-loop control of said supply current targeting (that is, having as a target) said target value for said supply current via a controller (e.g., 14, for instance a PID controller such as 141, 142, 143) controlling (e.g., via the signal indicated as PID) the duty cycle of the PWM signals generated by the PWM signal generator as a function of the offset (e.g., as calculated at the node 18) of the sensing signal with respect to the set point signal.

(66) As exemplified herein, the sensing signal may be forwarded to said controller in the absence of averaging processing applied to said sensing signal. As shown in FIG. 4, such averaging processing may still be performed, yet out of the control loop.

(67) As exemplified herein, a discrete-time version of the sensing signal may be produced (e.g., as a digitally converted version produced in the ADC 20b) and the duty cycle of the PWM signals generated by the PWM signal generator controlled as a function of the offset (e.g., as calculated at 18) of said discrete-time version of the sensing signal with respect to the set point signal.

(68) As exemplified herein, the controller circuit may comprise at least one signal processing branch (e.g., the branches 142, 143) operating on discrete-time signals at a second frequency (e.g., f.sub.CLK), wherein the method comprises selecting said second frequency as a multiple of said first frequency.

(69) As exemplified herein, said second frequency may be selected at least one order of magnitude (that is, 10 times) and optionally about three orders of magnitude (that is, 103 times) higher than said first frequency.

(70) As exemplified herein, the controller may comprise a PID controller including an integral branch (e.g., 142; K.sub.1, 142a) and a derivative branch (e.g., 143; K.sub.D, 143a) operating on discrete-time (e.g., digitally converted) signals.

(71) As exemplified herein, the controller may be a digital controller and the method may comprise forwarding (e.g., via the node 18) to said controller said sensing signal in digital form (e.g., as converted at 20b).

(72) As exemplified herein, a circuit may comprise:

(73) a PWM signal generator configured to provide a supply current to an electrical load, the PWM signal generator generating PWM signals with a first frequency, the PWM signals having a duty cycle;

(74) a controller configured to receive an offset signal indicative of the offset of a sensing signal indicative of a current (actual) value for said supply current with respect to a set point signal indicative of a target (e.g., average) value for said supply current;

(75) the controller configured to perform a closed-loop control of said supply current targeting said target value for said supply current by controlling the duty cycle of the PWM signals generated by the PWM signal generator as a function of said offset signal with the method As exemplified herein.

(76) As exemplified herein, a device may comprise:

(77) a circuit as exemplified herein; and

(78) an electrical load (e.g., L) coupled to said PWM signal generator to receive said supply current.

(79) Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only without departing from the extent of protection.

(80) The extent of protection is determined by the annexed claims.