Method and system for detecting clock failure

Abstract

System and method for detecting clock failure are disclosed. The system includes a pulse train generator, a delay circuit, and a failure detection circuit. The pulse train generator receives an input clock and generates a pulse train including a plurality of pulses aligned with a set of rising edges and a set of falling edges of the input clock. The delay circuit delays the input clock by a first time-interval to generate a first delayed clock. The failure detection circuit receives the pulse train and the first delayed clock from the pulse train generator and the delay circuit, respectively, and generates a clock detection signal that transitions from a first logic state to a second logic state based on a failure in the input clock.

Claims

1. A system for detecting clock failure, the system comprising: a pulse train generator that is configured to receive an input clock and generate a pulse train including a plurality of pulses aligned with a set of rising edges and a set of falling edges of the input clock; a delay circuit that is configured to delay the input clock by a first time-interval to generate a first delayed clock; and a failure detection circuit that is coupled to the pulse train generator and the delay circuit, and configured to receive the pulse train and the first delayed clock, and generate a clock detection signal that transitions from a first logic state to a second logic state based on a failure in the input clock.

2. The system of claim 1, wherein the pulse train generator comprises: a first delay element that is configured to delay the input clock by a second time-interval to generate a second delayed clock; a first logic gate that is coupled to the first delay element, and configured to receive the second delayed clock and the input clock, and generate a first intermediate signal that includes a first set of pulses aligned with the set of rising edges of the input clock; a second logic gate that is coupled to the first delay element, and configured to receive the second delayed clock and the input clock, and generate a second intermediate signal that includes a second set of pulses aligned with the set of falling edges of the input clock; and a third logic gate that is coupled to the first and second logic gates, and configured to receive the first and second intermediate signals and generate the pulse train.

3. The system of claim 2, wherein each of the plurality of pulses of the pulse train have a first pulse width corresponding to the second time-interval.

4. The system of claim 2, wherein the first time-interval is greater than a clock period of the input clock and the second time-interval is less than half of the clock period.

5. The system of claim 1, wherein the delay circuit comprises a second plurality of delay elements that are coupled in a series arrangement, and configured to receive the input clock, delay the input clock by the first time-interval, and generate the first delayed clock.

6. The system of claim 1, wherein the failure detection circuit comprises: a first reset synchronizer circuit that is coupled to the pulse train generator and the delay circuit, and configured to receive the pulse train and the first delayed clock, and generate a first detection signal, wherein the first detection signal transitions from the first logic state to the second logic state based on the failure during a first phase of the input clock; a second reset synchronizer circuit that is coupled to the pulse train generator and the delay circuit, and configured to receive the pulse train and the first delayed clock, and generate a second detection signal, wherein the second detection signal transitions from the first logic state to the second logic state based on the failure during a second phase of the input clock; a fourth logic gate that is coupled to the first and second reset synchronizer circuits, and configured to receive the first and second detection signals, and generate a third detection signal; and a fifth logic gate that is coupled to the fourth logic gate, and configured to receive the third detection signal and an enable input, and generate the clock detection signal.

7. The system of claim 6, wherein the first reset synchronizer circuit comprises: a first flip-flop that has: (i) a first reset terminal that is coupled to the pulse train generator, and configured to receive the pulse train, (ii) a first clock terminal that is coupled to the delay circuit, and configured to receive the first delayed clock, and (iii) a first output terminal that is configured to generate a first flip-flop output; and a second flip-flop that has: (i) a first input terminal that is coupled to the first output terminal, and configured to receive the first flip-flop output, (ii) a second reset terminal that is coupled to the pulse train generator, and configured to receive the pulse train, (iii) a second clock terminal that is configured to receive an inverted version of the first delayed clock, and (iv) a second output terminal that is configured to generate the first detection signal.

8. The system of claim 6, wherein the second reset synchronizer circuit comprises: a third flip-flop that has: (i) a third reset terminal that is coupled to the pulse train generator, and configured to receive the pulse train, (ii) a third clock terminal that is configured to receive an inverted version of the first delayed clock, and (iii) a third output terminal that is configured to generate a second flip-flop output; and a fourth flip-flop that has: (i) a second input terminal that is coupled to the third output terminal, and configured to receive the second flip-flop output, (ii) a fourth reset terminal that is coupled to the pulse train generator, and configured to receive the pulse train, (iii) a fourth clock terminal that is coupled to the delay circuit, and configured to receive the first delayed clock, and (iv) a fourth output terminal that is configured to generate the second detection signal.

9. The system of claim 6, wherein the first phase is a low phase of the input clock and the second phase is a high phase of the input clock.

10. A system-on-chip (SoC), comprising: a clock source that is configured to generate an input clock; a clock failure detection system that is coupled to the clock source, and configured to detect clock failure, the clock failure detection system comprising: a pulse train generator that is configured to receive the input clock, and generate a pulse train including a plurality of pulses aligned with a set of rising edges and a set of falling edges of the input clock; a delay circuit that is configured to delay the input clock by a first time-interval to generate a first delayed clock; and a failure detection circuit that is coupled to the pulse train generator and the delay circuit, and configured to receive the pulse train and the first delayed clock, and generate a clock detection signal that transitions from a first logic state to a second logic state based on a failure in the input clock.

11. The SoC of claim 10, wherein the pulse train generator comprises: a first delay element that is configured to delay the input clock by a second time-interval to generate a second delayed clock; a first logic gate that is coupled to the first delay element, and configured to receive the second delayed clock and the input clock, and generate a first intermediate signal that includes a first set of pulses aligned with the set of rising edges of the input clock; a second logic gate that is coupled to the first delay element, and configured to receive the second delayed clock and the input clock, and generate a second intermediate signal that includes a second set of pulses aligned with the set of falling edges of the input clock; and a third logic gate that is coupled to the first and second logic gates, and configured to receive the first and second intermediate signals and generate the pulse train.

12. The SoC of claim 10, wherein the delay circuit comprises a second plurality of delay elements that are coupled in a series arrangement, and configured to receive the input clock, delay the input clock by the first time-interval, and generate the first delayed clock.

13. The SoC of claim 10, wherein the failure detection circuit comprises: a first reset synchronizer circuit that is coupled to the pulse train generator and the delay circuit, and configured to receive the pulse train and the first delayed clock, and generate a first detection signal, wherein the first detection signal transitions from the first logic state to the second logic state based on the failure during a first phase of the input clock; a second reset synchronizer circuit that is coupled to the pulse train generator and the delay circuit, and configured to receive the pulse train and the first delayed clock, and generate a second detection signal, wherein the second detection signal transitions from the first logic state to the second logic state based on the failure during a second phase of the input clock; a fourth logic gate that is coupled to the first and second reset synchronizer circuits, and configured to receive the first and second detection signals, and generate a third detection signal; and a fifth logic gate that is coupled to the fourth logic gate, and configured to receive the third detection signal and an enable input, and generate the clock detection signal.

14. The SoC of claim 13, wherein the first reset synchronizer circuit comprises: a first flip-flop that has: (i) a first reset terminal that is coupled to the pulse train generator, and configured to receive the pulse train, (ii) a first clock terminal that is coupled to the delay circuit, and configured to receive the first delayed clock, and (iii) a first output terminal that is configured to generate a first flip-flop output; and a second flip-flop that has: (i) a first input terminal that is coupled to the first output terminal, and configured to receive the first flip-flop output, (ii) a second reset terminal that is coupled to the pulse train generator, and configured to receive the pulse train, (iii) a second clock terminal that is configured to receive an inverted version of the first delayed clock, and (iv) a second output terminal that is configured to generate the first detection signal.

15. The SoC of claim 13, wherein the second reset synchronizer circuit comprises: a third flip-flop that has: (i) a third reset terminal that is coupled to the pulse train generator, and configured to receive the pulse train, (ii) a third clock terminal that is configured to receive an inverted version of the first delayed clock, and (iii) a third output terminal that is configured to generate a second flip-flop output; and a fourth flip-flop that has: (i) a second input terminal that is coupled to the third output terminal, and configured to receive the second flip-flop output, (ii) a fourth reset terminal that is coupled to the pulse train generator, and configured to receive the pulse train, (iii) a fourth clock terminal that is coupled to the delay circuit, and configured to receive the first delayed clock, and (iv) a fourth output terminal that is configured to generate the second detection signal.

16. The SoC of claim 13, wherein the first phase is a low phase of the input clock and the second phase is a high phase of the input clock.

17. A method for detecting clock failure, the method comprising: generating, by a pulse train generator of a clock failure detection system, a pulse train including a plurality of pulses aligned with a set of rising edges and a set of falling edges of an input clock; delaying, by a delay circuit of the clock failure detection system, the input clock by a first time-interval to generate a first delayed clock; receiving, by a failure detection circuit of the clock failure detection system, the pulse train and the first delayed clock; and generating, by the failure detection circuit, a clock detection signal based on the pulse train and the first delayed clock, wherein the clock detection signal transitions from a first logic state to a second logic state based on a failure in the input clock.

18. The method of claim 17, further comprising: delaying, by the pulse train generator, the input clock by a second time-interval to generate a second delayed clock; and generating, by the pulse train generator, first and second intermediate signals based on the second delayed clock and the input clock, wherein the first intermediate signal includes a first set of pulses aligned with the set of rising edges of the input clock and the second intermediate signal includes a second set of pulses aligned with the set of falling edges of the input clock, and wherein the pulse train is generated based on the first and second intermediate signals.

19. The method of claim 18, wherein each of the plurality of pulses of the pulse train have a first pulse width corresponding to the second time-interval, and wherein the first time-interval is greater than a clock period of the input clock and the second time-interval is less than half of the clock period.

20. The method of claim 17, further comprising: generating, by the failure detection circuit, first and second detection signals based on the pulse train and the first delayed clock, wherein the first detection signal transitions from the first logic state to the second logic state based on the failure during a first phase of the input clock and the second detection signal transitions from the first logic state to the second logic state based on the failure during a second phase of the input clock; and receiving, by the failure detection circuit, an enable input, wherein the clock detection signal is further generated based on the first and second detection signals and the enable input.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The following detailed description of the preferred embodiments of the present disclosure will be better understood when read in conjunction with the appended drawings. The present disclosure is illustrated by way of example, and not limited by the accompanying figures, in which like references indicate similar elements.

(2) FIG. 1 illustrates a schematic block diagram of a system-on-chip (SoC) in accordance with an embodiment of the present disclosure;

(3) FIG. 2 is a timing diagram that illustrates an operation of a pulse train generator of the SoC of FIG. 1 in accordance with an embodiment of the present disclosure;

(4) FIG. 3 is a timing diagram that illustrates an operation of a clock failure detection system of the SoC of FIG. 1 when a temporary clock failure occurs during a first phase of an input clock in accordance with an embodiment of the present disclosure;

(5) FIG. 4 is a timing diagram that illustrates an operation of the clock failure detection system of the SoC of FIG. 1 when the temporary clock failure occurs during a second phase of the input clock in accordance with an embodiment of the present disclosure;

(6) FIG. 5 is a timing diagram that illustrates an operation of the clock failure detection system of the SoC of FIG. 1 when a permanent clock failure occurs in the input clock in accordance with an embodiment of the present disclosure; and

(7) FIGS. 6A and 6B, collectively represent a flowchart that illustrates a method for detecting clock failure in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION

(8) The detailed description of the appended drawings is intended as a description of the currently preferred embodiments of the present disclosure, and is not intended to represent the only form in which the present disclosure may be practiced. It is to be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the present disclosure.

(9) FIG. 1 illustrates a schematic block diagram of a system-on-chip (SoC) 100 in accordance with an embodiment of the present disclosure. The SoC 100 includes a clock source 102 that is configured to generate an input clock Clk.sub.in, and a clock failure detection system 104 that is coupled to the clock source 102 and configured to detect failure in the input clock Clk.sub.in. It will be understood by those of ordinary skill in the art that the SoC 100 includes various other circuits and systems for its operation, which are not shown in order not to obscure the disclosure. The SoC 100 may be included in various devices such as automotive devices, mobile devices, network devices, industrial robotic devices, or the like. The clock failure detection system 104 includes a delay circuit 106, a pulse train generator 108, and a failure detection circuit 110.

(10) The delay circuit 106 is an electronic circuit that is coupled to the clock source 102, and configured to receive the input clock Clk.sub.in from the clock source 102. The delay circuit 106 is further configured to delay the input clock Clk.sub.in by a first time-interval t.sub.1 and generate a first delayed clock Dclk1. The delay circuit 106 includes first through nm delay elements 112a-112n coupled in a series arrangement. Hereinafter, the first through n.sup.th delay elements 112a-112n are collectively referred to as a plurality of delay elements 112a-112n. The plurality of delay elements 112a-112n are configured to receive the input clock Clk.sub.in, delay the input clock Clk.sub.in by the first time-interval t.sub.1, and generate the first delayed clock Dclk1. The first time-interval t.sub.1 refers to a collective delay introduced in the input clock Clk.sub.in by the plurality of delay elements 112a-112n. In order to fulfill a minimum delay requirement across process, voltage or temperature (PVT) compensation, the first time-interval t.sub.1 is set to be greater than a clock period of the input clock Clk.sub.in. In one embodiment, the plurality of delay elements 112a-112n include an even number of NOT (inverter) gates. Other examples of the plurality of delay elements 112a-112n include, but are not limited to, buffers, delay cells, and the like.

(11) It will be apparent to a person skilled in the art that the scope of the present disclosure is not limited to the delay circuit 106 as illustrated in the FIG. 1. In various other embodiments, the delay circuit 106 may be realized using a different set of logic gates or components to achieve the same functionality as described in the foregoing description.

(12) The pulse train generator 108 is an electronic circuit that is coupled to the clock source 102. The pulse train generator 108 is configured to receive the input clock Clk.sub.in from the clock source 102 and generate a pulse train P_Tr. The pulse train P_Tr includes a plurality of pulses aligned with a set of rising edges and a set of falling edges of the input clock Clk.sub.in. The pulse train generator 108 includes an n+1.sup.th delay element 114 and first through third logic gates 116, 118, and 120.

(13) The n+1.sup.th delay element 114 is coupled to the clock source 102, and configured to receive the input clock Clk.sub.in from the clock source 102 and generate a second delayed clock Dclk2. The n+1.sup.th delay element 114 is configured to delay the input clock Clk.sub.in by a second time-interval t.sub.2 to generate the second delayed clock Dclk2. The second time-interval t.sub.2 is greater than a minimum pulse width requirement of the failure detection circuit 110 and less than half of a clock period of the input clock Clk.sub.in. In one embodiment, the n+1.sup.th delay element is a NOT gate.

(14) The first logic gate 116 is coupled to the clock source 102 and the n+1.sup.th delay element 114, and configured to receive the input clock Clk.sub.in from the clock source 102 and the second delayed clock Dclk2 from the n+1.sup.th delay element 114. The first logic gate 116 is further configured to generate a first intermediate signal FI.sub.sig. The first intermediate signal FI.sub.sig includes a first set of pulses aligned with the set of rising edges of the input clock Clk.sub.in. In one embodiment, the first logic gate 116 is an AND gate and a pulse width of each pulse in the first intermediate signal FI.sub.sig is equal to the second time-interval t.sub.2.

(15) The second logic gate 118 is coupled to the clock source 102 and the n+1.sup.th delay element 114, and configured to receive the input clock Clk.sub.in from the clock source 102 and the second delayed clock Dclk2 from the n+1.sup.th delay element 114. The second logic gate 118 is further configured to generate a second intermediate signal SI.sub.sig. The second intermediate signal SI.sub.sig includes a second set of pulses aligned with the set of falling edges of the input clock Clk.sub.in. In one embodiment, the second logic gate 118 is a NOR gate and a pulse width of each pulse in the second intermediate signal SI.sub.sig is equal to the second time-interval t.sub.2.

(16) The third logic gate 120 is coupled to the first and second logic gates 116 and 118, and configured to receive the first and second intermediate signals FI.sub.sig and SI.sub.sig from the respective first and second logic gates 116 and 118. The third logic gate 120 is further configured to generate the pulse train P_Tr. In one embodiment, the third logic gate 120 is an OR gate. Thus, the pulse train P_Tr is an ORed combination of the first and second intermediate signals FI.sub.sig and SI.sub.sig, and each of the plurality of pulses of the pulse train P_Tr has a pulse width corresponding to (i.e., equal to) the second time-interval t.sub.2.

(17) It will be apparent to a person skilled in the art that the scope of the present disclosure is not limited to the pulse train generator 108 as illustrated in FIG. 1. In various other embodiments, the pulse train generator 108 may be realized using a different set of logic gates to achieve the same functionality as described in the foregoing description.

(18) The failure detection circuit 110 is coupled to the delay circuit 106 and the pulse train generator 108. The failure detection circuit 110 is configured to receive the pulse train P_Tr from the pulse train generator 108 and the first delayed clock Dclk1 from the delay circuit 106, and generate a clock detection signal CD.sub.sig. The clock detection signal CD.sub.sig transitions from a first logic state (e.g., a logic low state) to a second logic state (e.g., a logic high state) based on a clock failure in the input clock Clk.sub.in. The failure detection circuit 110 includes a first reset synchronizer circuit 122, a second reset synchronizer circuit 124, and fourth and fifth logic gates 126 and 128.

(19) The first reset synchronizer circuit 122 is coupled to the pulse train generator 108 and the delay circuit 106. The first reset synchronizer circuit 122 is configured to receive the pulse train P_Tr from the pulse train generator 108 and the first delayed clock Dclk1 from the delay circuit 106, and generate a first detection signal FD.sub.sig. The first detection signal FD.sub.sig transitions from the first logic state to the second logic state based on the clock failure during a first phase of the input clock Clk.sub.in. In one embodiment, the first phase is a low phase of the input clock Clk.sub.in. The first reset synchronizer circuit 122 includes a first flip-flop 130 and a second flip-flop 132. The first flip-flop 130 is a positive edge triggered flip-flop and the second flip-flop 132 is a negative edge triggered flip-flop.

(20) In one embodiment, the first flip-flop 130 is a data flip-flop (D flip-flop). The first flip-flop 130 has a first reset terminal that is coupled to the pulse train generator 108 and configured to receive the pulse train P_Tr. The first flip-flop 130 further has a first clock terminal that is coupled to the delay circuit 106 and configured to receive the first delayed clock Dclk1, and a first input terminal that is configured to receive a voltage input V.sub.DD. In one example, the voltage input V.sub.DD may be 5 volts. At every rising edge of the pulse train P_Tr, the first flip-flop 130 is reset. The first flip-flop 130 further has a first output terminal that is configured to generate a first flip-flop output FF.sub.out based on the pulse train P_Tr, the first delayed clock Dclk1, and the voltage input V.sub.DD.

(21) In one embodiment, the second flip-flop 132 is a D flip-flop. The second flip-flop 132 has a second reset terminal that is coupled to the pulse train generator 108 and configured to receive the pulse train P_Tr, and a second clock terminal that is configured to receive an inverted version of the first delayed clock Dclk1. The second flip-flop 132 further has a second input terminal that is coupled to the first flip-flop 130 and configured to receive the first flip-flop output FF.sub.out. At every rising edge of the pulse train P_Tr, the second flip-flop 132 is reset. The second flip-flop 132 further has a second output terminal that is configured to generate the first detection signal FD.sub.sig based on the first flip-flop output FF.sub.out, the pulse train P_Tr, and the inverted version of the first delayed clock Dclk1.

(22) The second reset synchronizer circuit 124 is coupled to the pulse train generator 108 and the delay circuit 106. The second reset synchronizer circuit 124 is configured to receive the pulse train P_Tr from the pulse train generator 108 and the first delayed clock Dclk1 from the delay circuit 106, and generate a second detection signal SD.sub.sig. The second detection signal SD.sub.sig transitions from the first logic state to the second logic state based on the clock failure during a second phase of the input clock Clk.sub.in. In one embodiment, the second phase is a high phase of the input clock Clk.sub.in. The second reset synchronizer circuit 124 includes a third flip-flop 134 and a fourth flip-flop 136. The third flip-flop 134 is a negative edge triggered flip-flop and the fourth flip-flop 136 is a positive edge triggered flip-flop.

(23) In one embodiment, the third flip-flop 134 is a D flip-flop. The third flip-flop 134 has a third reset terminal that is coupled to the pulse train generator 108 and configured to receive the pulse train P_Tr. The third flip-flop 134 further has a first clock terminal that is configured to receive the inverted version of the first delayed clock Dclk1 and a third input terminal that is configured to receive the voltage input V.sub.DD. At every rising edge of the pulse train P_Tr, the third flip-flop 134 is reset. The third flip-flop 134 further has a third output terminal that is configured to generate a second flip-flop output SF.sub.out based on the pulse train P_Tr, the inverted version of the first delayed clock Dclk1, and the voltage input V.sub.DD.

(24) In one embodiment, the fourth flip-flop 136 is a D flip-flop. The fourth flip-flop 136 has a fourth reset terminal that is coupled to the pulse train generator 108 and configured to receive the pulse train P_Tr, and a fourth clock terminal that is coupled to the delay circuit 106 and configured to receive the first delayed clock Dclk1. The fourth flip-flop 136 further has a fourth input terminal that is coupled to the third flip-flop 134 and configured to receive the second flip-flop output SF.sub.out. At every rising edge of the pulse train P_Tr, the fourth flip-flop 136 is reset. The fourth flip-flop 136 further has a fourth output terminal that is configured to generate the second detection signal SD.sub.sig based on the second flip-flop output SF.sub.out, the pulse train P_Tr, and the first delayed clock Dclk1. The pulse train P_Tr has the pulse width that satisfies minimum pulse width requirements of the first through fourth reset terminals. Thus, the second time-interval t.sub.2 is configured in such a manner that the minimum pulse width requirements of the first through fourth reset terminals is satisfied.

(25) The first and second reset synchronizer circuits 122 and 124 are further coupled to the fourth logic gate 126. The fourth logic gate 126 is configured to receive the first and second detection signals FD.sub.sig and SD.sub.sig and generate a third detection signal TD.sub.sig. In one embodiment, the fourth logic gate 126 is an OR gate. Thus, the third detection signal TD.sub.sig is an ORed combination of the first and second detection signals FD.sub.sig and SD.sub.sig. The fourth logic gate 126 is further coupled to the fifth logic gate 128.

(26) The fifth logic gate 128 is configured to receive an enable input En and the third detection signal TD.sub.sig and generate the clock detection signal CD.sub.sig. The clock failure detection system 104 is enabled or disabled based on the enable input En. For example, when the enable input En is active (e.g., at a logic high state), the clock failure detection system 104 is enabled to detect clock failure and when the enable input En is inactive (e.g., at a logic low state), the clock failure detection system 104 is disabled. In one embodiment, the fifth logic gate 128 is an AND gate. The fifth logic gate 128 performs an AND operation on the enable input En and the third detection signal TD.sub.sig to generate the clock detection signal CD.sub.sig. Thus, when the enable input En is active, the clock detection signal CD.sub.sig transitions from the first logic state to the second logic state when the third detection signal TD.sub.sig transitions from the first logic state to the second logic state.

(27) In one embodiment, the clock detection signal CD.sub.sig may be stored in memory for maintaining a log of the clock failure. Further, the clock detection signal CD.sub.sig may be routed to a fault handler (not shown). The fault handler, upon receiving the clock detection signal CD.sub.sig, is configured to initiate a recovery mechanism to recover the input clock Clk.sub.in from the clock failure.

(28) FIG. 2 is a timing diagram 200 that illustrates an operation of the pulse train generator 108, in accordance with an embodiment of the present disclosure. During time period T.sub.0-T.sub.17, the pulse train generator 108 receives the input clock Clk.sub.in from the clock source 102. The n+1.sup.th delay element 114 delays the input clock Clk.sub.in by the second time-interval t.sub.2 to generate the second delayed clock Dclk2.

(29) During time period T.sub.0-T.sub.2, the input clock Clk.sub.in is at logic low state and the second delayed clock Dclk2 is at logic high state. Since the first intermediate signal FI.sub.sig is generated based on an AND operation between the input clock Clk.sub.in and the second delayed clock Dclk2, the first intermediate signal FI.sub.sig remains at logic low state during the time period T.sub.0-T.sub.2. Since the second intermediate signal SI.sub.sig is generated based on a NOR operation between the input clock Clk.sub.in and the second delayed clock Dclk2, the second intermediate signal SI.sub.sig remains at logic low state during the time period T.sub.0-T.sub.2. As the pulse train P_Tr is generated based on an OR operation between the first and second intermediate signals FI.sub.sig and SI.sub.sig, the pulse train P_Tr remains at logic low state during the time period T.sub.0-T.sub.2.

(30) At time instance T.sub.2, the input clock Clk.sub.in transitions from logic low state to logic high state (i.e., a rising edge occurs) whereas the second delayed clock Dclk2 remains at logic high state. As a result, the first intermediate signal FI.sub.sig and the pulse train P_Tr transition from logic low state to logic high state. However, the second intermediate signal SI.sub.sig remains at logic low state.

(31) At time instance T.sub.a (where, T.sub.a=T.sub.2+t.sub.2), the second delayed clock Dck2 transitions from logic high state to logic low state whereas the input clock Clk.sub.in remains at logic high state. As a result, the first intermediate signal FI.sub.sig and the pulse train P_Tr transition from logic high state to logic low state. The second intermediate signal SI.sub.sig continues to remain at logic low state. Thus, during the time period T.sub.2-T.sub.a, a pulse that has a pulse width equal to the second time-interval t.sub.2 is formed in each of the first intermediate signal FI.sub.sig and the pulse train P_Tr. The pulse is aligned with the rising edge of the input clock Clk.sub.in at the time instance T.sub.2.

(32) During time period T.sub.a-T.sub.4, the input clock Clk.sub.in is at logic high state and the second delayed clock Dclk2 is at logic low state. As a result, the first intermediate signal FI.sub.sig, the second intermediate signal SI.sub.sig, and the pulse train P_Tr remain at logic low state.

(33) At time instance T.sub.4, the input clock Clk.sub.in transitions from logic high state to logic low state (i.e., a falling edge occurs) whereas the second delayed clock Dclk2 remains at logic low state. As a result, the second intermediate signal SI.sub.sig and the pulse train P_Tr transition from logic low state to logic high state. However, the first intermediate signal FI.sub.sig remains at logic low state.

(34) At time instance T.sub.b (where, T.sub.b=T.sub.4+t.sub.2), the second delayed clock Dclk2 transitions from logic low state to logic high state whereas the input clock Clk.sub.in remains at logic low state. As a result, the second intermediate signal SI.sub.sig and the pulse train P_Tr transition from logic high state to logic low state. The first intermediate signal FI.sub.sig continues to remain at logic low state. Thus, during the time period T.sub.4-T.sub.b, another pulse that has a pulse width equal to the second time-interval t.sub.2 is formed in each of the second intermediate signal SI.sub.sig and the pulse train P_Tr. The pulse is aligned with the falling edge of the input clock Clk.sub.in at the time instance T.sub.4.

(35) Similarly, due to rising edges of the input clock Clk.sub.in at time instances T.sub.6, T.sub.10, and T.sub.14, pluses having the pulse width equal to the second time-interval t.sub.2 are formed in the first intermediate signal FI.sub.sig and the pulse train P_Tr. Further, due to falling edges of the input clock Clk.sub.in at time instances T.sub.8, T.sub.12, and T.sub.16, pluses having the pulse width equal to the second time-interval t.sub.2 are formed in the second intermediate signal SI.sub.sig and the pulse train P_Tr.

(36) FIG. 3 is a timing diagram 300 that illustrates an operation of the clock failure detection system 104 when the temporary clock failure occurs during the first phase of the input clock Clk.sub.in accordance with an embodiment of the present disclosure. The first phase is the low phase of the input clock Clk.sub.in.

(37) During time period T.sub.18-T.sub.28, the input clock Clk.sub.in operates normally without any clock failure. The rising edges of the input clock Clk.sub.in occur at time instances T.sub.20 and T.sub.24 and the falling edges of the input clock Clk.sub.in occur at time instances T.sub.22 and T.sub.26. Since the first delayed clock Dclk1 is generated by delaying the input clock Clk.sub.in by the first time-interval t.sub.1 (e.g., one clock period of the input clock Clk.sub.in), the rising edges of the first delayed clock Dclk1 occur at time instances T.sub.24 and T.sub.28 and the falling edges of the first delayed clock Dclk1 occur at time instances T.sub.26 and T.sub.30. Since pulses in the pulse train P_Tr are aligned with the rising and falling edges of the input clock Clk.sub.in, the pulses occur at time instances T.sub.20, T.sub.22, T.sub.24, and T.sub.26. The enable input En is activated at time instance T.sub.20 to enable the clock failure detection system 104. At time instances T.sub.20, T.sub.22, T.sub.24, and T.sub.26, the pulse train P_Tr resets the first through fourth flip-flops 130, 132, 134, and 136. As a result, the first flip-flop output FF.sub.out, the first detection signal FD.sub.sig, the second flip-flop output SF.sub.out, and the second detection signal SD.sub.sig remain at logic low state during time period T.sub.18-T.sub.26. As a result, the clock detection signal CD.sub.sig remains at logic low state during time period T.sub.18-T.sub.26.

(38) At time instance T.sub.28, the input clock Clk.sub.in fails to transit from logic low state to logic high state. Thus, a clock failure is observed at the low phase of the input clock Clk.sub.in. Due to the clock failure, rising and falling edges are absent in the input clock Clk.sub.in at time instances T.sub.28 and T.sub.30. As a result, no pulse is present in the pulse train P_Tr at time instances T.sub.28 and T.sub.30 to reset the first through fourth flip-flops 130, 132, 134, and 136.

(39) At time instance T.sub.28, the first delayed clock Dclk1 transitions from logic low state to logic high state. The first flip-flop 130 is triggered by the rising edge of the first delayed clock Dclk1, and as a result, the first flip-flop output FF.sub.out transitions from logic low state to logic high state. Since the second flip-flop 132 is negative edge triggered, the first detection signal FD.sub.sig remains at logic low state. Further, as the third flip-flop 134 is negative edge triggered, the second flip-flop output SF.sub.out remains at logic low state, and as a result the second detection signal SD.sub.sig remains at logic low state. The clock detection signal CD.sub.sig also remains at logic low state.

(40) At time instance T.sub.30, the first delayed clock Dclk1 transitions from logic high state to logic low state and the first flip-flop output FF.sub.out remains at logic high state. The second flip-flop 132 is triggered by the falling edge of the first delayed clock Dclk1, and as a result, the first detection signal FD.sub.sig transitions from logic low state to logic high state. Similarly, the third flip-flop 134 is triggered by the falling edge of the first delayed clock Dclk1, and as a result, the second flip-flop output SF.sub.out transitions from logic low state to logic high state. However, the second detection signal SD.sub.sig remains at logic low state. Due to the transition in the first detection signal FD.sub.sig, the clock detection signal CD.sub.sig also transitions from logic low state to logic high state, thus indicating the clock failure in the input clock Clk.sub.in.

(41) During time period T.sub.3-T.sub.32, the first flip-flop output FF.sub.out, the first detection signal FD.sub.sig, the second flip-flop output SF.sub.out, and the clock detection signal CD.sub.sig remain at logic high state. The second detection signal SD.sub.sig remains at logic low state.

(42) At time instance T.sub.32, the input clock Clk.sub.in recovers from the clock failure, and as a result, a rising edge is observed in the input clock Clk.sub.in. Thus, the pulse train P_Tr includes a pulse at time instance T.sub.32. The first through fourth flip-flops 130, 132, 134, and 136 are reset by the pulse train P_Tr. As a result, the first flip-flop output FF.sub.out, the first detection signal FD.sub.sig, and the second flip-flop output SF.sub.out transition from logic high state to logic low state. The second detection signal SD.sub.sig remains at logic low state. The clock detection signal CD.sub.sig also transitions from logic high state to logic low state, indicating recovery from the clock failure.

(43) FIG. 4 is a timing diagram 400 that illustrates an operation of the clock failure detection system 104 when the temporary clock failure occurs during the second phase of the input clock Clk.sub.in, accordance with an embodiment of the present disclosure. In one embodiment, the second phase is the high phase of the input clock Clk.sub.in.

(44) During time period T.sub.38-T.sub.46, the input clock Clk.sub.in operates normally without any clock failure. The rising edges of the input clock Clk.sub.in occur at time instances T.sub.40 and T.sub.44 and the falling edges of the input clock Clk.sub.in occur at time instance T.sub.42. Since the first delayed clock Dclk1 is generated by delaying the input clock Clk.sub.in by the first time-interval t.sub.1 (e.g., one clock period of the input clock Clk.sub.in), the rising edges of the first delayed clock Dclk1 occur at time instances T.sub.44 and T.sub.48 and the falling edge of the first delayed clock Dclk1 occur at time instance T.sub.46. Since pulses in the pulse train P_Tr are aligned with the rising and falling edges of the input clock Clk.sub.in, the pulses occur at time instances T.sub.40, T.sub.42, and T.sub.44. The enable input En is activated at time instance T.sub.40 to enable the clock failure detection system 104. At time instances T.sub.40, T.sub.42, and T.sub.44, the pulse train P_Tr resets the first through fourth flip-flops 130, 132, 134, and 136. As a result, the first flip-flop output FF.sub.out, the first detection signal FD.sub.sig, the second flip-flop output SF.sub.out, and the second detection signal SD.sub.sig remain at logic low state during time period T.sub.38-T.sub.44. As a result, the clock detection signal CD.sub.sig remains at logic low state during time period T.sub.38-T.sub.44.

(45) At time instance T.sub.46, the input clock Clk.sub.in fails to transition from logic high state to logic low state. Thus, a clock failure is observed at the high phase of the input clock Clk.sub.in. Due to the clock failure, rising and falling edges at time instances T.sub.46 and T.sub.48 are absent. As a result, no pulse is present in the pulse train P_Tr at time instances T.sub.46 and T.sub.48 to reset the first through fourth flip-flops 130, 132, 134, and 136.

(46) At time instance T.sub.46, the first delayed clock Dclk1 transitions from logic high state to logic low state. Since the first flip-flop 130 is positive edge trigged, the first flip-flop output FF.sub.out remains at logic low state, and as a result the first detection signal FD.sub.sig remains at logic low state. Further, as the third flip-flop 134 is negative edge triggered, the third flip-flop 134 is triggered by the falling edge of the first delayed clock Dclk1 and the second flip-flop output SF.sub.out transitions from logic low state to logic high state. Since the fourth flip-flop 136 is positive edge triggered, the second detection signal SD.sub.sig remains at logic low state. The clock detection signal CD.sub.sig also remains at logic low state.

(47) At time instance T.sub.48, the first delayed clock Dclk1 transitions from logic low state to logic high state and the second flip-flop output SF.sub.out, remains at logic high state. The first flip-flop 130 is triggered by the rising edge of the first delayed clock Dclk1, and as a result, the first flip-flop output FF.sub.out transitions from logic low state to logic high state. However, the first detection signal FD.sub.sig remains at logic low state. The fourth flip-flop 136 is triggered by the rising edge of the first delayed clock Dclk1, and as a result, the second detection signal SD.sub.sig transitions from logic low state to logic high state. Due to transition in the second detection signal SD.sub.sig, the clock detection signal CD.sub.sig also transitions from logic low state to logic high state, thus indicating the clock failure in the input clock Clk.sub.in.

(48) During time period T.sub.48-T.sub.50, the first flip-flop output FF.sub.out, the second flip-flop output SF.sub.out, the second detection signal SD.sub.sig, and the clock detection signal CD.sub.sig remain at logic high state. The first detection signal FD.sub.sig remains at logic low state.

(49) At time instance T.sub.50, the input clock Clk.sub.in recovers from the clock failure, and as a result, a falling edge is observed in the input clock Clk.sub.in. Thus, the pulse train P_Tr includes a pulse at time instance T.sub.50. The first through fourth flip-flops 130, 132, 134, and 136 are reset by the pulse train P_Tr. As a result, the first flip-flop output FF.sub.out, the second flip-flop output SF.sub.out, and the second detection signal SD.sub.sig, transition from logic high state to logic low state. The first detection signal FD.sub.sig remains at logic low state. The clock detection signal CD.sub.sig also transitions from logic high state to logic low state, indicating recovery from the clock failure.

(50) FIG. 5 is a timing diagram 500 that illustrates an operation of the clock failure detection system 104 when a permanent clock failure occurs in the input clock Clk.sub.in in accordance with an embodiment of the present disclosure.

(51) During time period T.sub.58-T.sub.66, the input clock Clk.sub.in operates normally without any clock failure. The rising edges of the input clock Clk.sub.in occur at time instances T.sub.60 and T.sub.64 and the falling edge of the input clock Clk.sub.in occurs at time instance T.sub.62. Since the first delayed clock Dclk1 is generated by delaying the input clock Clk.sub.in by the first time-interval t.sub.1 (e.g., one clock period of the input clock Clk.sub.in), the rising edges of the first delayed clock Dclk1 occur at time instances T.sub.64 and T.sub.68 and the falling edge of the first delayed clock Dclk1 occurs at time instance T.sub.66. Since pulses in the pulse train P_Tr are aligned with the rising and falling edges of the input clock Clk.sub.in, the pulses occur at time instances T.sub.60, T.sub.62, and T.sub.64. The enable input En is activated at time instance T.sub.60 to enable the clock failure detection system 104. At time instances T.sub.60, T.sub.62, and T.sub.64, the pulse train P_Tr resets the first through fourth flip-flops 130, 132, 134, and 136. As a result, the first flip-flop output FF.sub.out, the first detection signal FD.sub.sig, the second flip-flop output SF.sub.out, and the first detection signal FD.sub.sig remain at logic low state during time period T.sub.58-T.sub.64. As a result, the clock detection signal CD.sub.sig remains at logic low state during time period T.sub.58-T.sub.64.

(52) At time instance T.sub.66, the input clock Clk.sub.in fails to transition from logic high state to logic low state. Thus, a clock failure is observed at the high phase of the input clock Clk.sub.in. Due to the clock failure, rising and falling edges during time period T.sub.66-T.sub.77 are absent. As a result, no pulse is present in the pulse train P_Tr during time period T.sub.66-T.sub.77.

(53) At time instance T.sub.66, the first delayed clock Dclk1 transitions from logic high state to logic low state. Since the first flip-flop 130 is positive edge trigged, the first flip-flop output FF.sub.out remains at logic low state, and as a result the first detection signal FD.sub.sig remains at logic low state. Further, as the third flip-flop 134 is negative edge triggered, the second flip-flop output SF.sub.out transitions from logic low state to logic high state. Since the fourth flip-flop 136 is positive edge triggered, the second detection signal SD.sub.sig remains at logic low state. The clock detection signal CD.sub.sig also remains at logic low state.

(54) At time instance T.sub.68, the first delayed clock Dclk1 transitions from logic low state to logic high state and the second flip-flop output SF.sub.out remains at logic high state. The first flip-flop 130 is triggered by the rising edge of the first delayed clock Dclk1, and as a result the first flip-flop output FF.sub.out transitions from logic low state to logic high state. However, the first detection signal FD.sub.sig remains at logic low state. The fourth flip-flop 136 is triggered by the rising edge of the first delayed clock Dclk1, and as a result, the second detection signal SD.sub.sig transitions from logic low state to logic high state. Due to transition in the second detection signal SD.sub.sig, the clock detection signal CD.sub.sig also transitions from logic low state to logic high state, thus indicating the clock failure in the input clock Clk.sub.in.

(55) During time period T.sub.68-T.sub.77, the input clock Clk.sub.in fails to recover and the first flip-flop output FF.sub.out, the second flip-flop output SF.sub.out, and the second detection signal SD.sub.sig remain at logic high state. Hence, the clock detection signal CD.sub.sig also retains the logic high state. Therefore, the permanent clock failure is detected in the input clock Clk.sub.in.

(56) FIGS. 6A and 6B, collectively represent a flowchart 600 that illustrates a method for detecting clock failure in accordance with an embodiment of the present disclosure.

(57) At step 602, the input clock Clk.sub.in is received by the delay circuit 106 and the pulse train generator 108 from the clock source 102. At step 604, the input clock Clk.sub.in is delayed by the first time-interval t.sub.1 to generate the first delayed clock Dclk1 by the delay circuit 106. At step 606, the input clock Clk.sub.in is delayed by the second time-interval t.sub.2 to generate the second delayed clock Dclk2 by the pulse train generator 108. For example, the n+1.sup.th delay element 114 in the pulse train generator 108 delays the input clock Clk.sub.in by the second time-interval t.sub.2. At step 608, the first intermediate signal FI.sub.sig and the second intermediate signal SI.sub.sig are generated based on the input clock Clk.sub.in and the second delayed clock Dclk2 by the pulse train generator 108. For example, the first logic gate 116 in the pulse train generator 108 generates the first intermediate signal FI.sub.sig and the second logic gate 118 in the pulse train generator 108 generates the second intermediate signal SI.sub.sig. At step 610, the pulse train P_Tr is generated based on the first intermediate signal FI.sub.sig and the second intermediate signal SI.sub.sig by the pulse train generator 108. The third logic gate 120 in the pulse train generator 108 generates the pulse train P_Tr including the plurality of pulses aligned with the set of rising edges and the set of falling edges of the input clock Clk.sub.in.

(58) At step 612, the pulse train P_Tr and the first delayed clock Dclk1 are received by the failure detection circuit 110. At step 614, the first and second detection signals FD.sub.sig and SD.sub.sig are generated based on the pulse train P_Tr and the first delayed clock Dclk1 by the failure detection circuit 110. The first and second reset synchronizer circuits 122 and 124 in the failure detection circuit 110 generate the first and second detection signals FD.sub.sig and SD.sub.sig, respectively. At step 616, the enable input En is received by the failure detection circuit 110. The clock failure detection system 104 is enabled or disabled based on the enable input En. For example, when the enable input En is active (e.g., at a logic high state), the clock failure detection system 104 is enabled to detect the clock failure and when the enable input En is inactive (e.g., at a logic low state), the clock failure detection system 104 is disabled.

(59) At step 618, the clock detection signal CD.sub.sig is generated based on the first detection signal FD.sub.sig, the second detection signal SD.sub.sig, and the enable input En by the failure detection circuit 110. In other words, the clock detection signal CD.sub.sig is generated by the failure detection circuit 110 based on the pulse train P_Tr and the first delayed clock Dclk1.

(60) The clock failure detection system 104 disclosed herein facilitates an uninterrupted monitoring of the input clock Clk.sub.in for detecting clock failure. The clock failure detection system 104 mitigates the need of any reference clock signal or analog circuitry for detecting failure in the input clock Clk.sub.in, thus resulting in significant cost and size reduction as compared to conventional clock failure detection systems. Although, the clock failure detection system 104 is described herein to detect failure in a single clock, the clock failure detection system 104 is scalable to perform simultaneous monitoring of multiple clock inputs. Further, the clock failure detection system 104 is stable and robust, hence performs significantly well under all device conditions such as different temperature and humidity values. Further, use of dual flip-flops in each of the first and second reset synchronizer circuits 122 and 124 eliminates occurrence metastability issues in the clock failure detection system 104. Therefore, the clock failure detection system 104 is significantly immune to noise and variations in device parameters such as voltage, temperature, and the like. Therefore, the clock failure detection system 104 provides efficient and low-cost solution for detecting clock failure in the input clock Clk.sub.in.

(61) While various embodiments of the present disclosure have been illustrated and described, it will be clear that the present disclosure is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the present disclosure, as described in the claims.