METHOD FOR OPERATING A POWER ELECTRONIC CONVERTER DEVICE WITH FLOATING CELLS

Abstract

Described herein is a method of operating a power electronic converter device for an electrical power conversion system. The power electronic converter device includes a converter circuit including an input side, an output side, a first converter, and at least one second converter. The second converter includes at least one floating cell with a DC intermediate circuit and semiconductor devices. The method includes: switching the semiconductor devices of the floating cell at switching instants determined with optimized pulse patterns or carrier-based pulse width modulation; determining a fundamental voltage component for the floating cell; and generating the fundamental voltage component in the actual voltage of the floating cell by modifying the switching instants, such that a voltage V.sub.C AF of the DC intermediate circuit is lying in a given reference voltage range for balancing the DC intermediate circuit of the floating cell.

Claims

1. A method for operating a power electronic converter device for an electrical power conversion system, the power electronic converter device comprising a converter circuit including an input side with input terminals, an output side with at least one AC output terminal, a first converter with semiconductor devices connected to the input terminals and at least one second converter connected between an AC output of the first converter and the AC output terminal, said second converter comprising at least one floating cell with a DC intermediate circuit and semiconductor devices, the method comprising: switching the semiconductor devices of the floating cell at switching instants determined with optimized pulse patterns or carrier-based pulse width modulation; determining a fundamental voltage component for the floating cell, which fundamental voltage component depends on a difference between an actual voltage V.sub.C AF of the DC intermediate circuit of the floating cell and a reference value V.sub.C AF* for the voltage of the DC intermediate circuit; and generating the fundamental voltage component in an actual voltage of the floating cell by modifying the switching instants, such that a voltage V.sub.C AF of the DC intermediate circuit is lying in a given reference voltage range.

2. The method according to claim 1, wherein the fundamental voltage component is generated in the actual voltage of the floating cell, such that the voltage V.sub.C AF of the DC intermediate circuit is kept at the reference value V.sub.C AF*.

3. The method according to claim 1, wherein the fundamental voltage component is zero when the DC intermediate circuit of the floating cell is at the reference value V.sub.C AF*.

4. The method according to claim 1, wherein the fundamental voltage component is generated by a PI controller, whose input is the difference between the actual voltage V.sub.C AF of the DC intermediate circuit and the reference value V.sub.C AF*.

5. The method of claim 4, wherein a variable gain of the PI controller is adjusted in dependence of a fundamental component of a phase current flowing through the floating cell.

6. The method according to one of the previous claims claim 1, wherein the fundamental voltage component has a phase angle relative to a fundamental component of a phase current flowing through the floating cell in a range of −85°-+85° when charging the floating cell and of 95°-265° when discharging the floating cell.

7. The method according to claim 6, wherein the fundamental voltage component is in phase with said fundamental component of the phase current when charging the floating cell; and wherein the fundamental voltage component has a phase difference of 180° from said fundamental component of the phase current when discharging the floating cell.

8. The method according to claim 1, further comprising: switching the semiconductor devices of the first converter at switching instants determined with optimized pulse patterns or carrier-based pulse width modulation; and generating a fundamental voltage component in a voltage output by the first converter by modifying the switching instants applied to the first converter, wherein the fundamental voltage component in the voltage output by the first converter is determined in dependence of the fundamental voltage component determined for the floating cell.

9. The method according to claim 8, wherein the fundamental voltage component of the voltage at the first converter is modified, such that a fundamental component of a voltage at the at least one AC output terminal is kept constant; and/or wherein the fundamental voltage component generated by the floating cell is canceled out by the fundamental voltage component generated by the first converter.

10. The method according to claim 1, wherein the switching instants for the floating cell are modified by adjusting switching angles of the optimized pulse patterns; wherein an adjustment of the switching angles of the semiconductor devices of the floating cell is based on a sign of a corresponding switching transition; and/or wherein an adjustment of the switching angles of the semiconductor devices of the floating cell is based on appropriate gains related to the nominal switching angles of the optimized pulse patterns.

11. The method according to claim 1, wherein, when the floating cell is switched with carrier-based pulse width modulation, the switching instants are modified by adding a sinusoidal signal at a fundamental frequency to a reference of the carrier-based pulse width modulation.

12. The method according to claim 1, wherein, when both the first converter and the at least one floating cell are switched with optimized pulse patterns, the optimized pulse patterns of the first converter and the at least one floating cell are selected such that a weighted total harmonic distortion of a sum of the voltages of the DC intermediate circuit and an output voltage of the first converter is minimized.

13. A computer program product comprising computer-executable program code portions having program code instructions configured to execute the method according to claim 1 when loaded into a computer-based control device.

14. A non-transitory computer-readable medium, in which a computer program according to claim 13 is stored.

15. A power electronic converter device for an electrical power conversion system, the power electronic converter device comprising: a converter circuit including an input side with input terminals, an output side with at least one AC output terminal, a first converter with semiconductor devices connected to the input terminals and at least one second converter connected between an AC output of the first converter and an AC output terminal, said second converter comprising at least one floating cell with a DC intermediate circuit and semiconductor devices; and a control device for driving the semiconductor devices of the at least one floating cell, wherein the control device is configured for performing the method according to claim 1.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0047] These and other aspects of the present disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter. Individual features disclosed in the embodiments can constitute alone or in combination an aspect of the present disclosure. Features of the different embodiments can be carried over from one embodiment to another embodiment.

[0048] In the drawings:

[0049] FIG. 1 shows a schematic diagram of a converter circuit with a first and a second converter of a power electronic converter device according to a first embodiment of the present disclosure.

[0050] FIG. 2 shows a schematic diagram of a power electronic converter device according to a second embodiment of the present disclosure together with a three-phase load connected to the power electronic converter device.

[0051] FIG. 3 shows a schematic schema of the generation of an AF balancing signal for one phase by use of a PI controller.

[0052] FIG. 4 shows phasors of fundamental voltage components of the phase voltage of the first converter of the three-phase converter.

[0053] FIG. 5 shows modification of switching angles of the main converter in order to change the amplitude of the fundamental voltage component.

[0054] FIG. 6 shows a schematic diagram of the arrangement of the controller and a modulator modulating both converters by OPPs.

[0055] FIG. 7 shows a schematic diagram of the arrangement of controller and modulator modulating the first converter by OPPs and the second converter by CB-PWM.

[0056] FIG. 8 shows a schematic diagram of the arrangement of controller and modulator modulating the first converter by CB-PWM and the second converter by OPPs.

DETAILED DESCRIPTION

[0057] FIG. 1 shows a schematic diagram of a converter circuit 10. The converter circuit 10 shows one-phase of a three-phase converter device, which includes an input side 12 with input terminals 14, an output side 16 with an output terminal 18, a first converter 20 and a second converter 22 connected in series with the first converter 20. The first converter 20 is a neutral-point clamped (NPC) converter or an active neutral-point clamped (ANPC) converter. It could be another type of three-level converter, a two level converter or a converter with more than three levels. The first (main) converter 20 includes capacitive elements 24 (depicted as capacitors) and semiconductor devices 26. The second converter 22 includes a series connection of a plurality of floating cells 28. These floating cells 28 function as active filters (AF) and are therefore also called “AF cells” or “H-bridge AF cells”. Each floating cell 28 includes two pairs of semiconductor devices 30 and a DC intermediate circuit 32 with a capacitive element 34 (depicted as capacitor) interconnected between the two pairs of semiconductor devices 30. The capacitive element 34 has a capacitance C.sub.AF leading to a corresponding voltage V.sub.C AF at the DC intermediate circuit 32.

[0058] The basic AF control objective is to compensate the three phase (3L) (A)NPC output waveform harmonics while maintaining the average value of each AF cell capacitor voltage V.sub.C AF at its reference (AF balancing). The balancing control concept should also enable the use of the floating cells 28 as an add-on to existing converters. An additional control requirement is its suitability to modular concepts to ensure it can be easily adjusted to higher DC-link voltages and higher capacitor voltages as well as a higher number of floating cells 28.

[0059] FIG. 2 shows a power electronic converter device 36 according to a first embodiment and a load 38 connected to the output side 20 of the converter device 36. The converter device 36 includes the converter circuit 10 and a control device 40 for driving the semiconductor devices 26, 30 of at least one of the converters 20, 22 via pulse-like signals. The control device 40 drives the semiconductor devices 26, 30 by use of OPPs or CB-PWM such that a respective voltage V.sub.C AF of the DC intermediate circuits 32 is balanced, which means that it is lying in a given reference voltage range.

[0060] In the example the first converter 20 and the floating cells 28 are modulated by OPPs for a three-phase load 38. The steps of the switching transitions of the 3L(A)NPC are higher than the ones of the AF switching transitions. The pulse patterns of the two converters 20, 22 must be computed in such a way that the weighted total harmonic distortion (weighted THD) of the sum of the voltages 42, 44 of the first converter 20 and the cell(s) 28 of the second converter 22 is minimized. Other objective functions can also be considered. Furthermore, the fundamental voltage component must be generated only by the first converter 20 (the 3L(A)NPC converter), the fundamental voltage component of the floating cell(s) 28 is zero since it cannot provide active power. The resulting voltage 46 at the load 38 is depicted as a 3-phase voltage course.

[0061] The OPP-modulated floating cells 28 need a balancing mechanism that ensures that the average voltage of the capacitive element 34 (functioning as an intermediate floating capacitor) remains constant and close to its reference. The present disclosure proposes two balancing approaches.

[0062] The approach is based on the injection of a fundamental AF voltage component which may be in phase with the load current, when charging is desired. For discharging the angle may be 180°. The necessary AF fundamental component for the balancing may be generated by a PI controller unit 48 whose input is the difference between the (filtered) actual voltage of the AF capacitor VC AF and the average value reference VC AF* as shown in FIG. 3. The proportional gain of the PI controller unit 48 can be multiplied with the inverse of the amplitude of the fundamental load current i{circumflex over ( )}L in order to keep the gain of the balancing loop constant and independent of the load current. For low currents the gain can be limited to certain values in order to avoid very big changes in the nominal switching angles. The output of the PI controller unit 48 gives the amplitude of the desired AF fundamental component v{circumflex over ( )}l for the corresponding floating cell 28. Each phase should have one such controller and the control of the AF capacitor voltage in each phase is independent of the other phases.

[0063] Besides modifying the AF fundamental voltage component, the 3L(A)NPC fundamental component must be modified accordingly in order to keep the fundamental component of the voltage at the load terminals the same. The calculation of the desired fundamental 3L(A)NPC phase voltage component is carried out with the help of the phasors of the fundamental voltage components of the 3L(A)NPC and the AF as illustrated in FIG. 4. With the help of the phasor diagram the desired 3L(A)NPC phasor {right arrow over (V)}.sub.1 3L can be calculated from the fundamental component of the nominal OPP {right arrow over (V)}.sub.1 3Lnom for a given AF fundamental component phasor {right arrow over (V)}.sub.1 AF:

{right arrow over (V)}.sub.1 3L={right arrow over (V)}.sub.1 3Lnom−{right arrow over (V)}.sub.1 AF=|{right arrow over (V)}.sub.1 3L|.Math..   (1)

[0064] From the above equation we can calculate the amplitude |{right arrow over (V)}.sub.1 3L| and phase θ of the desired 3L(A)NPC fundamental component. From the former we can calculate the necessary change in the amplitude of the fundamental 3L(A)NPC voltage

ΔV.sub.NPC=|{right arrow over (V)}.sub.1 3L|−|{right arrow over (V)}.sub.1 3Lnom|.   (2)

[0065] The next sections describe how the nominal switching angles are modified in order to generate the necessary 3L(A)NPC and AF fundamental components in each phase.

[0066] By appropriately modifying the switching angles of the original 3L(A)NPC pulse pattern over 2π, α.sub.NPC i, where the index i refers to the i.sup.th switching transition Δu.sub.NPC i, the desired 3L(A)NPC fundamental component can be generated. Different approaches can be used for this modification. In this specific implementation it is done in two steps, one to get the desired amplitude and one to get the desired phase:

[0067] 1) In a first step the amplitude of the fundamental component is modified via addition of an angle ΔαNPCi to each 3L(A)NPC switching angle:

Δα.sub.NPCi=k.Math.s(Δu.sub.NPCi).Math.g.sub.NPC.Math.Δm.sub.NPC,   (3)

[0068] where

[00001]$\begin{array}{cc}\Delta m_{\mathrm{NPC}}=\Delta V_{\mathrm{NPC}}/V_{\mathrm{dc}},k=\{\begin{array}{c}1,{\alpha }_{\mathrm{NPC},i}\le \pi \\ -1,{\alpha }_{\mathrm{NPC},i}>\pi \end{array}& \left(4\right)\end{array}$

[0069] The total dc-link voltage of the first converter (especially 3L(A)NPC converter) 20 is 2Vdc, which is also visible in FIG. 2. The sign of k depends on the half period of the fundamental component of the nominal pulse pattern the switching angle lies in. This is exemplified in FIG. 5. The g.sub.NPC.Math.Δm.sub.NPC part of equation (5) is independent of the actual nominal switching angle, which means that the absolute value of the change is the same for all switching angles, only the sign is switching angle dependent. The gain gNPC defines how big this change should be in order to achieve the desired change in the modulation index. When we have only one switching angle within a quarter wave period and the OPP has both half wave and quarter wave symmetry the necessary gain can be calculated analytically

g.sub.NPC=[α.sub.NPC1 nom−acos(4/π.Math.|{right arrow over (V)}.sub.1 3L|/)]/Δm.sub.NPC.   (5)

[0070] For higher number of switching angles the gain g.sub.NPC is calculated as a function of the modulation index and stored in the OPP. It is calculated by changing the nominal 3L(A)NPC switching angles by Δα.sub.NPCi=k.Math.sign(Δu.sub.NPci).Math.Δ.sub.NPC and calculating the change Δm.sub.NPC that it causes to the modulation index of the 3L(A)NPC:

g.sub.NPC=Δα.sub.NPC/Δm.sub.NPC.   (6)

[0071] 2) Subsequently, the previously calculated angle θ is added to each 3L(A)NPC nominal switching angle in order to obtain the desired phase of the 3L(A)NPC fundamental voltage. The modified 3L(A)NPC switching angles will then be:

α.sub.NPCi=α.sub.NPCi nom+Δα.sub.NPCi−θ.   (7)

[0072] For a three phase load with a phase difference of ±2π/3 for phases b and c the modified 3L(A)NPC switching angles in each phase can be expressed as:

[00002]$\begin{array}{cc}\begin{array}{c}\begin{array}{c}{\alpha }_{\mathrm{NPC},ia}={\alpha }_{\mathrm{NPC},i\mathrm{nom}}-\theta +{\mathrm{\Delta \alpha }}_{\mathrm{NPC},ia}\\ {\alpha }_{\mathrm{NPC},ib}={\alpha }_{\mathrm{NPC},i\mathrm{nom}}-\theta -2\pi /3+{\mathrm{\Delta \alpha }}_{\mathrm{NPC},ib}\end{array}\\ {\alpha }_{\mathrm{NPC},ic}={\alpha }_{\mathrm{NPC},i\mathrm{nom}}-\theta +2\pi /3+{\mathrm{\Delta \alpha }}_{\mathrm{NPC},ic}\end{array}\}.& \left(8\right)\end{array}$

[0073] The desired AF modulation index can be achieved via small modifications of the original AF switching angles (for which the AF modulation index is zero) of the corresponding phase. Before these modifications are done, the angle θ defined previously is added to the nominal switching angles of the AF in order to avoid mismatches between the pulse patterns of the first and second converter 20, 22 (3L(A)NPC and the AF):

α′.sub.AFi=α.sub.AFi nom−θ,   (9)

[0074] where αAFi nom is the i.sup.th nominal AF switching angle.

[0075] Different approaches can be the used for the injection of a fundamental component, for example a modification of the switching angles based on the following formula may be used:

Δα.sub.AFi=Δα.sub.AFmax.Math.sign(Δu.sub.AFi).Math.sin(α′.sub.AFi nom+φ.sub.AF).   (10)

[0076] where Δu.sub.AFi is the switching transition corresponding to the i.sup.th switching angle α.sub.AFi, and φ.sub.AF is the desired phase of the AF fundamental component. φ.sub.AF may be set equal to the phase difference between the fundamental components of the load voltage and the load current, which is denoted as φ.sub.L in FIG. 4. This way the injected AF voltage component is in phase with the load current and we can charge or discharge the AF capacitor more effectively.

[0077] For a desired AF modulation index m.sub.AF one must select the quantity Δα.sub.AFmax accordingly. This is done by multiplying m.sub.AF with a gain, which is OPP-specific and approximately constant for relatively small changes of the nominal switching angles:

g.sub.AF=Δα.sub.AFmax/m.sub.AF   (11)

[0078] It can be precomputed for each pulse pattern as a function of φ.sub.AF and then stored with each OPP of the AF. Often, the influence of φ.sub.AF on the ratio Δα.sub.AFmax/m.sub.AF is negligible and it suffices to store one ratio for each AF pulse pattern (that corresponds to a specific modulation index of the main converter). If the influence of φ.sub.AF is not negligible, the ratio Δα.sub.AFmax/m.sub.AF as a function of φ.sub.AF must be computed stored.

[0079] The calculated angle difference Δα.sub.AFi is added to α′.sub.AFi nom in order to calculate the modified AF switching angle which is going to be used for the AF modulation

α.sub.AFi=α′.sub.AFi+Δα.sub.AF,i.   (12)

[0080] By switching at the modified switching angles we generate the necessary AF fundamental component, which has both the desired amplitude v{circumflex over ( )}.sub.1 AF and phase φ.sub.AF.

[0081] For a three phase load with a phase difference of ±2π/3 for phases b and c the AF switching angles modifications in each phase can be expressed as:

[00003]$\begin{array}{cc}\begin{array}{c}\begin{array}{c}{\alpha }_{\mathrm{AF},ia}={\alpha }_{\mathrm{AF},i\mathrm{nom}}-\theta +{\mathrm{\Delta \alpha }}_{\mathrm{AF},ia}\\ {\alpha }_{\mathrm{AF},ib}={\alpha }_{\mathrm{AF},i\mathrm{nom}}-\theta -2\pi /3+{\mathrm{\Delta \alpha }}_{\mathrm{AF},ib}\end{array}\\ {\alpha }_{\mathrm{AF},ic}={\alpha }_{\mathrm{AF},i\mathrm{nom}}-\theta +2\pi /3+{\mathrm{\Delta \alpha }}_{\mathrm{AF},ic}\end{array}\},& \left(13\right)\end{array}$

[0082] A simplified diagram of a balancing control unit 50 and an OPP modulator unit 52 is shown in FIG. 6. The control unit 50 should compensate only the average capacitor voltage and not the voltage ripple. This can be done by either filtering the measured capacitor voltage fed to the PI control unit 48 with a moving average filter over a suitably selected time window (e.g. half the fundamental period) or by appropriately selecting the bandwidth of the PI control unit 48. Module 54 represents the calculation of the necessary fundamental components of the first converter 20. When calculating the second converter 22 floating cell 28 switching angle changes (represented by module 56) and first converter 20 switching angle changes (represented by module 58) some restrictions have to be considered, which are not described in detail in this document. For example, the modified switching angle can't be higher than the next nominal switching angle. Constraints in the relation between the switching angles of different phases can be also considered if necessary. The calculated first converter switching angle changes are provided to a modulator module 60 for the first converter 20 and the calculated second converter switching angle changes are provided to a modulator module 62 for the second converter 22. Both modulator modules 60, 62 are OPP modulator modules in the example of FIG. 6.

[0083] In the above approach different fundamental components are considered for each phase, since the voltage of the capacitors of the floating cells can be a bit different in each phase. In a variation of the balancing approach the voltages of the capacitors of the floating cells of the different phases are brought to the same value with the help of a common mode (CM) component considered in the modulation of the floating cells. The CM component may be generated either via appropriate modification of the nominal switching angles of the floating cells in all three phases or by using the three-phase redundant switching vectors of the floating cells. In the former case an additional term Δα.sub.i,CM is added to the AF switching angles, which is calculated by

Δα.sub.AF,i=F.sub.max CM.Math.sign(Δu.sub.AFi).Math..   (14)

[0084] As previously for the fundamental component, for a desired CM component m.sub.AF, CM one must select the quantity Δα.sub.AFmax CM accordingly. This is done by multiplying m.sub.AF, CM with a gain, which is OPP-specific and approximately constant for relatively small changes of the nominal switching angles:

g.sub.AF, CM=Δα.sub.AFmax CM/m.sub.AF, CM   (15)

[0085] The term calculated by (14) is added to the term considered in (10), so that the total modification of the switching angles of the floating cells is given by

Δα.sub.AFi=Δα.sub.AFmax CM.Math.sign(Δu.sub.AFi)+Δα.sub.AFmax.Math.sign(Δu.sub.AFi).Math.sin(α′.sub.AFi nom+φ.sub.AF).   (16)

[0086] If redundant vectors are used alternative combinations of the switching states are considered that generate the same differential voltage but different CM voltage. For example instead of the combination [u.sub.Afi,a, u.sub.AFi,b, u.sub.AFi,c]=[1, 1, 0] one can select [u.sub.AFi,a, u.sub.AFi,b, u.sub.AFi,c]=[0, 0, −1]. The difference between two phases remains the same, but the sum of the three phases is different. The selection of a redundant vector or not is based on the prediction of the evolution of the capacitor voltages after one sampling interval in the three phases using the capacitor transfer function and the measured phase current.

[0087] However, the use of redundant vectors will increase the switching frequency of the semiconductors of the floating cells. The switching frequency can be optimized by selecting a suitably long horizon (more than one sampling interval) and include penalization of the number of the necessary switching actions that take place when selecting redundant vectors which will bring the three capacitor voltages close to each other in the considered horizon. The (equal) voltage of the capacitors of the three phases is then brought to the desired reference value by the switching angle modifications described in (3)-(13). Since the voltages in each phase are considered equal the necessary fundamental components for the main converter and the floating cells (shown by phasors in FIG. 4) are the same for all three phases. Only a phase displacement of −2π/3 and +2π/3 compared to phase a will be present in phases b and c respectively.

[0088] A special case that must be carefully treated is when one or more switching angles of the main converter are the same with one or more switching angles of the floating cells. Then only the remaining AF switching angles (which are not the same with any switching angles of the main converter) are used for the generation of the fundamental component of the floating cells. Furthermore, in such a case the modification of the switching angles of the main converter generates a fundamental component also in the floating cells. This must be compensated with the afore mentioned remaining switching angles of the floating cells. The AF fundamental voltage component generated by the modification of the switching angles of the main converter is given by

{right arrow over (v)}.sub.DM,injected=−2.Math.r.sub.AF.Math.Δm.sub.NPC, {right arrow over (v)}.sub.Dm,injected=θ,   (17)

[0089] where r.sub.AF is the ratio between the voltage of the floating cell and half the dc-link voltage of the main converter. The compensation term for the remaining switching angles of the floating cells is then calculated by: Δα.sub.AF,i,DM,comp=2.Math.r.sub.AF.Math.Δm.sub.NPC.Math.g.sub.AF.Math.sign(Δu.sub.AF,i).Math.sin(α.sub.AF,i−θ).Math.(18)

[0090] The same principle applies when the switching angles of the main converter are modified to balance the neutral point, e.g. when the main converter is a 3L(A)NPC. The CM component that will appear in the floating cells due to some simultaneous switchings with the main converter must be compensated by the remaining switching angles of the floating cells.

[0091] If CB-PWM is used for the H-bridge cell(s) 28, the previously discussed modifications are applied only to the switching angles of the first converter 20 (modules 54, 58, 60). The necessary modifications of the AF switching instants are made by simply adding a suitable sinusoidal signal (generated by function generator 64) at the fundamental frequency to the CB-PWM reference of the AF (provided to corresponding modulator module 62). The amplitude of this signal is equal to v{circumflex over ( )}.sub.1 AF divided by the AF voltage and its phase may be equal to the phase of the load current φ.sub.L as shown in FIG. 7. In this case the nominal switching instants of the AF are computed by comparing a reference signal equal to the difference between the 3L(A)NPC reference signal and the 3L(A)NPC output switching states with the carrier signals. The above mentioned “nominal” reference signal is in essence equal to the sum of the 3L(A)NPC output voltage harmonics.

[0092] If CB-PWM is used for the first converter 20, the previously discussed modifications are applied only to the switching angles of the AF. The necessary modifications of the 3L(A)NPC switching instants are made by suitably modifying its CB-PWM reference as shown in FIG. 8. The amplitude of the sinusoidal reference is equal to mNPC nom+ΔmNPC and its phase equal to θ. CM components can also be added to this sinusoidal reference if it is desirable. The proposed balancing schemes facilitate the balancing of the AF cell capacitor voltages when the AF cells and/or the main converter are modulated by OPPs. With OPP modulation we can achieve, in many cases, an improved output voltage quality compared to CB-PWM or other modulation approaches.

[0093] The control algorithm can be implemented on any computational hardware including DSPs, FPGAs, microcontrollers, CPUs, GPUs, multi-core platforms, and combinations thereof.

[0094] In the present disclosure, the first converter 20 is a 3L(A)NPC converter, but the same methods can be applied to other types of three-level converters, including neutral point piloted 3L converter. Embodiments of the present disclosure can also be applied to main converters with two levels or to main converters with more than three levels.

[0095] In the following, important aspects of the implementation of the method will be presented once again in other words:

[0096] 1. the second converter 22 includes one or more auxiliary cells 28;

[0097] 2. the modulation of the first converter 20 and of the second converter 22 is based on OPPs, or the modulation of only the first converter 20 is based on OPPs and CB-PWM is employed for the second converter 22, or the modulation of only the second converter 22 is based on OPPs and CB-PWM is used for the first converter 20;

[0098] 3. the OPPs are pre-computed and stored in look-up tables;

[0099] 4. the entries in the look-up tables contain the switching angles and the corresponding first or second converter switching states as a function of the modulation index and the pulse number;

[0100] 5. the second converter 22 outputs a voltage that is used to optimize the waveform of the sum of the generated voltages of the first and the second converter 20, 22 with respect to different objective functions;

[0101] 6. the computation of the above mentioned OPPs can be computed for different objective functions and performance trade-offs. For example, different OPPs could provide different behaviors of the harmonic distortion of the phase current, the common-mode voltage at the output and the floating capacitor voltage ripple;

[0102] 7. there is a means to detect or to estimate the voltage of the capacitive H-bridge element (floating capacitor) 34 of the second converter 22;

[0103] 8. the average voltage of the floating capacitor 34 is kept to its reference value by modifying the nominal switching angles of the first and second converter 22 stored in look-up tables or by modifying the nominal switching angles of the first converter and the reference signal of the second converter if CB-PWM is used for the second converter 22 or by modifying the reference signal of the first converter 20 and the nominal switching angles of the second converter if CB-PWM is used for the first converter;

[0104] 9. the change of the switching angles is based on manipulative quantities that may correspond to the amplitude of the fundamental voltage components of the first and the second converter 20, 22;

[0105] 10. the manipulative quantities may be generated by a PI control unit 48′, a hysteresis controller 70, or a combination of both. The input of the controller 48′, 70 is the deviation of the capacitor voltage from its reference value;

[0106] 11. the amplitude of the load current value can also be an input to the PI control unit 48′ so that the switching angle modifications are adjusted based also on it;

[0107] 12. the change of the switching angles is subject to restrictions related to the next and previous switching angles in one phase and possibly to the next and previous switching angles in other phases; and

[0108] 13. the capacitor voltage ripple of the second converter 22 is taken into account either by suitable hysteresis bounds for the hysteresis controllers 70 or by filtering the measured voltage with a moving average filter over a suitably selected time window (e.g. half the fundamental period) for the PI control units or by suitably adjusting the bandwidth of the PI control units 48′.