Analog to analog converter with quantized digital controlled amplification

Abstract

Methods and systems for power amplification of time varying envelope signals are disclosed herein. In one embodiment, a plurality of signals with constant envelope generated from the decomposition of the quantized version of a time varying envelope signal are individually amplified and then summed to form a desired time-varying envelope signal. Amplitude, phase and frequency characteristics of one or more of the constituent signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time varying envelope signal. In another embodiment, a time-varying envelope signal is decomposed into in-phase and quadrature components that are quantized and decomposed into a plurality of quasi constant or constant envelope constituent signals. The constituent signals are amplified, and then summed to construct an amplified version of the original time-varying envelope signal. The signal amplifiers may be Class A, B, AB, C, D, Class F or Class S amplifiers to provide high amplification efficiency.

Claims

1. A method of analog to analog conversion with quantized digital controlled amplification, comprising: receiving a frequency reference signal; receiving a clock reference signal; receiving information; generating a plurality of control signals from said received information; generating a plurality of quantization bits and quantization control signals; gerar as amostras temporais do sinal de informao e as amostras da respectiva componente em fase e da componente em quadrature; generating from the quantized signal a plurality of substantially constant envelope signals that vary in amplitude and phase relative to each other using said frequency reference signal and said control signals and said quantization bits and said quantization control signals; providing said substantially constant envelope in-phase and quadrature signals to a multi amplifier amplification (MAA) stage, said MAA stage comprising at least four or more circuit branches each comprising one or more transistors, wherein said substantially constant envelope signals are simultaneously amplified and combined to create a desired output signal of said MAA stage, or providing said substantially constant envelope complex signals to a MAA stage, said MAA stage comprising at least two or more circuit branches each comprising one or more transistors, wherein said substantially constant envelope complex signals are simultaneously amplified and combined to create a desired output signal of said MAA stage.

2. The method of analog to analog conversion with quantized digital controlled amplification according to claim 1, wherein said step of receiving information comprises: receiving one or more time varying envelope information bandpass signals.

3. The method of analog to analog conversion with quantized digital controlled amplification according to claim 1, wherein said step of receiving information comprises: receiving in-phase and quadrature phase components of one or more time varying envelope information bandpass signals.

4. The method of analog to analog conversion with quantized digital controlled amplification according to claim 1, further comprising using one or more biasing control functions to simultaneously amplify and combine said substantially constant envelope signals.

5. The method according to claim 1, further comprising harmonically shaping said desired output signal.

6. The method of analog to analog conversion with quantized digital controlled amplification according to claim 1, further comprising manipulating said control signals to vary power output.

7. The method of analog to analog conversion with quantized digital controlled amplification according to claim 1, wherein: said step of generating a plurality of control signals comprises processing said received information to generate a samples of in-phase and quadrature components of bandpass or baseband information signals; said step of quantization comprises processing said the samples of in-phase and quadrature components of bandpass information signals to generate said quantization bits and quantizer control signals; and said step of generating a plurality of substantially constant envelope signals comprises using said in-phase and quadrature quantization bits and quantizer control signals and control signals to generate said substantially constant envelope constituent signals from the decomposition of the quantized signals.

8. The method of analog to analog conversion with quantized digital controlled amplification according to claim 1, wherein said quantized signals decomposition into constant envelope components comprises at least four constituent signals where two are in-phase constituent signals and other two are quadrature constituent signals.

9. The method of analog to analog conversion with quantized digital controlled amplification according to claim 8, wherein said four constituent signals include two substantially constant envelope in-phase constituent signals that when combined form the in-phase component of said desired output signal, and two substantially constant envelope quadrature constituent signals that when combined form the quadrature component of said desired output signal.

10. The method of analog to analog conversion with quantized digital controlled amplification according to claim 8, wherein said four constituent signals include two in-phase constituent signals and two quadrature constituent signals that are summed to form two substantially constant envelope complex constituent signals that when combined form the desired output signal.

11. An apparatus of analog to analog conversion with quantized digital controlled amplification, comprising: an input circuitry that receives information, and that generates a plurality of control signals from said received information; an input circuitry that receives information, and that generates a plurality of samples from said received information; a quantizer circuitry that coupled to said input circuitry, that receives said control signals, information and a frequency reference signal, and that generates a plurality of quantization bits and quantizer control signals from said received information; a constituent signal mapper circuitry, coupled to said quantizer circuitry, that receives said quantization bits, quantizer control signals and a frequency reference signal, and that generates a plurality of constituent signals and a plurality of said substantially constant envelope signals that vary in amplitude and phase relative to each other using said frequency reference signal, said control signals, said quantization bits and said quantizer control signals; a multi amplifier amplification (MAA) stage that receives said substantially constant envelope signals, said MAA stage comprising at least two or more circuit branches each comprising one or more transistors, wherein said substantially constant envelope signals are simultaneously amplified and combined to create a desired output signal of said MAA stage; outputs of each of said circuit branches of MAA stage are added by said combiner to produce a resulting signal, said signal amplifier outputs being coupled to terminals of an input of said combiner; and amplitude modulation of said resulting signal from said combiner is achieved by an addition of said outputs.

12. The apparatus of analog to analog conversion with quantized digital controlled amplification of claim 11, wherein said received information comprises one or more bandpass time varying envelope information signals.

13. The apparatus of analog to analog conversion with quantized digital controlled amplification of claim 11, wherein said received information comprises in-phase and quadrature phase components of one or more bandpass information signals.

14. The apparatus of analog to analog conversion with quantized digital controlled amplification of claim 11, wherein said received information comprises samples of in-phase and quadrature phase components of one or more time varying envelope bandpass information signals.

15. The apparatus of analog to analog conversion with quantized digital controlled amplification of claim 11, further comprising biasing control circuitry coupled to said MAA stage, wherein said biasing control circuitry operates according to one or more biasing control functions to simultaneously amplify and combine said substantially constant envelope signals.

16. The apparatus of analog to analog conversion with quantized digital controlled amplification of claim 11, further comprising: means for harmonically shaping said desired output signal; and control signals to vary output signal power.

17. The apparatus of claim 11, wherein: said input circuitry processes said received information to generate samples of the in-phase and quadrature amplitude control signals; and said constituent signal mapper circuitry uses said in-phase and quadrature quantization bits and quantizer control signals to generate said substantially constant envelope constituent signals.

18. The apparatus of analog to analog conversion with quantized digital controlled amplification of claim 11, wherein said input circuitry includes digital circuitry that processes said received information and that generates said control signals.

19. The apparatus of analog to analog conversion with quantized digital controlled amplification of claim 11, wherein said mapper circuitry comprises one or more look up tables which are used to process quantized bits and quantization control received information and generate said substantially constant envelope constituent signals.

20. The apparatus of analog to analog conversion with quantized digital controlled amplification of claim 11, wherein said plurality of constituent signals comprises at least four constituent signals.

21. The apparatus of analog to analog conversion with quantized digital controlled amplification of claim 20, wherein said four constituent signals include two substantially constant envelope in-phase signals that when combined form the in-phase component of said desired output signal, and two substantially constant envelope quadrature signals that when combined form the quadrature component of said desired output signal.

22. The apparatus of analog to analog conversion with quantized digital controlled amplification of claim 20, wherein said four constituent signals include two in-phase constituent signals and two quadrature constituent signals that when summed form two substantially constant envelope complex signals that when combined form the desired output signal.

23. The apparatus of analog to analog conversion with quantized digital controlled amplification of claim 11, wherein said MAA stage branches comprises one or more power amplification sub-stages.

24. The apparatus of analog to analog conversion with quantized digital controlled amplification of claim 11, further comprising: means for dynamically controlling said transistors of said circuit branches to thereby transition operation of said transistors along an operational range that includes switching amplifier operation and current source amplifier operation.

25. The apparatus of analog to analog conversion with quantized digital controlled amplification of claim 11, wherein said MAA stage comprises a plurality of said amplifiers from a group comprising: class A signal amplifiers; class B signal amplifiers; class AB signal amplifiers; class D signal amplifiers; class F signal amplifiers; class E signal amplifiers; class S signal amplifiers; class C signal amplifiers.

26. The apparatus of analog to analog conversion with quantized digital controlled amplification of claim 11, wherein said MAA stage comprises a plurality of bipolar junction transistors (BJTs) of type NPN.

27. The apparatus of analog to analog conversion with quantized digital controlled amplification of claim 11, wherein said MAA stage comprises a plurality of bipolar junction transistors (BJTs) of type PNP.

28. The apparatus of analog to analog conversion with quantized digital controlled amplification of claim 11, wherein said MAA stage comprises a plurality of bipolar junction transistors (BJTs) of type NPN or PNP.

29. The apparatus of analog to analog conversion with quantized digital controlled amplification of claim 11, wherein said MAA stage comprises a plurality of Field Effect Transistors (FETs) with N or P Channels.

30. The apparatus of analog to analog conversion with quantized digital controlled amplification of claim 11, wherein said MAA stage comprises a plurality of Field Effect Transistors (FETs) with N or P Channels, namely using silicon based on metaloxide-semiconductor (MOS) technology.

31. The apparatus of analog to analog conversion with quantized digital controlled amplification of claim 11, wherein said MAA stage comprises a plurality of Field Effect Transistors (FETs) with N or P Channels, namely using silicon based on metal-oxide-semiconductor (MOS) technology.

32. The apparatus of analog to analog conversion with quantized digital controlled amplification of claim 11, wherein said MAA stage comprises a plurality of Field Effect Transistors (FETs) with N or P Channels, namely using Gallium arsenide (GaAs) technology, Gallium nitride (GaN) technology and/or silicon-germanium (SiGe) technology.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0057] The various aspects of embodiments of the present invention will be described with reference to the accompanying drawings, wherein generally similar reference numbers indicate identical or functionally similar elements. The various aspects of embodiments disclosed here, including features and advantages of the present invention outlined above are described more fully in the detailed description in conjunction with the drawings in which:

[0058] FIG. 1 is a process flowchart embodiment for power amplification according to the analog to analog converter with quantized digital controlled amplification method.

[0059] FIG. 2A is a block diagram that illustrates an exemplary embodiment of a signal power amplification apparatus for implementing the analog to analog converter with quantized digital controlled amplification method.

[0060] FIG. 2B is a block diagram that illustrates an exemplary embodiment of a signal power amplification apparatus for implementing the analog to analog converter with quantized digital controlled amplification method with constituent signals resulting from the sum of in-phase and quadrature constituent components of the quantized sample of the input signal

[0061] FIG. 3 is a process flowchart embodiment for power amplification according to the I/Q analog to analog converter with quantized Digital controlled amplification method.

[0062] FIG. 4A is a block diagram that illustrates an exemplary embodiment of a signal power amplification apparatus for implementing the I/Q analog to analog converter quantized Digital controlled amplification method with the constituent signals the in-phase and the quadrature components of the quantized sample of the input signal.

[0063] FIG. 4B is a block diagram that illustrates another exemplary embodiment of a signal power amplification apparatus for implementing the I/Q analog to analog converter with quantized Digital controlled amplification method with constituent signals resulting from the sum of in-phase and quadrature constituent components of the quantized sample of the input signal.

[0064] FIG. 5 is a process flowchart embodiment for power amplification according to the On/Off analog to analog converter with quantized digital controlled amplification method.

[0065] FIG. 6A is a block diagram that illustrates an exemplary embodiment of signal power amplification apparatus for implementing the On/Off analog to analog converter with quantized digital controlled amplification method with the constituent signals the in-phase and the quadrature components of the quantized sample of the input signal.

[0066] FIG. 6B is a block diagram that illustrates an exemplary embodiment of signal power amplification apparatus for implementing the On/Off analog to analog converter with quantized digital controlled amplification method with constituent signals resulting from the sum of in-phase and quadrature constituent components of the quantized sample of the input signal.

[0067] FIG. 7 is a block diagram that illustrates an exemplary embodiment for implementing a power amplification stage of analog to analog converter with quantized digital controlled amplification method using class F amplifiers.

[0068] FIG. 8 is a block diagram that illustrates another exemplary embodiment for implementing a power amplification stage of analog to analog converter with quantized digital controlled amplification method using class D amplifiers.

[0069] FIG. 9 is a block diagram that illustrates another exemplary embodiment for implementing a power amplification stage of analog to analog converter with quantized digital controlled amplification method using class A, B, AB, C or class E amplifiers.

[0070] FIG. 10 is a block diagram that illustrates another exemplary embodiment for implementing a power amplification stage of analog to analog converter with quantized digital controlled amplification method using class S amplifiers.

DETAILED DESCRIPTION OF THE INVENTION

Table of Contents

[0071] 1. Introduction [0072] 1.1. Decomposition of time-varying envelope signals into constant envelope components

[0073] 2. Analog to analog converter with quantized digital controlled amplification (AAQDCA) methods and systems [0074] 2.1. Analog to analog converter with quantized digital controlled amplification [0075] 2.2. I/Q analog to analog converter with quantized digital controlled amplification [0076] 2.3 On/Off analog to analog converter with quantized digital controlled amplification

[0077] 3. Multi amplifier amplification stage [0078] 3.1. Multi amplifier amplification stage embodiments

[0079] 4. Summary

[0080] 5. Conclusions

1. INTRODUCTION

[0081] Methods, apparatuses and systems for analog to analog converter with quantized digital controlled amplification (AAQDCA) are disclosed herein. High-level description of AAQDCA methods and systems according to embodiments of the present invention will be provided in next sections 2 and 3.

[0082] The AAQDCA by quantizing and decomposing the quantized envelope signal into constant envelope constituent signals allows the use of non-linear amplifiers in the amplification of time varying envelope signals, avoiding at same time non-linear distortion effects.

[0083] For purposes of convenience, and not limitation, methods and systems of the present invention are sometimes referred as quantized digital controlled amplification (QDCA).

[0084] Some definitions are provided in this section only for convenience purposes, and are not limiting. The meaning of these terms will be apparent for a person skilled in the art based on the entirety of the teachings provided herein.

[0085] Generically, modulated signals can be described by s(t)=s.sub.I(t)cos(w.sub.ct)+j s.sub.Q(t)sin(w.sub.ct), where w.sub.c=2f.sub.c denotes the angular frequency, f.sub.c denotes the carrier frequency, and s.sub.I(t) and s.sub.Q(t) denote the in-phase and the quadrature component, respectively. The signal can be also described in terms of its complex envelope by s(t)=Re{{tilde over (s)}(t)e.sup.jw.sup.c.sup.t}, where {tilde over (s)}(t)=s.sub.I(t)+js.sub.Q(t) denotes the complex envelope, with the signal envelope given by e(t)={square root over ((s.sub.I(t)).sup.2+(s.sub.Q(t)).sup.2)}. When e(t) is constant or quasi constant along time a signal is said as constant envelope signal. Time varying envelope signal refers a signal where e(t) shows amplitude variations with time. Having both non-constant envelope and phase, s(t) is said to be a time-varying complex envelope signal. The dynamic range (DR) of the envelope represents the range of values between which the signal's envelope varies. The dynamic range of the in-phase component (DRi) represents the range of values between which the in-phase component varies. The dynamic range of the quadrature component (DRq) represents the range of values between which the quadrature component varies.

[0086] For purposes of convenience, and not limitation, time varying complex envelope signals are sometimes referred to herein as time varying envelope signals.

1.1 Decomposition of Time-Varying Envelope Signals into Constant Envelope Components

[0087] In a time varying envelope signal the envelope values may assume any value inside the dynamic range of the envelope, which means that the number of possible values for the envelope will be infinite. Without a discretization of the possible magnitude values of the time varying envelope, a phase phasor that represents the signal the outphasing or LINC technique, mentioned before, can be applied to obtain the decomposition into two or more constant magnitude phasors with appropriately specified phase shifts relative to a reference phasor.

[0088] A different approach can be applied to decompose time varying envelope signals into quasi constant or constant envelope components based on the discretization of the signal envelope values, which can be performed by a quantization process. Through the quantization the infinite set of envelope values could be restricted to a finite set of quantizer values or symbols ={s.sub.0, s.sub.1, . . . , s.sub.N.sub.QL.sub.1}, where N.sub.QL dneotes the number of quantization levels, i.e. the size of the alphabet of quantization symbols. Let N.sub.QL denote as s(nT.sub.s)=s.sub.n the time domain sample of the time-varying envelope signal at the sample instant nT.sub.s and s.sub.I(nT.sub.s)=s.sub.nI and s.sub.Q(nT.sub.s)=s.sub.nQ the corresponding in-phase and quadrature components. Dynamic ranges of (nT.sub.s)=s.sub.n, s.sub.I(nT.sub.s)=s.sub.nI and s.sub.Q(nT.sub.s)=s.sub.nQ are DR, DRi and DRq respectively. For purposes of convenience, and not limitation it is assumed that DRi=DRq.

[0089] By the quantization process the time domain sample of the input signal s.sub.n is transformed into a quantized symbol s.sub.n,QT taken from a finite alphabet of N.sub.QL=2.sup.N.sup.b possible quantization symbols. The N.sub.b quantization bits and N.sub.QL=2.sup.N.sup.b quantization levels can be defined in terms of the maximum quantization error

[00001]${\mathrm{.Math.}}_Q=\frac{\mathrm{DR}}{22^{N_b}}=,$

where 2 represents the quantization interval between two adjacent complex quantization symbols. The N.sub.b quantization (.sub.n.sup.(N.sup.b.sup.1), .sub.n.sup.(N.sup.b.sup.2), . . . , .sub.n.sup.(1), .sub.n.sup.(0)) bits are employed in the definition of N.sub.mN.sub.b polar components in which each quantization level can be decomposed. The bits (.sub.n.sup.(N.sup.b.sup.1), .sub.n.sup.(N.sup.b.sup.2), . . . , .sub.n.sup.(1), .sub.n.sup.(0)) are converted into polar form (b.sub.n.sup.(N.sup.b.sup.1), b.sub.n.sup.(N.sup.b.sup.2), . . . , b.sub.n.sup.(1), b.sub.n.sup.(0)) by b.sub.n.sup.(m)=(1).sup..sup.n.sup.(m). The finite set of quantizer symbols ={s.sub.0, s.sub.1, . . . , s.sub.N.sub.QL.sub.1}, where N.sub.QL=2.sup.N.sup.b is the number of quantization levels.

[0090] Each symbol from the finite set of quantizer values or symbols ={s.sub.0, s.sub.1, . . . , s.sub.N.sub.QL.sub.1}, can be represented as a sum of N.sub.mN.sub.b polar components, that are the result of the decomposition of quantization value s.sub.n,QT into polar components or complex components, which is given by

[00002]$s_{n,\mathrm{QT}}=g_0+g_1.Math.b_n^{\left(0\right)}+g_2.Math.b_n^{\left(1\right)}+g_3.Math.b_n^{\left(0\right)}.Math.b_n^{\left(1\right)}+g_4.Math.b_n^{\left(2\right)}+\mathrm{.Math.}=\underset{i=0}{\overset{N_m-1}{.Math.}}.Math.g_i.Math.\underset{m=0}{\overset{N_m-1}{.Math.}}.Math.{\left(b_n^{\left(m\right)}\right)}^{{}_{m,i}}=\underset{i=0}{\overset{N_m-1}{.Math.}}.Math.g_i.Math.b_n^{\mathrm{eq}\left(i\right)},$

with (.sub.N.sub.m.sub.1,i .sub.N.sub.m.sub.2,i . . . .sub.1,i .sub.0,i) denoting the binary representation of i, b.sub.n.sup.(m)=(1).sup..sup.n.sup.(m) denoting the polar representation of the bit .sub.n.sup.(m), b.sub.n.sup.eq(i)=.sub.m=0.sup.N.sup.m.sup.1 (b.sub.n.sup.(m)).sup..sup.m,i denoting the i'th polar compoennts of s.sub.n and N.sub.m is the number of non-null complex coefficients g.sub.i of the referred decomposition equation above (the total number of coefficients is 2.sup.N.sup.b1). For example, for N.sub.b=6 and a symmetrical dynamic range DR (using as reference the zero value) the quantization levels are

[00003]$p.Math.\frac{\sqrt{2}}{2}.Math.\mathrm{jk}.Math.\frac{\sqrt{2}}{2}.Math.,$

with p=1, 3, 5, 7 and k=1, 2, 3 5 7 which can be given by

s.sub.n,QT=g.sub.1b.sub.n.sup.(0)+g.sub.2b.sub.n.sup.(1)+g.sub.4b.sub.n.sup.(2)+g.sub.8b.sub.n.sup.(3)+g.sub.16g.sub.n.sup.(4)+g.sub.32b.sub.n.sup.(5),

with

[00004]$g.Math..Math.1=\frac{\sqrt{2}}{2}.Math.,g.Math..Math.2=j.Math.\frac{\sqrt{2}}{2}.Math.,g.Math..Math.4=2.Math.\frac{\sqrt{2}}{2}.Math.,g.Math..Math.8=j.Math..Math.2.Math.\frac{\sqrt{2}}{2}.Math.,g.Math..Math.16=4.Math.\frac{\sqrt{2}}{2}.Math.,g.Math..Math.32=j.Math..Math.4.Math.\frac{\sqrt{2}}{2}.Math..Math..Math.\mathrm{and}.Math..Math.g_i=0,\mathrm{for}.Math..Math.i1,2,4,8,16,32.$

[0091] The example above refers the case of quantized samples taken from time variant envelope signals. A person skilled in the art, however, will understand that by quantizing the envelope values of any time-variant envelope signal, and decomposing as a sum of a plurality of quasi or constant envelope signals, any time-variant quantized version of the envelope signal can be generated in terms of constant envelope signals.

2. ANALOG TO ANALOG CONVERTER WITH QUANTIZED CONTROLLED AMPLIFICATION METHODS AND SYSTEMS

[0092] AAQDCA methods and systems according to embodiments of the present invention rely on the ability to quantize and decompose any quantized time-varying envelope signal into several substantially constant envelope constituent signals or to generate such constituent signals, amplify the constituent signals, and then sum the amplified signals to generate an amplified version of the time-varying envelope signal. In sections 2.1-2.3, embodiments of the present invention are provided, including 6 amplification branch embodiments with all branches active or controlled branch activation depending on the polarity of the quantized signal. In the following descriptions, each embodiment is first presented conceptually using a mathematical derivation of underlying concepts of the embodiment. Three embodiments of a method of operation of the QDCA are then presented, followed by various system level embodiments. In the next embodiments for purposes of convenience, and not limitation it is assumed that DRi=DRq.

2.1 Analog to Analog Converter with Quantized Digital Controlled Amplification

[0093] According to one embodiment of the invention, herein called QDCA for ease of illustration and not limitation, a time varying envelope signal is decomposed into 6 quasi or constant envelope constituent signals and DRi=DRq. The constituent signals are amplified individually, and then summed to construct an amplified version of the original time-varying complex envelope signal.

[0094] According to another embodiment of the invention, herein called quantized digital controlled amplification with complex components (QDCAC) for ease of illustration and not limitation, a time varying envelope signal is decomposed into 6 quasi or constant envelope constituent signals and DRi=DRq. The in-phase and quadrature constituent signals with same amplitude are summed to generate 3 complex constituent signals that are amplified individually, and then summed to construct an amplified version of the original time-varying complex envelope signal.

[0095] It is noted that 6 or 3 branches are employed in these embodiments, it is also assumed DRi=DRq and the same number of quantization bits for in-phase and quadrature components for purposes of illustration, and not limitation. The scope of the invention covers the use of other numbers of branches, DRiDRq and different number of quantization bits for the in-phase and quadrature components and implementation of such variations will be apparent to persons skilled in the art based on the teachings contained herein.

[0096] Accordingly, in the QDCA and QDCAC embodiments the time domain sample of the signal s.sub.n is transformed into a quantized symbol s.sub.n,QT taken from a finite alphabet of 2.sup.N.sup.b complex quantization symbols. The N.sub.b quantization bits and N.sub.QL=2.sup.N.sup.b quantization levels can be defined in terms of the maximum quantization error

[00005]${\mathrm{.Math.}}_Q=\frac{\mathrm{DR}}{22^{N_b}}=,$

where 2 represents the quantization interval. The N.sub.b quantization (.sub.n.sup.(N.sup.b.sup.1), .sub.n.sup.(N.sup.b.sup.2), . . . , .sub.n.sup.(1), .sub.n.sup.(0)) bits are employed in the definition of N.sub.mN.sub.b complex components in which each quantization level can be decomposed. The bits (.sub.n.sup.(N.sup.b.sup.1), .sub.n.sup.(N.sup.b.sup.2), . . . , .sub.n.sup.(1), .sub.n.sup.(0)) are converted into polar form (b.sub.n.sup.N.sup.b.sup.1), b.sub.n.sup.(N.sup.b.sup.2), . . . , b.sub.n.sup.(1), b.sub.n.sup.(0)) by b.sub.n.sup.(m)=(1).sup..sup.n.sup.(m). The finite set of quantizer symbols ={s.sub.0, s.sub.1, . . . , s.sub.N.sub.QL.sub.1}, where N.sub.QL=2.sup.N.sup.b is the number of complex quantization levels. Each symbol from the finite set of quantizer complex alphabet ={s.sub.0, s.sub.1, . . . , s.sub.N.sub.QL.sub.1}, can be represented as a sum of N.sub.mN.sub.b components, that are the result of the decomposition of quantization value s.sub.n,QT given by

[00006]$\begin{array}{c}{s}_{n,\mathrm{QT}}=g_0+g_1.Math.b_n^{\left(0\right)}+g_2.Math.b_n^{\left(1\right)}+g_3.Math.b_n^{\left(0\right)}.Math.b_n^{\left(1\right)}+g_4.Math.b_n^{\left(2\right)}+\mathrm{.Math.}\\ =\underset{i=0}{\overset{N_m-1}{.Math.}}.Math..Math.g_i.Math.\underset{m=0}{\overset{N_m-1}{.Math.}}.Math..Math.{\left(b_n^{\left(m\right)}\right)}^{{}_{m,i}}=\underset{i=0}{\overset{N_m-1}{.Math.}}.Math..Math.g_i.Math.b_n^{\mathrm{eq}\left(i\right)},\end{array}$

with (.sub.N.sub.m.sub.1,i .sub.N.sub.m.sub.2,i . . . .sub.1,i .sub.0,i) denoting the binary representation of i, b.sub.n.sup.(m)=(1).sup..sup.n.sup.(m) denoting the polar representation of the bit .sub.n.sup.(m), b.sub.n.sup.eq(i)=.sub.m=0.sup.N.sup.m.sup.1 (b.sub.n.sup.(m)).sup..sup.m,i denoting the i-th component of s.sub.n and N.sub.m is the number of non-zero g.sub.i complex coefficients of the referred decomposition equation (the total number of coefficients is 2.sup.N.sup.b1). For example, for N.sub.b=6 and a symmetrical DR (using as reference the zero value) the quantization levels are

[00007]$p.Math.\frac{\sqrt{2}}{2}.Math.\mathrm{jk}.Math.\frac{\sqrt{2}}{2}.Math.,$

with p=1, 3, 5, 7 and k=1, 3, 5, 7, which can be given by

s.sub.n,QT=g.sub.1b.sub.n.sup.(0)+g.sub.h2b.sub.n.sup.(1)+g.sub.4b.sub.n.sup.(2)+g.sub.8b.sub.n.sup.(3)+g.sub.16b.sub.n.sup.(4)+g.sub.32b.sub.n.sup.(5)=s.sub.1,2+s.sub.4,8 +s.sub.16,32

with

[00008]$g.Math..Math.1=\frac{\sqrt{2}}{2}.Math.,g.Math..Math.8=j.Math.\frac{\sqrt{2}}{2}.Math.,g.Math..Math.2=2.Math.\frac{\sqrt{2}}{2}.Math.,g.Math..Math.16=j.Math..Math.2.Math.\frac{\sqrt{2}}{2}.Math.,g.Math..Math.4=4.Math.\frac{\sqrt{2}}{2}.Math.,g.Math..Math.32=j.Math..Math.4.Math.\frac{\sqrt{2}}{2}.Math.$

and all the others gi zero valued and

[00009]$s_{1,2}=\frac{\sqrt{2}}{2}.Math.j.Math.\frac{\sqrt{2}}{2}.Math.,s_{4,8}=\frac{2.Math.\sqrt{2}}{2}.Math.j.Math.\frac{2.Math.\sqrt{2}}{2}.Math.,s_{16,32}=\frac{4.Math.\sqrt{2}}{2}.Math.j.Math.\frac{4.Math.\sqrt{2}}{2}.Math..$

Each one of the N.sub.m polar components with amplitude g.sub.i can be modulated as a bi-phase shift keying (BPSK) signal. Note that the pulse shape employed in each BPSK signal can be selected to achieve high spectral efficiency and constant envelope. For the i-th branch the peak amplitude of the corresponding BPSK signal is given by the corresponding |g.sub.i|. In the QDCA embodiment the in-phase and quadrature components are used to generate constituent signals with constant envelope that are individually amplified. In the QDCAC embodiment the in-phase and quadrature components whit same amplitude can be also combined to generate constituent signals with constant envelope that are individually amplified.

[0097] The operation of the QDCA and QDCAC embodiments shall be described further with reference to the flowchart of FIG. 1. Optional components are illustrated with dashed lines. The process starts at step 101, which includes receiving the signal to be amplified. In another embodiment this involves receiving the desired input RF signal. In another embodiment this involves receiving the desired intermediate frequency (IF) signal. In another embodiment this involves receiving the envelope samples of the desired input signal.

[0098] Step 102 includes receiving a clock signal set according to the signal frequency of the input signal.

[0099] Step 103 includes receiving a clock signal set according to a desired sample rate of the input signal. It is important to mention that as understood by a person skilled in the art the sample rate may vary according to the bandwidth of the input signal and the desired time resolution of the sampling process.

[0100] Step 104 includes receiving a clock signal in accordance with a desired output signal frequency of the desired output signal.

[0101] Step 105 includes sampling the input signal in accordance with the sampling rate to generate the samples of the input signal. In the embodiment example of FIG. 2, step 105 is implemented by a sampling circuit or a sample and hold (S/H) circuit.

[0102] Step 106 includes quantizing the samples to generate the quantization bits that correspond to the quantized symbol.

[0103] Step 107 includes processing individually the quantized bits to generate the corresponding polar representation of each quantization bit.

[0104] Step 108 includes processing the six polar signals to generate the corresponding constituent signals. It is important to note that in certain embodiments of the present invention steps 106, 107 and 108 can be done once by a block that quantizes and converts directly the samples into the constituent constant envelope signals. As understood by a person skilled in the art based on the teaching herein, the steps 106 to 108 can be performed by a block using a comparator and a LUT with the corresponding constituent signals for the quantized values.

[0105] Step 109A includes processing the outputs of the constituent complex mapper to generate the in-phase and quadrature components of each quantized sample.

[0106] Step 109B includes processing the in-phase and quadrature components of the quantized sample by summing in-phase and quadrature components with same amplitude to generate a set of constituent signals with quasi or constant envelope and a sum equal to the quantized sample of the signal.

[0107] Step 110A includes processing the quantized in-phase components of the constituent signals by multiplying the signals by a periodic pulse signal with the desired output signal frequency. The quantized in-phase constituent signals have quasi or constant envelopes and a sum equal to the in-phase component of the quantized sample of the input signal. Includes processing the quantized quadrature components of the constituent signals by multiplying the signals by a periodic pulse signal with the desired output signal frequency. The quantized quadrature constituent signals have quasi or constant envelopes and a sum equal to the quadrature component of the quantized sample of the input signal.

[0108] Step 110B includes processing the signals resulting from the combination of the quantized in-phase and quadrature components with same amplitude of step 109B, by multiplying the signals by a periodic pulse signal with the desired output signal frequency. The constituent signals have quasi or constant envelopes and a sum equal to the quantized sample of the input signal.

[0109] Step 111 includes individually amplifying each of one of the constituent signals, and summing the amplified signals to generate the desired output signal.

[0110] Block diagram 200A of FIG. 2A is an example that illustrates an exemplary embodiment of the QDCA embodiment implementing the process flowchart 100 of FIG. 1, but using the optional steps 109A and 110A. In the example of FIG. 2A, optional components are illustrated with dashed lines. In other embodiments, additional components may be optional. In this example a bandpass time varying envelope signal 201, a clock reference signal 202 for the sampling process and a channel clock 203, with the desired frequency for the output signal, are received as inputs. In another embodiment the signal 201 can be the samples of a time-varying envelope signal and the S/H 204 is not required. In another embodiments signal 201 can be a baseband signal, or IF signal.

[0111] The clock reference signal 202 can be used by the S/H block 204, by the quantizer 207 and by the polar converter block 214. It can be understood by a person skilled in the art that the choice of the clock reference signal is made according the bandwidth of the input signal and the desired output signal.

[0112] The S/H circuit 204 samples the received signal according to a clock signal 202 and releases these values 205 to the quantizer 206. Still referring to FIG. 2, the samples 205 are converted by the 6 bit quantizer 207 into 6 bits signals 208, 209, 210, 211, 212, and 213. The signals 208, 209, 210, 211, 212, and 213 are provided to a polar converter 214 that generates the signals 215, 216, 217, 218, 219 and 220 that are the polar versions of the bits signals 208, 209, 210, 211, 212, and 213. It is noted that one 6 bit quantizer and 6 amplification branches are employed in this embodiment only for purposes of illustration, and not limitation. The scope of the invention covers use of other numbers of branches, and implementation of such variations will be apparent to persons skilled in the art based on the teachings contained herein.

[0113] The polar signals 215, 216, 217, 218, 219 and 220 are provided to the constituent signal mapper 221 that generates the in-phase constituent signals components 222, 223 and 224 that correspond to the real part of the complex symbol signals s.sub.1,2, s.sub.4,8, s.sub.16,32 and generates the quadrature constituent signals components 225, 226 and 227 that correspond to imaginary part of the complex symbol signals s.sub.1,2, s.sub.4,8, s.sub.16,32, respectively. The signal mapper also generates for each constituent signal component a pulse shape to assure good spectral efficiency and power efficiency.

[0114] In an embodiment a common clock signal 202 is used to ensure that the outputs of S/H 205, the outputs of quantizer 207 and the outputs of the polar converter 214 are time aligned.

[0115] In-phase constituent signals 231, 232 and 233 are obtained by multiplying in 229-1, 229-2 and 229-3 the signals 222, 223 and 224 by a pulse periodic signal 228 with the desired frequency for the output signal generated by 206. Quadrature constituent components signals 234, 235 and 236 are obtained by multiplying in 229-4, 229-5 and 229-6 the signals 225, 226 and 227 by a pulse periodic signal 228 with the desired frequency for the output signal generated by 206. Constituent signals 231, 232, 233, 234, 235 and 236 with quasi or constant envelope are the inputs of the corresponding power amplifiers (PAs) 237-{1, . . . , 6} of the amplification stage that may be non-linear power amplifiers. In another embodiment PAs 237-{1, . . . , 6} include switching power amplifiers of class D. In another embodiment PAs 237-{1, . . . , 6} include switching power amplifiers of class E, class F and sigma delta class S.

[0116] The outputs of PAs 238, 239, 240, 241, 242 and 243 are coupled together in a combiner 244 using well known combining techniques such as active combiners or other techniques such as Wilkison, hybrid or transformers. Alternatively, the outputs of PAs 237-{1, . . . , 6} can be coupled through LC matching for a minimal power loss. Amplification stage embodiments according to power amplification methods and systems of the present invention will further described in section 3.1.

[0117] The combiner's output signal 245 is submitted to a bandpass filter 246 with central frequency equal to the desired frequency of the output signal 247.

[0118] In another embodiment a bias circuit 249 can be employed to provide bias signals 249-{1, . . . , 6} to the PAs. In another embodiment a phase control circuit 250 could be employed to generate control signals 251-{1, . . . , 6} to compensate any phase shifts among amplifiers.

[0119] Block diagram 200B of FIG. 2B is an example that illustrates an embodiment of the QDCAC implementing the process flowchart 100 of FIG. 1 and using the optional steps 109B and 110B. In the example of FIG. 2B, optional components are illustrated with dashed lines. In other embodiments, additional components may be optional.

[0120] In this example a bandpass time varying envelope signal 201, a clock reference signal 202 for the sampling process and a channel clock 203 with the desired frequency for the output signal are received as inputs. In another embodiment the signal 201 can be the samples of a time-varying envelope signal and the S/H 204 is not required. In another embodiments signal 201 can be a baseband signal, or IF signal.

[0121] The clock reference signal 202 can be used by the S/H block 204, by the quantizer 207 and by the polar converter block 214. It can be understood by a person skilled in the art that the choice of the clock reference signal is made according the bandwidth of the input signal and the desired output signal.

[0122] The S/H circuit 204 samples the received signal according to a clock signal 202 and releases these values 205 to the quantizer 206. Still referring to FIG. 2, the samples 205 are converted by the 6 bit quantizer 207 into 6 bits signals 208, 209, 210, 211, 212, and 213. The signals 208, 209, 210, 211, 212, and 213 are provided to a polar converter 214 that generates the signals 215, 216, 217, 218, 219 and 220 that are the polar versions of the bits signals 208, 209, 210, 211, 212, and 213. It is noted that one 6 bit quantizer and 3 amplification branches are employed in this embodiment only for purposes of illustration, and not limitation. The scope of the invention covers use of other numbers of branches, and implementation of such variations will be apparent to persons skilled in the art based on the teachings contained herein.

[0123] The polar signals 215, 216, 217, 218, 219 and 220 are provided to the constituent signal mapper 221 that generates the in-phase constituent signals components 222, 223 and 224 that correspond to the real part of the complex symbol signals s.sub.1,2, s.sub.4,8, s.sub.16,32 and generates the quadrature constituent signals components 225, 226 and 227 that correspond to imaginary part of the complex symbol signals s.sub.1,2, s.sub.4,8, s.sub.16,32, respectively. The signal mapper also generates for each constituent signal a pulse shape to assure good spectral efficiency and power efficiency.

[0124] In an embodiment a common clock signal 202 is used to ensure that the outputs of S/H 205, the outputs of quantizer 207 and the outputs of the polar converter 214 are time aligned.

[0125] The in-phase constituent signals 230, 231 and 232 are obtained by multiplying in 229-1, 229-2 and 229-3 the signals 222, 223 and 224 by a pulse periodic signal 228 with the desired frequency for the output signal generated by 206. The quadrature constituent signals 233, 234 and 235 are obtained by multiplying in 229-4, 229-5 and 229-6 the signals 225, 226 and 227 by a pulse periodic signal 228 with the desired frequency for the output signal generated by 206.

[0126] In-phase constituent signals 230, 231 and 232 are summed in 236-1, 236-2 and 236-3 with the quadrature constituent signals 233, 234 and 235 with the same amplitude, i. e. each in-phase component is combined with the corresponding quadrature component with the same amplitude to generate the constituent complex signals 237, 238 and 239. Constituent signals 237, 238 and 239 have quasi or constant envelope and are the inputs of the corresponding power amplifiers (PAs) 240-{1, . . . , 3} of the amplification stage that may be non-linear power amplifiers. In another embodiment PAs 240-{1, . . . , 3} include switching power amplifiers of class D. In another embodiment PAs 240-{1, . . . , 3} include switching power amplifiers of class E, class F and sigma delta class S.

[0127] The outputs of PAs 241, 242 and 243 are coupled together in a combiner 244 using well known combining techniques such as active combiners or other techniques such as Wilkison, hybrid or transformers. Alternatively, the outputs of PAs 241, 242 and 243 can be coupled through LC matching for a minimal power loss. Amplification stage embodiments according to power amplification methods and systems of the present invention will further described in section 3.1.

[0128] The output signal 245 is submitted to a bandpass filter 246 with central frequency equal to the desired frequency of the output signal 247.

[0129] In another embodiment a bias circuit 248 can be employed to provide bias signals 249-{1, . . . , 3} to the PAs. In another embodiment a phase control circuit 250 could be employed to generate control signals 251-{1, . . . , 3} to compensate any phase shifts among amplifiers.

[0130] In other embodiment voltage-to-current or current-to-voltage converters 252-{1, . . . , 6} may be employed before the sum of the in-phase and quadrature constituent signals with same amplitude performed in 236-{1, . . . , 3}. It is important to mention that as understood by a person skilled in the art that the voltage-to-current or current-to-voltage converters 252-{1, . . . , 6} may be embedded in the sum operations 236-{1, . . . , 3} or in the multiplications performed in 229-{1, . . . , 6}.

2.2 I/Q Quantized Digital Controlled Amplification (IQQDCA)

[0131] According to one embodiment of the invention, herein called the I/Q quantized Digital controlled amplification (IQQDCA), for ease of illustration and not limitation, a time-varying envelope signal is decomposed into 6quasi or constant envelope constituent signals and DRi=DRq. The constituent signals are amplified individually, and then summed to construct an amplified version of the original time-varying complex envelope signal. It is noted that 6 amplification branches are employed in these embodiments for purposes of illustration, and not limitation. The scope of the invention covers use of other numbers of branches, and DRi=DRq and DRiDRq and implementation of such variations will be apparent to persons skilled in the art based on the teachings contained herein.

[0132] According to another embodiment of the invention, herein called the IQQDCA with complex components (IQQDCAC), for ease of illustration and not limitation, a time-varying envelope signal is decomposed into 3 quasi or constant envelope complex constituent signals and DRi=DRq. The constituent signals are amplified individually, and then summed to construct an amplified version of the original time-varying complex envelope signal. It is noted that 3 amplification branches are employed in these embodiments for purposes of illustration, and not limitation. The scope of the invention covers use of other numbers of branches, and DRi=DRq and DRiDRq and implementation of such variations will be apparent to persons skilled in the art based on the teachings contained herein.

[0133] According to IQQDCA and IQQDCA embodiments the time domain sample of the complex envelope in-phase component s.sub.nI can be transformed into a quantized symbol s.sub.nI,QT taken from a finite alphabet of 2.sup.N.sup.b possible quantization symbols. Also, time domain sample of the complex envelope quadrature component s.sub.nQ can be transformed into a quantized symbol s.sub.nQ,QT taken from a finite alphabet of 2.sup.N.sup.b possible quantization symbols. The N.sub.b quantization bits and N.sub.QL=2.sup.N.sup.b quantization levels applied in each component can be defined in terms of the maximum quantization errors

[00010]${\mathrm{.Math.}}_{\mathrm{Qi}}=\frac{\mathrm{DRi}}{22^{N_b}}=\frac{2.Math..Math..Math.i}{2}.Math..Math.\mathrm{and}.Math..Math.{\mathrm{.Math.}}_{\mathrm{Qq}}=\frac{\mathrm{DRq}}{22^{N_b}}=\frac{2.Math..Math..Math.q}{2}$

where 2i and 2q represent the quantization interval for the in-phase component and the quantization interval for the quadrature component, respectively. For each component N.sub.b quantization bits (.sub.nI.sup.(N.sup.b.sup.1), .sub.nI.sup.(N.sup.b.sup.2), . . . , .sub.nI.sup.(1), .sub.nI.sup.(0)) and (.sub.nq.sup.(N.sup.b.sup.1), .sub.nq.sup.(N.sup.b.sup.2), . . . , .sub.nq.sup.(1), .sub.nq.sup.(0)) are employed in the definition of N.sub.mN.sub.b polar components in which each quantization level can be decomposed. Both sets of bits (.sub.nI.sup.(N.sup.b.sup.1), .sub.nI.sup.(N.sup.b.sup.2), . . . , .sub.nI.sup.(1), .sub.nI.sup.(0)) and (.sub.nq.sup.(N.sup.b.sup.1), .sub.nq.sup.(N.sup.b.sup.2), . . . , .sub.nq.sup.(1), .sub.nq.sup.(0)) are converted into polar forms (b.sub.nI.sup.(N.sup.b.sup.1), b.sub.nI.sup.(N.sup.b.sup.2), . . . , b.sub.nI.sup.(1), b.sub.nI.sup.(0)) by b.sub.nI.sup.(m)=(1).sup..sup.nI.sup.(m) and b.sub.nq.sup.(m)=(1).sup..sup.nq.sup.(m).

[0134] Each in-phase symbol from the finite set of quantizer symbols ={s.sub.I,0, s.sub.I,1, . . . , s.sub.I,N.sub.QL.sub.1}, can be represented as a sum of N.sub.mIN.sub.b polar components that are the result of the decomposition of quantization value s.sub.nI,QT into polar components given by

[00011]$\begin{array}{c}{s}_{\mathrm{nI},\mathrm{QT}}=g_0+g_1.Math.b_{\mathrm{nI}}^{\left(0\right)}+g_2.Math.b_{\mathrm{nI}}^{\left(1\right)}+g_3.Math.b_{\mathrm{nI}}^{\left(0\right)}.Math.b_{\mathrm{nI}}^{\left(1\right)}+g_4.Math.b_{\mathrm{nI}}^{\left(2\right)}+\mathrm{.Math.}\\ =\underset{i=0}{\overset{N_{\mathrm{mI}}-1}{.Math.}}.Math..Math.g_i.Math.\underset{m=0}{\overset{N_{\mathrm{mI}}-1}{.Math.}}.Math..Math.{\left(b_{\mathrm{nI}}^{\left(m\right)}\right)}^{{}_{m,i}}=\underset{i=0}{\overset{N_{\mathrm{mI}}-1}{.Math.}}.Math..Math.g_i.Math.b_{\mathrm{nI}}^{\mathrm{eq}\left(i\right)},\end{array}$

with (.sub.N.sub.mI.sub.1,i .sub.N.sub.mI.sub.2,i . . . .sub.1,i .sub.0,i) denosting the binary representation of i, b.sub.nI.sup.eq(i)=.sub.m=0.sup.N.sup.mI.sup.1 (b.sub.nI.sup.(m)).sup..sup.m,i denoting the i'th polar component of s.sub.nI,QT and N.sub.mI is the number of non-null g.sub.i real coefficients of the referred decomposition (the total number of coefficients is 2.sup.N.sup.b1). For example, for N.sub.b=3 and a symmetrical dynamic range DRi (using as reference the zero value) the quantization levels are 7, 5, 3, , which can be given by

s.sub.nI,QT=g.sub.1b.sub.nI.sup.(0)+g.sub.2b.sub.nI.sup.(1)+g.sub.4b.sub.nI.sup.(2)=s.sub.1I+s.sub.2I+s.sub.4I,

with g1=, g2=2, g4=4 and g0=g3=g5=g6=g7=0 and

[00012]$s_{1.Math.I}=\frac{\sqrt{2}}{2}.Math.,s_{2.Math.I}=\frac{2.Math.\sqrt{2}}{2}.Math.,s_{4.Math.I}=\frac{4.Math.\sqrt{2}}{2}.Math..$

[0135] For the quadrature component each quadrature symbol from the finite set of quantizer symbols Q={s.sub.q,0, s.sub.q,1, . . . , q.sub.q,N.sub.QL.sub.1}, can be represented as a sum of N.sub.mQN.sub.b solar components, that are the result of the decomposition of quantization value s.sub.nq,QT into polar components given by

[00013]$\begin{array}{c}{s}_{\mathrm{nq},\mathrm{QT}}=g_0+g_1.Math.b_{\mathrm{nq}}^{\left(0\right)}+g_2.Math.b_{\mathrm{nq}}^{\left(1\right)}+g_3.Math.b_{\mathrm{nq}}^{\left(0\right)}.Math.b_{\mathrm{nq}}^{\left(1\right)}+g_4.Math.b_{\mathrm{nq}}^{\left(2\right)}+\mathrm{.Math.}\\ =\underset{i=0}{\overset{N_{\mathrm{mQ}}-1}{.Math.}}.Math..Math.g_i.Math.\underset{m=0}{\overset{N_{\mathrm{mQ}}-1}{.Math.}}.Math..Math.{\left(b_{\mathrm{nq}}^{\left(m\right)}\right)}^{{}_{m,i}}=\underset{i=0}{\overset{N_{\mathrm{mQ}}-1}{.Math.}}.Math..Math.g_i.Math.b_{\mathrm{nq}}^{\mathrm{eq}\left(i\right)},\end{array}$

with (.sub.N.sub.mQ.sub.1,i .sub.N.sub.mQ.sub.2,i . . . .sub.1,i .sub.0,i) denoting the binary representation of i, b.sub.nq.sup.eq(i)=.sub.m=0.sup.N.sup.mQ.sup.1 (b.sub.nq.sup.(m)).sup..sup.m,i denoting the i-th polar component of s.sub.nQ,QT and N.sub.mQ is the number of non-zero g.sub.i imaginary coefficients of the referred decomposition (the total number of coefficients is 2.sup.N.sup.b1). For example, for N.sub.b=3 and a symmetrical dynamic range (using as reference the zero value) the quantization levels are j7, j5, j3, j, which can be given by

s.sub.nq,QT=g.sub.1b.sub.nq.sup.(0)+g.sub.2b.sub.nq.sup.(1)+g.sub.4b.sub.nq.sup.(2),

with g1=j, g2=j, g4=j4 and g0=g3=g5=g6=g7=0 and

[00014]$s_{1.Math.Q}=j.Math.\frac{\sqrt{2}}{2}.Math.,s_{2.Math.Q}=j.Math.\frac{2.Math.\sqrt{2}}{2}.Math.,s_{4.Math.Q}=j.Math.\frac{4.Math.\sqrt{2}}{2}.Math..$

[0136] For the i-th branch the peak amplitude of the corresponding signal is given by the corresponding |g.sub.i|. Each one of the N.sub.m polar components with amplitude g.sub.i can be modulated as a BPSK signal. Note that the pulse shape employed in each BPSK signal can be selected to achieve high spectral efficiency and constant envelope. For the i-th branch the peak amplitude of the corresponding BPSK signal is given by the corresponding |g.sub.i|. In the IQQDCA embodiment the in-phase and quadrature components are used to generate constituent signals with quasi constant or constant envelope that are indvidualy amplified. In the IQQDCAC embodiment the in-phase and quadrature components whit same amplitude are combined to generate constituent signals with quasi constant or constant envelope that are indvidualy amplified.

[0137] Operation of the IQQDCA and IQQDCAC embodiments shall be described further with reference to the flowchart of FIG. 3. Optional steps are illustrated with dashed lines. The process starts at step 301, which includes receiving a time varying envelope bandpass signal. In another embodiment this involves receiving the desired input RF signal. In another embodiment this involves receiving the desired IF signal. In another embodiment this involves receiving a baseband signal. In another embodiment this involves receiving the samples of the time varying envelope signal or receiving the samples the in-phase and quadrature components of a time varying envelope signal.

[0138] Step 302 includes receiving a clock signal set according to the signal frequency of the input signal.

[0139] Step 303 includes receiving a clock signal set according to a desired sample rate of the input signal. It is important to mention that as understood by a person skilled in the art the sample rate may vary according to the bandwidth of the input signal and the desired time resolution of the sampling process.

[0140] Step 304 includes receiving a clock signal in accordance with a desired output signal frequency of the desired output signal.

[0141] Step 305 includes processing the signal to generate in-phase and quadrature components.

[0142] Step 306 includes sampling the in-phase and quadrature components of the input signal in accordance with the sampling rate to generate the corresponding samples.

[0143] Step 307 includes processing individually by a quantizer the in-phase and quadrature components to generate the quantization bits that correspond to the quantized value of the in-phase and the quantization bits that correspond to the quantized value of the quadrature component, respectively. As understood by a person skilled in the art based on the teaching herein, step 307 can be performed by a block using a single quantizer. Also, as understood by a person skilled in the art based on the teaching herein, step 307 can be performed by a comparator and a LUT with the corresponding quantization bits of the quantized values.

[0144] Step 308 includes processing individually the quantization bits of the quantized in-phase component to generate the corresponding polar representation of each quantization bit and processing individually the quantization bits of the quantized quadrature component to generate the corresponding polar representation of each quantization bit.

[0145] Step 309 includes processing individually in a mapper the polar signals associated to the quantized in-phase component to map them into the corresponding constituent signals and processing individually the polar signals associated to the quantized quadrature component to map them into the corresponding constituent signals. It is important to note that in certain embodiments of the present invention steps 307, 308 and 309 can be done once by a block that quantizes and generates directly the constituent signals.

[0146] Step 310A includes processing the quantized in-phase components of the constituent signals by multiplying the signals by a periodic pulse signal with the desired output signal frequency. The quantized in-phase constituent signals have quasi or constant envelopes and a sum equal to the in-phase component of the quantized sample of the input signal. This step also includes also processing the quantized quadrature components of the constituent signals by multiplying the signals by a periodic pulse signal with the desired output signal frequency. The quantized quadrature constituent signals have quasi or constant envelopes and a sum equal to the quadrature component of the quantized sample of the input signal.

[0147] Step 310B includes processing the quantized in-phase components and the quantized quadrature components of the constituent signals by multiplying the signals by a periodic pulse signal with the desired output signal frequency. After the multiplication the resulting in-phase constituent signals are summed with the corresponding resulting quadrature constituent components with the same amplitude to generate a set of complex constituent signals with quasi or constant envelopes and a sum equal to the quantized version of the input signal.

[0148] Step 311 includes individually amplifying each of one of the constituent signals, and summing the amplified signals to generate the desired output signal.

[0149] Block diagram 400A of FIG. 4A is an example that illustrates an embodiment of the IQQDCA, implementing the process flowchart 300 of FIG. 3, but using optional step 310A. In the example of FIG. 4A, optional components are illustrated with dashed lines. In other embodiments, additional components may be optional.

[0150] In this example a time varying envelope signal 401, a clock reference signal 402 for the sampling process and a channel clock 403 with the desired frequency for the output signal are received as inputs. In another embodiment 401 can be the samples of a time-variant envelope signal and the S/H 407 is not required. In another embodiment the input signal 401 can be the samples of the in-phase and quadrature components of a time varying envelope signal and the phase splitter 404 and the S/H are not required.

[0151] The clock reference signal 402 can be used by the S/H block 407, by the two quantizers 410 and 411 and by the polar converters 418 and 419. It can be understood by a person skilled in the art that the choice of the clock reference signal is made according the bandwidth of the input signal and the desired output signal. As understood by a person skilled in the art other reference clock signals and different reference clock signals may be used by the different blocks. It is noted that two 3 bit quantizers and 6 amplification branches are employed in this embodiment only for purposes of illustration, and not limitation. The scope of the invention covers the use of other numbers of branches, and implementation of such variations will be apparent to persons skilled in the art based on the teachings contained herein. It is also important to note that in certain embodiments of the present invention the quantizers employed to quantize the values of the samples of the in-phase and quadrature components may have different number of quantization levels and quantization bits.

[0152] The input signal 401 is submitted to the phase splitter 404 that generates the in-phase component 405A and quadrature component 4058 and releases them to the S/H 407. The S/H circuit 407 samples the in-phase 405A and the quadrature component 4058 of the received signal according to a clock signal 402 and generates the in-phase samples 408 and quadrature samples 409. The sample of the in-phase component 408 is submitted to a 3 bit quantizer 410 that generates 3 bit signals 412, 413, and 414, an end of conversion signal 412A to be used as control signal in the constituent signal mapper 420 and a polar signal representing the sign of the sample value 412b. The sample of the quadrature component 409 is submitted to a 3 bit quantizer 410 that generates 3 bit signals 415, 416, and 417, an end of conversion signal 415A to be used as control signal in the constituent signal mapper 421 and a polar signal representing the sign of the sample 415b. Signals 412, 413, 414 and signals 415, 416, and 417 are provided to bit polar converters 418 and 419, that generate the signals 428, 429 and 430 and the signals 431, 432 and 433 that are the polar versions of the signals 412, 413, 414 and signals 415, 416, and 417, respectively. In other embodiment signals 412, 413, 414 and signals 415, 416, and 417 may be provided to the constituent signal mappers.

[0153] The signals of the in-phase component 412, 413 and 414 are provided to the in-phase constituent signal mapper 420 that generates the signals 422, 423 and 424 with amplitudes that correspond to the coefficients associated to each bit. Amplitudes of 422, 423 and 424 correspond to the coefficients g1, g2 and g4. The signals 422, 423 and 424 are multiplied by the corresponding polar signals 428, 429, and 430 to generate the in-phase constituent components 441, 442 and 443 that correspond to the signals s.sub.1I, s.sub.2I and s.sub.4I, associated to the decomposition of the in-phase component of the quantized value. In another embodiment the signals 422, 423 and 424 are multiplied in 435, 436 and 437 by the corresponding polar signals 428, 429, 430 and the polar signal 412b to generate the in-phase constituent components 441, 442 and 443 that correspond to the signals s.sub.1I, s.sub.2I and s.sub.4I, associated to the decomposition of the in-phase component of the quantized value.

[0154] The signals of the quadrature component 415, 416, and 417 are provided to the quadrature constituent signal mapper 421 that generates the signals 425, 426 and 427 with amplitudes that correspond to the coefficients associated to each bit. Amplitudes of 425, 426 and 427 correspond to the coefficients g1, g2 and g4 related with the decomposition of the quadrature value into constituent signals. The signals 425, 426 and 427 are multiplied by the polar signals 431, 432, and 433 to generate the quadrature constituent components 444, 445 and 446 that correspond to the signals s.sub.1Q, s.sub.2Q and s.sub.4Q, associated to the decomposition of the quadrature component of the quantized value. In another embodiment the signals 425, 426 and 427 are multiplied in 438, 439 and 440 by the polar signals 431, 432, 433 and the polar signal 415b to generate the quadrature constituent components 444, 445 and 446 that correspond to the signals s.sub.1Q, s.sub.2Q and s.sub.4Q, associated to the decomposition of the quadrature component of the quantized value. Each signal mapper also generates for each constituent signal a pulse shape to assure good spectral efficiency and power efficiency.

[0155] In-phase constituent signals 448, 449 and 450 are obtained by multiplying in 447-1, 447-2 and 447-3 the signals 441, 442 and 443 by a periodic pulse signal 434 with the desired frequency for the output signal generated by 406. Quadrature constituent signals 451, 452 and 453 are obtained by multiplying in 447-4, 447-5 and 447-6 the signals 444, 445 and 446 by a periodic pulse signal 434 with the desired frequency for the output signal generated by 406.

[0156] In other embodiments the signal 434 can be a sinusoidal signal or a pulse train signal with frequency selected according to the desired frequency of the output signal.

[0157] The set of constituent signals 448, 449, 450, 451, 452 and 453 with quasi and/or constant envelope are the inputs of the corresponding PAs 454-{1, . . . , 6} of the amplification stage, that may be non-linear power amplifiers. In another embodiment PAs 454-{1, . . . , 6} include switching power amplifiers of class D. In another embodiment PAs 454-{1, . . . , 6} include switching power amplifiers of class E. In another embodiment PAs 454-{1, . . . , 6} include switching power amplifiers of class F or class S. In other embodiment PAs 454-{1, . . . , 6} may include power amplifiers of class A, B, AB or C.

[0158] The outputs of PAs 455, 456, 457, 458, 459 and 460 are coupled together in a combiner 461 using well known combining techniques such as active combiners or other techniques such as Wilkison, hybrid or transformers. Alternatively, the outputs of PAs 455, 456, 457, 458, 459 and 460 can be coupled through inductances and/or capacitances for a minimal power loss. Amplification stage embodiments according to power amplification methods and systems of the present invention will further described in section 3.1.

[0159] The combiner's output signal 462 is submitted to a bandpass filter 463 with central frequency equal to the desired frequency of the output signal, being the signal 464 the desired amplified signal.

[0160] In another embodiment a bias circuit 465 can be employed to provide bias signals 466-{1, . . . , 6} to the PAs. In another embodiment a phase control circuit 467 could be also employed to provide control signals 468-{1, . . . , 6} to compensate any phase shifts among amplifiers.

[0161] Block diagram 400B of FIG. 4B is an example that illustrates an exemplary embodiment of the IQQDCA, implementing the process flowchart 300 of FIG. 3 using optional step 310B. In the example of FIG. 4B, optional components are illustrated with dashed lines. In other embodiments, additional components may be optional.

[0162] In this example a time varying envelope signal 401, a clock reference signal 402 for the sampling process and a channel clock 403 with the desired frequency for the output signal are received as inputs. In another embodiment 401 can be the samples of a time-variant envelope signal and the S/H 407 is not required. In another embodiment the input signal 401 can be the samples of the in-phase and quadrature components of a time varying envelope signal and the phase splitter 404 and the S/H are not required.

[0163] The clock reference signal 402 can be used by the S/H block 407, by the two quantizers 410 and 411 and by the polar converters 418 and 419. It can be understood by a person skilled in the art that the choice of the clock reference signal is made according the bandwidth of the input signal and the desired output signal. As understood by a person skilled in the art other reference clock signals and different reference clock signals may be used by the different blocks. It is noted that two 3 bit quantizers and 3 amplification branches are employed in this embodiment for purposes of illustration, and not limitation. The scope of the invention covers the use of other numbers of branches, and implementation of such variations will be apparent to persons skilled in the art based on the teachings contained herein. It is also important to note that in certain embodiments of the present invention the quantizers employed to quantize the values of the samples of the in-phase and quadrature components may have different number of quantization levels and quantization bits.

[0164] The input signal 401 is submitted to the phase splitter 404 that generates the in-phase component 405A and quadrature component 4058 and releases them to the S/H 407. The S/H circuit 407 samples the in-phase 405A and the quadrature component 4058 of the received signal according to a clock signal 402 and generates the in-phase samples 408 and quadrature samples 409. The sample of the in-phase component 408 is submitted to a 3 bit quantizer 410 that generates 3 bit signals 412, 413, and 414, an end of conversion signal 412A to be used as control signal in the constituent signal mapper 420 and a polar signal representing the sign of the sample value 412b. The sample of the quadrature component 409 is submitted to a 3 bit quantizer 410 that generates 3 bit signals 415, 416, and 417, an end of conversion signal 415A to be used as control signal in the constituent signal mapper 421 and a polar signal representing the sign of the sample 415b. Signals 412, 413, 414 and signals 415, 416, and 417 are provided to bit polar converters 418 and 419, that generate the signals 428, 429 and 430 and the signals 431, 432 and 433 that are the polar versions of the signals 412, 413, 414 and signals 415, 416, and 417, respectively. In other embodiment signals 412, 413, 414 and signals 415, 416, and 417 may be provided to the constituent signal mappers.

[0165] The signals of the in-phase component 412, 413, and 414 are provided to the in-phase constituent signal mapper 420 that generates the signals 422, 423 and 424 with amplitudes that correspond to the coefficients associated to each bit. Amplitudes of 422, 423 and 424 correspond to the coefficients g1, g2 and g4. The signals 422, 423 and 424 are multiplied by the corresponding polar signals 428, 429, and 430 to generate the in-phase constituent components 441, 442 and 443 that correspond to the signals s.sub.1I, s.sub.2I and s.sub.4I, associated to the decomposition of the in-phase component of the quantized value. In another embodiment the signals 422, 423 and 424 are multiplied in 435, 436 and 437 by the corresponding polar signals 428, 429, 430 and the polar signal 412b to generate the in-phase constituent components 441, 442 and 443 that correspond to the signals s.sub.1I, s.sub.2I and s.sub.4I, associated to the decomposition of the in-phase component of the quantized value. The signal mapper also generates for each constituent signal a pulse shape to assure good spectral efficiency and power efficiency.

[0166] The signals of the quadrature component 415, 416, and 417 are provided to the quadrature constituent signal mapper 421 that generates the signals 425, 426 and 427 with amplitudes that correspond to the coefficients associated to each bit. Amplitudes of 425, 426 and 427 correspond to the coefficients g1, g2 and g4 related with the decomposition of the quadrature value into constituent signals. The signals 425, 426 and 427 are multiplied by the polar signals 431, 432, and 433 to generate the quadrature constituent components 444, 445 and 446 that correspond to the signals s.sub.1Q, s.sub.2Q and s.sub.4Q, associated to the decomposition of the quadrature component of the quantized value. In another embodiment the signals 425, 426 and 427 are multiplied in 438, 439 and 440 by the polar signals 431, 432, 433 and the polar signal 415b to generate the quadrature constituent components 444, 445 and 446 that correspond to the signals s.sub.1Q, s.sub.2Q and s.sub.4Q, associated to the decomposition of the quadrature component of the quantized value. In-phase constituent signals 448, 449 and 450 are obtained by multiplying in 447-1, 447-2 and 447-3 the signals 441, 442 and 443 by a periodic pulse signal 434 with the desired frequency for the output signal generated by 406. Quadrature constituent signals 451, 452 and 453 are obtained by multiplying in 447-4, 447-5 and 447-6 the signals 444, 445 and 446 by a periodic pulse signal 434 with the desired frequency for the output signal generated by 406.

[0167] In other embodiments the signal 434 can be a sinusoidal signal or a pulse train signal with frequency selected according to the desired frequency of the output signal.

[0168] In 454-1, 454-2 and 454-3 each in-phase constituent signal 448, 449 and 450 is summed with the corresponding quadrature constituent signal 451, 452 and 453 with the same amplitude, i. e. each in-phase component is combined with the corresponding quadrature component with the same amplitude to generate the constituent complex signals 455, 456 and 457. Constituent signals 455, 456 and 457 have quasi or constant envelope are the inputs of the corresponding PAs 458-{1, . . . , 3} of the amplification stage that may be non-linear power amplifiers.

[0169] In another embodiment PAs 458-{1, . . . , 3} include switching power amplifiers of class D. In another embodiment PAs 458-{1, . . . , 3} include switching power amplifiers of class E. In another embodiment PAs 458-{1, . . . , 3} include switching power amplifiers of class F or class S. In other embodiment PAs 458-{1, . . . , 3} may include power amplifiers of class A, B, AB or C.

[0170] The outputs of PAs 459, 460 and 461 are coupled together in a combiner 462 using well known combining techniques such as active combiners or other techniques such as Wilkison, hybrid or transformers. Alternatively, the outputs of PAs 459, 460 and 461 can be coupled through inductances and/or capacitances for a minimal power loss. Amplification stage embodiments according to power amplification methods and systems of the present invention will further described in section 3.1.

[0171] The combiner's output signal 463 is submitted to a bandpass filter 464 with central frequency equal to the desired frequency of the output signal, being the signal 465 the desired amplified signal.

[0172] In another embodiment a bias circuit 466 can be employed to provide bias signals 467-{1, . . . , 3} to the PAs. In another embodiment a phase control circuit 468 could be also employed to provide control signals 469-{1, . . . , 3} to compensate any phase shifts among amplifiers.

[0173] In other embodiment voltage-to-current or current-to-voltage converters 470-{1, . . . , 6} may be employed before the sum of the in-phase and quadrature constituent signals with same amplitude performed in 454-{1, . . . , 3}. It is important to mention that as understood by a person skilled in the art that the voltage-to-current or the current-to-voltage converters 470-{1, . . . , 6} may be embedded in the sum operations or in the multiplications performed in 447-{1, . . . , 6}.

2.3 On/Off Quantized Digital Controlled Amplification (OOQDCA)

[0174] According to one embodiment of the invention, herein called On/Off quantized digital controlled amplification (OOQDCA), for ease of illustration and not limitation, a time-varying envelope signal is decomposed into 6 substantially constant envelope constituent signals that may be active or inactive. The in-phase and quadrature constituent signals are amplified individually, and then summed to construct an amplified version of the original time-varying envelope signal.

[0175] According to another embodiment of the invention, herein called OOQDCA with complex components (OOQDCAC), for ease of illustration and not limitation, a time-varying envelope signal is decomposed into 6 substantially constant envelope constituent signals that may be active or inactive. The active in-phase and quadrature components with same amplitude are summed to generate complex constituent signals that are amplified individually, and then summed to construct an amplified version of the original time-varying envelope signal.

[0176] It is noted that 6 amplification or 3 amplification branches are employed in these embodiments, it is also assumed DRi=DRq and the same number of quantization bits for in-phase and quadrature components for purposes of illustration, and not limitation. The scope of the invention covers the use of other numbers of branches, DRDRq and different number of quantization bits for the in-phase and quadrature components and implementation of such variations will be apparent to persons skilled in the art based on the teachings contained herein.

[0177] According to the OOQDCA and OOQDCAC embodiments the time domain sample of the complex envelope in-phase component s.sub.nI can be transformed into a quantized symbol s.sub.nI,QT taken from a finite alphabet of 2.sup.N.sup.b possible quantization symbols that are represented as a sum of unipolar components. Also, the time domain sample of the complex envelope quadrature component s.sub.nQ can be transformed into a quantized symbol s.sub.nQ,QT taken from a finite alphabet of 2.sup.N.sup.b possible quantization symbols that are decomposed as a sum of unipolar components. For the quantization of each component are employed N.sub.b+1 bits, where one bit is a polarity bit and the N.sub.b quantization bits and N.sub.QL=2.sup.N.sup.b quantization levels applied in each component are defined in terms of the maximum quantization errors

[00015]${\mathrm{.Math.}}_{\mathrm{Qi}}=\frac{\mathrm{DRi}}{22^{N_b}}=\frac{.Math..Math.i}{2}.Math..Math.\mathrm{and}.Math..Math.{\mathrm{.Math.}}_{\mathrm{Qq}}=\frac{\mathrm{DRq}}{22^{N_b}}=\frac{.Math..Math.q}{2}$

with i and q denoting the quantization interval for the in-phase component and the quantization interval for the quadrature component, respectively. Additional bits .sub.nI.sup.(N.sup.b.sup.) and .sub.nq.sup.(N.sup.b.sup.) are used to indicate the polarity of the quantized value. For each component N.sub.b quantization bits (.sub.nI.sup.(N.sup.b.sup.1), .sub.nI.sup.(N.sup.b.sup.2), . . . , .sub.nI.sup.(1), .sub.nI.sup.(0)) and (.sub.nq.sup.(N.sup.b.sup.1), .sub.nq.sup.(N.sup.b.sup.2), . . . , .sub.nq.sup.(1), .sub.nq.sup.(0)) are employed in the definition of N.sub.mN.sub.b unipolar components in which each quantization level can be decomposed. Both polarity bits .sub.nI.sup.(N.sup.b.sup.) and .sub.nq.sup.(N.sup.b.sup.) are converted into polar forms by

[00016]$b_{\mathrm{nI}}^{\left(N_b\right)}={\left(-1\right)}^{{}_{\mathrm{nI}}^{\left(N_b\right)}.Math.}.Math.\mathrm{and}.Math..Math.b_{n.Math.q}^{\left(N_b\right)}={\left(-1\right)}^{{}_{\mathrm{nq}}^{\left(N_b\right)}}.$

Both finite sets of quantizer symbols I={s.sub.I,0, s.sub.I,1, . . . , s.sub.I,N.sub.QL.sub.1} and Q={s.sub.q,0, s.sub.q,1, . . . , s.sub.q,N.sub.QL.sub.1} follow the rules (.sub.nI.sup.(N.sup.b.sup.1), .sub.nI.sup.(N.sup.b.sup.2), . . . , .sub.nI.sup.(1), .sub.nI.sup.(0))s.sub.nI,QT and (.sub.nq.sup.(N.sup.b.sup.1), .sub.nq.sup.(N.sup.b.sup.2), . . . , .sub.nq.sup.(1), .sub.nq.sup.(0))s.sub.nq,QT.

[0178] Each symbol from the finite set of in-phase components of the quantizer symbols I={s.sub.I,0, s.sub.I,1, . . . , s.sub.I,N.sub.QL.sub.1}, can be represented as a sume of N.sub.mIN.sub.b unipolar components that are the result of the decomposition of quantization value s.sub.nI,QT into polar components, given by

[00017]$\begin{array}{c}{s}_{\mathrm{nI},\mathrm{QT}}=b_{\mathrm{nI}}^{\left(N_b\right)}\left(g_0+g_1.Math.{}_{\mathrm{nI}}^{\left(0\right)}+g_2.Math..Math..Math.b_{\mathrm{nI}}^{\left(1\right)}+g_3.Math.{}_{\mathrm{nI}}^{\left(0\right)}.Math.{}_{\mathrm{nI}}^{\left(1\right)}+g_4.Math.{}_{\mathrm{nI}}^{\left(2\right)}+\mathrm{.Math.}\right)\\ =b_{\mathrm{nI}}^{\left(N_b\right)}.Math.\underset{i=0}{\overset{N_{\mathrm{mI}}-1}{.Math.}}.Math..Math.g_i.Math.\underset{m=0}{\overset{N_{\mathrm{mI}}-1}{.Math.}}.Math..Math.{\left({}_{\mathrm{nI}}^{\left(m\right)}\right)}^{{}_{m,i}}=b_{\mathrm{nI}}^{\left(N_b\right)}.Math.\underset{i=0}{\overset{N_{\mathrm{mI}}-1}{.Math.}}.Math..Math.g_i.Math.{}_{\mathrm{nI}}^{\mathrm{eq}\left(i\right)},\end{array}$

with (.sub.N.sub.mI.sub.1,i .sub.N.sub.mI.sub.2,i . . . .sub.1,i .sub.0,i) denoting the binary representation of i, .sub.nI.sup.eq(i)=.sub.m=0.sup.N.sup.mI.sup.1 (.sub.nI.sup.(m)).sup..sup.m,i and N.sub.mI is the number of non-zero g.sub.i real coefficients of the referred decomposition (the total number of coefficients is 2.sup.N.sup.b1). For example, for N.sub.b=3 and a symmetrical dynamic range (using as reference the zero value) the quantization levels are 7, 5, 3, , which can be given by

s.sub.nI,QT=b.sub.nI.sup.(N.sup.b.sup.)(g.sub.1.sub.nI.sup.(0)+g.sub.2.sub.nI.sup.(1)+g.sub.4.sub.nI.sup.(2))

where g.sub.1I=, g.sub.2I=2, g.sub.4I=4, b.sub.nI.sup.(N.sup.b.sup.)=1 and g0=g3=g5=g6=g7=0. For each quantized value only a number of components equal to the number of bits at one in the set of bits (.sub.nI.sup.(2), .sub.nI.sup.(1), .sub.nI.sup.(0)) are active at the mapper's output.

[0179] For the quadrature component each symbol from the finite set of quantizer symbols Q={s.sub.q,0, s.sub.q,1, . . . , s.sub.q,N.sub.QL.sub.1}, can be represetned as a sum of N.sub.mQN.sub.b unipolar components, that are the result of the decomposition of quantization value s.sub.nq,QT into polar components given by

[00018]$\begin{array}{c}{s}_{\mathrm{nq},\mathrm{QT}}=b_{\mathrm{nq}}^{\left(N_b\right)}\left(g_0+g_1.Math.{}_{\mathrm{nq}}^{\left(0\right)}+g_2.Math.{.Math.}_{\mathrm{nq}}^{\left(1\right)}+g_3.Math.{}_{\mathrm{nq}}^{\left(0\right)}.Math.{}_{\mathrm{nq}}^{\left(1\right)}+g_4.Math.{}_{\mathrm{nq}}^{\left(2\right)}+\mathrm{.Math.}\right)\\ =b_{\mathrm{nq}}^{\left(N_b\right)}.Math.\underset{i=0}{\overset{N_{\mathrm{mQ}}-1}{.Math.}}.Math..Math.g_i.Math.\underset{m=0}{\overset{N_m.Math.Q-1}{.Math.}}.Math..Math.{\left({}_{\mathrm{nq}}^{\left(m\right)}\right)}^{{}_{m,i}}=b_{\mathrm{nI}}^{\left(N_b\right)}.Math.\underset{i=0}{\overset{N_{\mathrm{mQ}}-1}{.Math.}}.Math..Math.g_i.Math.{}_{\mathrm{nq}}^{\mathrm{eq}\left(i\right)},\end{array}$

with b.sub.nq.sup.eq(i)=.sub.m=0.sup.N.sup.mQ.sup.1 (b.sub.nq.sup.(m)).sup..sup.m,i and N.sub.mQ is the number of non-zero g.sub.i imaginary coefficients of the referred decomposition (the total number of coefficients is 2.sup.N.sup.b1). For example, for N.sub.b=3 and a symmetrical dynamic range (using as reference the zero value) the quantization levels are j7, j5, j3, j, which can be given by

s.sub.nq,QT=b.sub.nq.sup.(N.sup.b.sup.)(g.sub.1b.sub.nq.sup.(0)+g.sub.2b.sub.nq.sup.(1)+g.sub.4b.sub.nq.sup.(2))

with g.sub.1Q=j, g.sub.2Q=j2, g.sub.4Q=j4 and g0=g3=g5=g6=g7=0.

[0180] Again, instead N.sub.mQ components only a number of components equal to the number of bits at one in the set of bits are active at the mapper's output. Each one of the N.sub.mI and N.sub.mQ polar components with amplitude g.sub.i can be modulated as a BPSK signal. Note that the pulse shape employed in each BPSK signal can be selected to achieve high spectral efficiency and constant envelope. In the OOIQQDCA embodiment the in-phase and quadrature components are used to generate constituent signals with quasi constant or constant envelope that are individually amplified. In the OOIQQDCAC embodiment the in-phase and quadrature components whit same amplitude are also combined to generate constituent signals with quasi constant or constant envelope that are individually amplified.

[0181] Operation of the OOQDCA and OOQDCAC embodiments shall be described further with reference to the flowchart of FIG. 5. Optional steps are illustrated with dashed lines. The process starts at step 501, which includes receiving a time varying envelope signal. In another embodiment this involves receiving the desired RF signal. In another embodiment this involves receiving the desired IF signal. In another embodiment this involves receiving the samples of the desired input signal or the samples of the in-phase and quadrature components of the time varying envelope signal.

[0182] Step 502 includes receiving a clock signal set according to the signal frequency of the input signal.

[0183] Step 503 includes receiving a clock signal set according to a desired sample rate of the input signal. It is important to mention that as understood by a person skilled in the art the sample rate may vary according to the bandwidth of the input signal and the desired time resolution of the sampling process.

[0184] Step 504 includes receiving a clock signal in accordance with a desired output signal frequency of the desired output signal.

[0185] Step 505 includes processing the input signal to generate in-phase and quadrature components.

[0186] Step 506 includes sampling the in-phase and quadrature components in accordance with the sampling rate to generate the samples of these components.

[0187] Step 507 includes processing individually by a quantizer the in-phase and quadrature components to generate the quantization bits and the corresponding quantized value of the in-phase and the quantization bits and the corresponding quantized value of the quadrature component, respectively. As understood by a person skilled in the art based on the teaching herein, step 507 can be performed by a block using a single quantizer. Also as understood by a person skilled in the art based on the teaching herein, step 507 can be performed by a comparator and a LUT with the corresponding quantization bits of the quantized values.

[0188] Step 508A includes processing individually the quantized value of the in-phase component to obtain the polarity and generate the corresponding polarity bit. Step 508B includes processing individually the quantized value of the quadrature component to obtain the polarity and generate the corresponding polarity bit.

[0189] Steps 509A and 509B include processing individually the polarity bit of the quantized value of the in-phase component to generate the corresponding polar representation and processing individually the polarity bit of the quantized value of the quadrature component to generate the corresponding polar representation.

[0190] Steps 510A and 510B include multiplying individually each quantization bit corresponding to the quantized value of the in-phase component by the polar signal of the polarity bit of the quantized in-phase component and multiplying individually each quantization bit corresponding to the quantized value of the quadrature component by the polar signal of the polarity bit of the quantized quadrature component, respectively.

[0191] Step 511A includes processing individually in a mapper the quantization bits associated to the quantized in-phase component to map them into the corresponding constituent signals. Step 511B includes processing individually in a mapper the quantization bits associated to the quantized quadrature component to map them into the corresponding constituent signals.

[0192] Steps 512A and 512B include multiplying the constituent signals of the quantized in-phase component by the signals that result from step 510A and multiplying the constituent signals of the quantized quadrature component by the signals that result from step 510B.

[0193] Step 513A includes processing the in-phase component signals that resulted from step 512A by multiplying the signals by a periodic pulse signal with the desired output signal frequency. The resulting quantized in-phase constituent signals may have quasi or constant envelopes and a sum equal to the in-phase component of the quantized sample of the input signal.

[0194] Step 513B includes processing the quadrature component signals that resulted from step 512B by multiplying the signals by a periodic pulse signal with the desired output signal frequency. The resulting quantized quadrature constituent signals may have quasi or constant envelopes and a sum equal to the quadrature component of the quantized sample of the input signal. Step 514 is an optional step that includes processing the signals that resulted from steps 513A and 513B, by summing the in-phase signals with the quadrature signals with the same amplitude to generate a set of complex constituent signals with quasi or constant envelopes and a sum equal to the quantized sample of the input signal

[0195] Step 515 includes individually amplifying each of one of the constituent signals, and summing the amplified signals to generate the desired output signal.

[0196] Block diagram 600A of FIG. 6A is an example that illustrates an exemplary embodiment of the OOQDCA, implementing the process flowchart 500 of FIG. 5, without the optional step 514. In the example of FIG. 6A, optional components are illustrated with dashed lines. In other embodiments, additional components may be optional.

[0197] In this example a time varying envelope signal 601, a clock reference signal 602 for the sampling process and a channel clock 603 with the desired frequency for the output signal are received as inputs. In another embodiment 601 can be the samples of a time varying envelope signal and the S/H 607 is not required. In another embodiment 601 can be the samples of the in-phase and quadrature components of a time varying envelope signal and 604 and 607 are not required.

[0198] The clock reference signal 602 can be used by the S/H 607, by the two quantizers 610 and 611 and by the polar converters 620 and 622. It can be understood by a person skilled in the art that the choice of the clock reference signal is made according the bandwidth of the input signal and the desired output signal. As understood by a person skilled in the art other reference clock signals and different reference clock signals may be used by the different blocks. It is noted that two 3 bit quantizers and 6 amplification branches are employed in this embodiment only for purposes of illustration, and not limitation. The scope of the invention covers use of other numbers of branches, and implementation of such variations will be apparent to persons skilled in the art based on the teachings contained herein.

[0199] The phase splitter 604 receives the input signal 601 and generates the in-phase and quadrature components 605a and 605b, respectively.

[0200] The S/H circuit 607 samples the received signal according to a clock signal 602 and generates the time samples the in-phase component 608 and the time samples of the quadrature component 609. The sample of the in-phase component 608 is converted by the quantizer 610 into 3 quantization bit signals 612, 613, and 614, one polarity bit signal 615 and one end of conversion bit signal 612a. The sample of the quadrature component 609 is converted by the quantizer 611 into 3 bit signals 616, 617, and 618, one polarity bit signal 619 and one end of conversion bit signal 616a to be used to control the constituent signal mapper. Signal 615 is submitted to a polar converter 620 that generates the polar signal 621. Also the polarity bit signal 619 of the quadrature component is provided to a polar converter 622 that generates the polar signal 623.

[0201] The quantization bit signals 612, 613 and 614 are multiplied in 624, 625 and 626 by the polar signal 621 to generate the signals 639, 640 and 641. The quantization bit signals 616, 617 and 618 are multiplied in 627, 628 and 629 by the polar signal 623.

[0202] The signal 612a is applied to the in-phase constituent signal mapper 630 that generates the signals 631, 632 and 633 with amplitudes that correspond to the coefficients associated to each bit. In another embodiment the signals 612, 613, and 614 are provided to the in-phase constituent signal mapper 630 that generates the signals 631, 632 and 633 with amplitudes that correspond to the coefficients associated to each bit. Amplitudes of 631, 632 and 633 correspond to the coefficients g.sub.1I, g.sub.2I and g.sub.4I. Each signal 631, 632 and 633 is multiplied individually in 624, 625 and 626 by the result of the product of the corresponding quantization bit and the polarity bit 621 to generate the signals 638, 639 and 640. The in-phase constituent components 631, 632 and 633 are multiplied in 644, 645 and 646 by the signals 638, 639 and 640 to generate the signals 651, 652 and 653 that correspond to the signals s.sub.1I, s.sub.2I and s.sub.4I, associated to the decomposition of the in-phase component of the quantized value. Each signal mapper also generates for each constituent signal component a pulse shape to assure good spectral efficiency and power efficiency.

[0203] The signal 616a is applied to the quadrature constituent signal mapper 634 that generates the signals 635, 636 and 637 with amplitudes that correspond to the coefficients associated to each bit. In another embodiment the signals 616, 617, and 618 are provided to the quadrature constituent signal mapper 634 that generates the signals 635, 636 and 637 with amplitudes that correspond to the coefficients associated to each bit. Amplitudes of 635, 636 and 637 correspond to the coefficients g.sub.1Q, g.sub.2Q and q.sub.4Q. Each signal 635, 636 and 637 is multiplied individually in 627, 628 and 629 by the result of the product of the corresponding quantization bit and the polarity bit 623 to generate the signals 641, 642 and 643. The quadrature constituent components 635, 636 and 637 are multiplied in 647, 648 and 649 by the signals 641, 642 and 643 to generate the signals 654, 655 and 656 that correspond to the signals s.sub.1Q, s.sub.2Q and s.sub.4Q, associated to the decomposition of the quadrature component of the quantized value.

[0204] In-phase constituent signals 659, 660 and 661 are obtained by multiplying in 657-{1, . . . , 3} the signals 651, 652 and 653 by a periodic pulse signal 650 with the desired frequency for the output signal generated by 606. Quadrature constituent signals 661, 662 and 663 are obtained by multiplying in 657-{4, . . . , 6} the signals 654, 655 and 656 by a periodic pulse signal 651 with the desired frequency for the output signal generated by 606.

[0205] In other embodiments the signal 650 can be a sinusoidal signal or a pulse train signal with frequency selected according to the desired frequency of the output signal.

[0206] The constituent signals 658, 650, 660, 661, 662 and 663 with quasi and/or constant envelope are the inputs of the corresponding PAs 664-{1, . . . , 6} of the amplification stage, that may be non-linear power amplifiers. In another embodiment PAs 664-{1, . . . , 6} include switching power amplifiers of class D. In other embodiments PAs 664-{1, . . . , 6} include switching power amplifiers of class E or class F.

[0207] The outputs of PAs 665, 666, 667, 668, 669 and 670 are coupled together in a combiner 671 using well known combining techniques such as active combiners or other techniques such as Wilkison, hybrid or transformers. Alternatively, the outputs of PAs 664-{1, . . . , 6} can be coupled through inductances and/or capacitances for a minimal power loss. Amplification stage and combiner stage embodiments according to power amplification methods and systems of the present invention will further described in section 3.1.

[0208] The output signal from the combiner 672 is submitted to a bandpass filter 673 with central frequency equal to the desired frequency of the output signal, being the signal 674 the desired amplified signal.

[0209] In another embodiment a self bias circuit 676 can be employed to provide bias signals 676-{1, . . . , 6} to the PA's. In another embodiment a phase control circuit 677 could be also employed to generate control signals 678-{1, . . . , 6} to compensate any phase shifts among amplifiers.

[0210] Block diagram 600B of FIG. 6B is an example that illustrates an exemplary embodiment of the OOQDCA, implementing the process flowchart 500 of FIG. 5, with the optional step 514. In the example of FIG. 6B, optional components are illustrated with dashed lines. In other embodiments, additional components may be optional.

[0211] In this example a time varying envelope signal 601, a clock reference signal 602 for the sampling process and a channel clock 603 with the desired frequency for the output signal are received as inputs. In another embodiment 601 can be the samples of a time varying envelope signal and the S/H 607 is not required. In another embodiment 601 can be the samples of the in-phase and quadrature components of a time varying envelope signal and 604 and 607 are not required.

[0212] The clock reference signal 602 can be used by the S/H 607, by the two quantizers 610 and 611 and by the polar converters 620 and 622. It can be understood by a person skilled in the art that the choice of the clock reference signal is made according the bandwidth of the input signal and the desired output signal. As understood by a person skilled in the art other reference clock signals and different reference clock signals may be used by the different blocks. It is noted that two 3 bit quantizers and 3 amplification branches are employed in this embodiment for purposes of illustration, and not limitation. The scope of the invention covers use of other numbers of branches, and implementation of such variations will be apparent to persons skilled in the art based on the teachings contained herein.

[0213] The phase splitter 604 receives the input signal 601 and generates the in-phase and quadrature components 605a and 605b, respectively.

[0214] The S/H circuit 607 samples the received signal according to a clock signal 602 and generates the samples the in-phase component 608 and the samples of the quadrature component 609. The sample of the in-phase component 608 is converted, by the quantizer 610, into 3 quantization bit signals 612, 613, and 614, one polarity bit signal 615 and one end of conversion bit signal 612a. The sample of the quadrature component 609 is converted, by the quantizer 611, into 3 bit signals 616, 617, and 618, one polarity bit signal 619 and one end of conversion bit signal 616a to be used to control the constituent signal mapper. Signal 615 is submitted to a polar converter 620 that generates the polar signal 621. Also the polarity bit signal 619 of the quandrature component is provided to a polar converter 622 that generates the polar signal 623.

[0215] The quantization bit signals 612, 613 and 614 are multiplied in 624, 625 and 626 by the polar signal 621 to generate the signals 638, 639 and 640. The quantization bit signals 616, 617 and 618 are multiplied in 627, 628 and 629 by the polar signal 623.

[0216] The signal 612a is applied to the in-phase constituent signal mapper 630 that generates the signals 631, 632 and 633 with amplitudes that correspond to the coefficients associated to each bit. In another embodiment the signals 612, 613, and 614 are provided to the in-phase constituent signal mapper 630 that generates the signals 631, 632 and 633 with amplitudes that correspond to the coefficients associated to each bit. Amplitudes of 631, 632 and 633 correspond to the coefficients g.sub.1I, g.sub.2I and g.sub.4I. Each signal 631, 632 and 633 is multiplied individually in 624, 625 and 626 by the result of the product of the corresponding quantization bit and the polarity bit 621 to generate the signals 638, 639 and 640. The in-phase constituent components 631, 632 and 633 are multiplied in 644, 645 and 646 by the signals 638, 639 and 640 to generate the signals 652, 653 and 654 that correspond to the signals s.sub.1I, s.sub.2I and s.sub.4I, associated to the decomposition of the in-phase component of the quantized value. Each signal mapper also generates for each constituent signal component a pulse shape to assure good spectral efficiency and power efficiency.

[0217] The signal 616a is applied to the quadrature constituent signal mapper 635 that generates the signals 635, 636 and 637 with amplitudes that correspond to the coefficients associated to each bit. In another embodiment the signals 616, 617, and 618 are provided to the quadrature constituent signal mapper 634 that generates the signals 635, 636 and 637 with amplitudes that correspond to the coefficients associated to each bit. Amplitudes of 635, 636 and 637 correspond to the coefficients g.sub.1Q, g.sub.2Q and g.sub.4Q. Each signal 635, 636 and 637 is multiplied individually in 627, 628 and 629 by the result of the product of the corresponding quantization bit and the polarity bit 623 to generate the signals 641, 642 and 643. The quadrature constituent components 635, 636 and 637 are multiplied in 647, 648 and 649 by the signals 641, 642 and 643 to generate the signals 654, 655 and 656 that correspond to the signals s.sub.1Q, s.sub.2Q and s.sub.4Q, associated to the decomposition of the quadrature component of the quantized value.

[0218] The In-phase constituent signals 658, 659 and 660 are obtained by multiplying in 657-{1, . . . , 3} the signals 651, 652 and 653 by a periodic pulse signal 650 with the desired frequency for the output signal generated by 606. The quadrature constituent signals 661, 662 and 663 are obtained by multiplying signals 654, 655 and 656 by a periodic pulse signal 650 with the desired frequency for the output signal generated by 606.

[0219] In other embodiments the signal 650 can be a sinusoidal signal or a pulse train signal with frequency selected according to the desired frequency of the output signal.

[0220] In 664-1, 664-2 and 664-3 each in-phase constituent signal 658, 659 and 660 is summed with the corresponding quadrature constituent signal 661, 662 and 663 with the same amplitude, i. e. each in-phase component is combined with the corresponding quadrature component with the same amplitude to generate the constituent complex signals 665, 666 and 667. Constituent signals 665, 666 and 667 have quasi or constant envelope and are the inputs of the corresponding power amplifiers (PAs) 668-{1, . . . , 3} of the amplification stage that may be non-linear power amplifiers.

[0221] The constituent signals 665, 666 and 667 have quasi and/or constant envelope and are the inputs of the corresponding PAs 668-{1, . . . , 3} of the amplification stage, that may be non-linear power amplifiers. In another embodiment PAs 668-{1, . . . , 3} include switching power amplifiers of class D. In other embodiments PAs 668-{1, . . . , 3} include switching power amplifiers of class E or class F.

[0222] The outputs of PAs 669, 670 and 671 are coupled together in a combiner 672 using well known combining techniques such as active combiners or other techniques such as Wilkison, hybrid or transformers. Alternatively, the outputs of PAs 669, 670 and 671 can be coupled through inductances and/or capacitances for a minimal power loss. Amplification stage and combiner stage embodiments according to power amplification methods and systems of the present invention will further described in section 3.1.

[0223] The output signal from the combiner 673 is submitted to a bandpass filter 674 with central frequency equal to the desired frequency of the output signal, being the signal 675 the desired amplified signal.

[0224] In another embodiment a self bias circuit 676 can be employed to provide bias signals 677-{1, . . . , 3} to the PAs. In another embodiment a phase control circuit 678 could be also employed to generate control signals 679-{1, . . . , 3} to compensate any phase shifts among amplifiers.

[0225] In other embodiment voltage-to-current or current-to-voltage converters 680-{1, . . . , 6} may be employed before the sum of the in-phase and quadrature constituent signals with same amplitude performed in 664-{1, . . . , 3}. It is important to mention that as understood by a person skilled in the art that the voltage-to-current or the current-to-voltage converters 680-{1, . . . , 6} may be embedded in the sum operations or in the multiplications performed in 657-{1, . . . , 6}.

3. MULTI AMPLIFIER AMPLIFICATION STAGE

[0226] One aspect of embodiments of the present invention lies in the multi amplifier amplification (MAA) stage. This is shown, for example, in FIG. 4A where the amplification stage has six PAs 451-{1, . . . , 6} or in FIG. 4B where the amplification stage has three PAs 451-{1, . . . , 3}. This is also shown in FIGS. 2A, 2B, 6A and 6B, for example. Various embodiments for MAA stage are described herein. While the following is described in the context of QDCA, it should be understood that the following teachings generally apply to coupling or summing the outputs of any active devices in any application.

[0227] In another aspect, amplification stage embodiments of the present invention can be controlled to increase the power efficiency of the amplifier by controlling the output stage's current according to the desired output power level.

[0228] In what follows, various amplification stage embodiments according to QDCA embodiments of the present invention are provided in section 3.1.

3.1. Multi Amplifier and Combiner Embodiments

[0229] Block diagram 700 of FIG. 7, illustrates a multi power amplifier stage embodiment 700 with class F amplifiers according to an embodiment of the present invention. Multi power amplifier stage embodiment 700 includes a plurality of PA branches 708-{1, . . . , n}. Signals 701-{1, . . . , n} incoming from respective the products of the constituent signals components by a periodic signal represent inputs for amplification stage 700. Referring FIGS. 2, 2A, 4, 4A, 6 and 6A, the input signals are the sets of signals 231, 232, 233, 234, 235 and 236, signals 237, 238 and 239, signals 448, 449, 450, 451, 452 and 453, signals 455, 456, 457, signals 658, 659, 660, 661, 662, 663 and signals 665, 666 and 667, respectively. According to this embodiment of the present invention, signals 701-{1, . . . , n} represent the constant envelope constituent signals of a desired output signal of the power amplifier.

[0230] PA branches 708-{1, . . . , n} apply equal or substantially equal power amplification to respective signals 701-{1, . . . , n}. In an embodiment, the power amplification level through PA branches 708-{1, . . . , n} is set according to a power level requirement of the desired output signal.

[0231] In the embodiment of FIG. 7, each PA branch 708-{1, . . . , n} includes a limiter 702-{1, . . . , n}, an optional driver 703-{1, . . . , n}, an optional matching impedance 704-{1, . . . , n} and a power amplifier 706-{1, . . . , n}. In other embodiments, drivers 703-{1, . . . n} as illustrated in FIG. 7, may also be added in a PA branch prior to the power amplifier element to reinforce the input signal 705-{1, . . . , n}. In embodiments, drivers are employed whenever a required output power level may not be achieved in a single amplifying stage. According to embodiment 700, PAs 706-{1, . . . , n} include switching power amplifiers. In the example of FIG. 7, power amplifiers 706-{1, . . . , n} include Field Effect Transistor (FET) devices T1, . . . , Tn, inductances L1, . . . , Ln, and supply tensions V.sub.suppply1, . . . , V.sub.supplyn. To generate the desired output signal, outputs of PA branches 707-{1, . . . , n} are coupled at the combiner 711 to generate the output signal 712. Accordingly, minimal power loss is incurred in summing the outputs of PAs 707-{1, . . . n}.

[0232] In another embodiment an optional bias circuit 709, as illustrated in FIG. 7, may be also employed to provide the bias signals 710-{1, . . . , n} that control the amount of current flow through the PAs 706-{1, . . . n}.

[0233] In one embodiment the combiner 711 is a near zero-impedance conducting wire that provides minimal isolation between the coupled outputs. It is noted that in certain embodiments of the present invention, output coupling, as shown in the embodiment of FIG. 7 or embodiments subsequently described below, may utilize certain output stage protection measures. These protection measures may be implemented at different stages of the PA branch. Further, the type of protection measures needed may be PA implementation-specific.

[0234] Block diagram 800 of FIG. 8 illustrates another multi power amplifier output stage with class D amplifiers according to an embodiment of the present invention. Similarly to the embodiment of FIG. 7, the output stage 800 includes a plurality of PA branches 808-{1, . . . , n}. Signals 801-{1, . . . , n} incoming from respective the products of the constituent signals components by a periodic signal represent inputs for amplification stage 800. Referring FIGS. 2, 2A, 4, 4A, 6 and 6A, the input signals are the sets of signals 231, 232, 233, 234, 235 and 236, signals 237, 238 and 239, signals 448, 449, 450, 451, 452 and 453, signals 455, 456, 457, signals 658, 659, 660, 661, 662, 663 and signals 665, 666 and 667, respectively. According to this embodiment of the present invention, signals 801-{1, . . . , n} represent the constant envelope constituent signals of a desired output signal of the power amplifier.

[0235] Each of PA branch 808-{1, . . , n} may include multiple power amplification stages represented by a limiter 802-(1, . . . , n) that provides a signal 802-{1, . . . , n} to the drivers in parallel 803-{1, . . . , n} and 804-{1, . . . , n} each one providing a input signal to the corresponding transistors TP-{1, . . . n} and TN-{1, . . . , n} of each signal power amplifier 806-{1, . . . , n}. Each signal power amplifier 806-{1, . . . , n} includes two transistors TP-{1, . . . , n} and TN-{1, . . . , n} followed by a capacitor C-{1, . . . , n} and a inductance L-{1, . . . , n}. Signal power amplifier 806-{1, . . . , n} have supply tensions V.sub.suppply1, . . . , V.sub.supplyn.

[0236] To generate the desired output signal, outputs of PA branches 807-{1, . . . , n} are coupled at the combiner 809 to generate the output signal 810. Accordingly, minimal power loss is incurred in summing the outputs of PAs 807-{1, . . . , n}.

[0237] In an embodiment the combiner 809 is a near zero-impedance conducting wire that provides minimal isolation between the coupled outputs.

[0238] Block diagram 900 of FIG. 9 illustrates another multi amplifier amplification stage embodiment with class A, B, AB or C amplifiers according to the present invention. Similarly to the embodiment of FIG. 7, the multi amplifier amplification stage 900 includes a plurality of PA branches 907-{1, . . . , n}. Signals 901-{1, . . . , n} incoming from respective the products of the constituent signals components by a periodic signal represent inputs for amplification stage 900. Referring FIGS. 2, 2A, 4, 4A, 6 and 6A, the input signals are the sets of signals 231, 232, 233, 234, 235 and 236, signals 237, 238 and 239, signals 448, 449, 450, 451, 452 and 453, signals 455, 456, 457, signals 658, 659, 660, 661, 662, 663 and signals 665, 666 and 667, respectively. According to this embodiment of the present invention, signals 901-{1, . . . , n} represent the quasi constant or constant envelope constituent signals of a desired output signal of the power amplifier.

[0239] Each of PA branches 907-{1, . . . , n} may include multiple power amplification stages represented by a driver 902-{1, . . . , n}, a matching impedance 903-{1, . . . , n} and power amplifier 905-{1, . . . , n}. According to embodiment 900, PAs 905-{1, . . . , n} include FET devices T1, . . . , Tn. In the example of FIG. 9, power amplifiers 905-{1, . . . , n} include FET devices T1, . . . , Tn, inductances L1, . . . , Ln, and supply tensions V.sub.suppply1, . . . , V.sub.supplyn. The multi amplifier amplification stage embodiment 908 includes a bias control circuit network 909-{1, . . . , n} that provides bias signals 909-{1, . . . , n} coupled to each PA 905-{1, . . , n} in each PA branch 907-{1, . . . , n}. To generate the desired output signal, outputs of PA branches 906-{1, . . . , n} are coupled at the combiner 910 to generate the output signal 911. Accordingly, minimal power loss is incurred in summing the outputs of PAs 906-{1, . . . , n}.

[0240] Block diagram 1000 of FIG. 10 illustrates another multi amplifier amplification stage embodiment according to the present invention. Similarly to the embodiment of FIG. 7, output stage 1000 includes a plurality of PA branches 1006-{1, . . . , n}. Each of PA branches 1006-{1, . . . , n} may include multiple power amplification stages represented a delta sigma modulator 1002-{1, . . . , n}, two drivers in parallel 1003-{1, . . . , n} and 1004-{1, . . . , n} and a PA 1005-{1, . . . , n} composed by two transistors TP-{1, . . . , n} and TN-{1, . . . , n} in parallel followed by a capacitor C-{1, . . . , n} and an inductance L-{1, . . . , n}.

[0241] According to embodiment 1000, PAs 1005-{1, . . . , n} include switching power amplifier stages. In the example of FIG. 10, power amplifiers 1005-{1, . . . , n} include FET devices TP1, . . . , TPn and TN1, . . . , TNn, respectively channel P and channel N. The complementary stack arrangement of P and N type channel transistors forms a class D based stage, taking advantage of the efficiency associated with this type of amplification stage.

[0242] To generate the desired output signal, outputs of PA branches 1007-{1, . . . , n} are coupled at the combiner 1008 to generate the output signal 1009. Accordingly, minimal power loss is incurred in summing the outputs of PAs 1007-{1, . . . , n}.

[0243] Embodiments are not limited to one type of FET channel N devices as described herein. A person skilled in the art will appreciate, for example, that embodiments of the present invention may be implemented using npn or pnp Bipolar Junction Transistors (BJTs), complementary MOS (CMOS), N-type MOS (NMOS), positive channel MOS (PMOS), Laterally Diffused MOS (LDMOS), BiCMOS or other type of transistors. Further, embodiments can be implemented using GaAs, Gallium nitride (GaN) and/or SiGe (silicon-germanium) transistors with the desired transistor switching speed being a factor to consider.

[0244] In embodiments, the number of transistors included within each PA is set according to a required maximum output power level of the power amplifier. In other embodiments, the number of transistors in the PA is such that the numbers of transistors in the pre-driver, driver, and PA stages conform to a geometric progression.

[0245] While preferred embodiments of the present disclosure have been described above, the present disclosure is not limited to the specific configurations described above. Various variations and modifications may be made without departing from the scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.

4. SUMMARY

[0246] Mathematical basis for a new concept related to processing signals to provide power amplification is provided herein. These new concepts permit arbitrary waveforms to be constructed from sums of waveforms which are substantially constant envelope in nature. Desired output signals and waveforms may be constructed from substantially constant envelope constituent signals which can be created from the knowledge and quantization of the time varying envelope of the input signal. Constituent signals of the quantized signal are generated and summed using novel techniques not available commercially, not taught or found in literature or related art. Furthermore, the blend of various techniques and circuits provided in the disclosure provide unique aspects of the invention which permits superior linearity, power added efficiency, monolithic implementation and low cost. Embodiments of the invention can be implemented by a blend of hardware, software and firmware. Both digital and analog techniques can be used with or without microprocessors and DSP's (digital signal processors).

[0247] Embodiments of the invention can be implemented for communications systems and electronics in general. In addition, and without limitation, mechanics, electro mechanics, electro optics, and fluid mechanics can make use of the same principles for efficiently amplifying and transducing signals.

5. CONCLUSIONS

[0248] The present invention has been described above with the aid of functional building blocks illustrating the functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. Any such alternate boundaries are thus within the scope and spirit of the claimed invention. One person skilled in the art will recognize that these functional building blocks can be implemented by discrete components, application specific integrated circuits, processors executing appropriate software and the like and combinations thereof.

[0249] While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.