HIGH-VOLTAGE FAST-AVALANCHE DIODE

Abstract

A high-voltage fast-avalanche diode, being a silicon-avalanche shaper or sharpener (SAS), has a thick active region above 300 microns in thickness.

Claims

1. A diode device comprising: a high-voltage fast-avalanche diode comprising a silicon-avalanche shaper or sharpener (SAS) that has a thick active region above 300 microns in thickness.

2. The diode device according to claim 1, wherein said SAS has a rise time of 100 ps.

3. The diode device according to claim 1, wherein said SAS has an output voltage of 7.9 kV.

4. The diode device according to claim 1, wherein said SAS comprises a vertical p+-n.sub.0-n.sup.+ structure with a substrate comprising a float-zone, N-type Si wafer.

5. A method of making the diode device of claim 1 comprising: creating a p.sup.+ layer by depositing a thermal oxide on both sides of an at least 300 micron, 10 kΩ-cm, n-type, float zone wafer; selectively making on a top side of the wafer a p.sup.+-n.sub.0 junction; applying a boron SOD or other doping acceptors such as aluminum, and other methods such as an ion-implantation to the top side; making a drive-in of boron; etching the thermal oxide on the bottom side of the wafer; applying phosphorous SOD or other donors such as arsenic, and other methods such as ion-implantation to the bottom side; making a drive-in of phosphorous on the bottom side; and forming metallic contacts to the structure.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG. 1 illustrates SAS structure (not to scale), in accordance with an embodiment of the invention.

[0013] FIG. 2 illustrates an experimental setup circuitry for the device of the invention.

[0014] FIG. 3 shows the load voltage versus time, measured on a 50 Ω load.

DETAILED DESCRIPTION

[0015] Reference is now made to FIGS. 1 and 2.

[0016] The SAS diode may be prepared by the following process, in accordance with a non-limiting embodiment of the invention:

[0017] First implant, of the p.sup.+ layer:

[0018] 1. A thermal oxide, SiO.sub.2, is deposited on both sides of a 525 micron, 10 kΩ-cm, n-type, float zone wafer.

[0019] 2. Selective opening in the “top” (boron) side is made via a mask which includes the p.sup.+-n.sub.0 junction, as in FIG. 1.

[0020] 3. A boron-SOD is applied to the structure top side. It is noted that this step can be replaced by a standard method such as ion-implantation, or diffusion using a solid or a gas source. Also, other acceptor materials such as aluminum can be used as well.

[0021] 4. A drive-in of the boron for a depth of a few microns is made.

[0022] Second Implant, of the n+ Layer:

[0023] 1. Etching of the oxide in the “bottom” (phosphorous) side of the wafer is made.

[0024] 2. A phosphorous SOD is applied to the structure bottom side. It is noted that this step can be replaced by a standard method such as ion-implantation, or diffusion using a solid or a gas source. Also, other donor materials such as arsenic can be used as well.

[0025] 3. A drive-in of the phosphorous for a depth of about a few microns is made.

Finally, metallic contacts are applied to the structure.

[0026] A diode with a junction cross section of 4 mm.sup.2 may be thus prepared. Its leakage current is measured at a reverse voltage of 3 kV. A 72 μA current is measured without a breakdown. When two diodes are connected in series the leakage current is reduced by a factor of 2.

[0027] In order to test it dynamically, the inventors connected its cathode to the ground via a 1 pF peaking capacitor, and also to a 6-kV, 1-ns pulsed-power generator (measured on a 50-Ω load) via a 200 pF DC-block capacitor and a 20 nH coil, as shown in FIG. 2. The SAS anode was connected to a 50 Ω load and measured by a high-voltage attenuator and an 8-GHz oscilloscope. The inventors estimate that the maximum voltage obtained at the peaking capacitor before the SAS was turned on was about 14 kV.

[0028] Experimental Result

[0029] FIG. 3 shows the load voltage, measured on a 50 Ω load. A peak voltage of 7.9 kV was obtained. Following a pre-pulse of about 1.5 kV, a sharp, 100-ps rise time was obtained. The maximum voltage rise-rate at the load was 52 kV/ns. The experimental results are supported by a numerical simulation (not shown here).

[0030] Comparison

[0031] Table 1 shows a comparison of this invention to two other state-of-the-art sharpening devices from the literature (first column). The second column shows the width of the active region. It is noted that the width in this invention is substantially wider, which enables working with a thick wafer, and alleviates the need for deep diffusion. Therefore it simplifies the process and reduces the cost.

[0032] The third and fourth columns describe the input and output pulse, respectively, in terms of peak voltage and rise-time. The fifth column describes the maximum rise-rate of the load voltage. The sixth column refers to the number of diodes used, in case of a high-voltage stack [13], thus, the seventh column calculates the rise-rate per diode. The eighth column shows a figure of merit for the sharpening quality, in terms of output rise-rate to input voltage and its rise-time.

[0033] It is seen that in this invention the voltage rise rate (single diode) and the quality of sharpening is higher than the prior art.

TABLE-US-00001 Max # of sharpening Active dV.sub.o/dt diodes, (dV.sub.o/dt)/N (dV.sub.o/dt)/ Ref. region V-in V-out [kV/ns] N [kV/ns] (Vin/tr) Lyubutin 180 μm 180 kV/ 150 kV/100 ps 1580 44 36 3.5 (2010) [13] 400 ps Brylevskiy 100 μm 2.2 kV/ 1.25 kV/100 ps 10 1 10 3.2 (2019) [14] 700 ps This 520 μm 10 kV/ 7.9 kV/100 ps 48 1 52 5.2 invention 1 ns

REFERENCES

[0034]

TABLE-US-00002 1 Kesar, A. S., et al. “6-kV, 130-ps rise-time pulsed-power circuit featuring cascaded compression by fast recovery and avalanche diodes.” Electronics Letters 49.24 (2013): 1539-1540, and references therein. 2 Merensky, Lev M., et al. “The driving conditions for obtaining subnanosecond high-voltage pulses from a silicon-avalanche-shaper diode.” IEEE Transactions on Plasma Science 42.12 (2014): 4015-4019, and references therein. 3 Kesar, Amit S., et al. “Characterization of a drift-step-recovery diode based on all epi-Si growth.” IEEE Transactions on Plasma Science 44.10 (2016): 2424-2428, and references therein. 4 Kesar, Amit S. “A Compact, 10-kV, 2-ns risetime pulsed-power circuit based on off-the-shelf components.” IEEE Transactions on Plasma Science 46.3 (2018): 594-597, and references therein. 5 Yatom, S., et al. “Spectroscopic study of plasma evolution in runaway nanosecond atmospheric-pressure He discharges.” Physical Review E 88.1 (2013): 013107. 6 Kesar, Amit S. “Underground anomaly detection by electromagnetic shock waves.” IEEE Transactions on Antennas : and Propagation 59.1 (2010) 149-153. 7 Kardo-Sysoev, A. F. “New power semiconductor devices for generation of nano and subnanosecond pulses,” in Ultra-Wideband Radar Technology, J. D. Taylor, Ed. New' York: CRC Press, 2001. 8 Kardo-Sysoev, A. F., and M. V. Popova. “Modeling of fast ionization waves in silicon pn junctions under breakdown.” Semiconductors 30.5 (1996): 431-435. 9 Grekhov, Igor V., et al. “High-power semiconductor-based nano and subnanosecond pulse generator with a low delay time.” IEEE Transactions on Plasma Science 33.4 (2005): 1240-1244. 10 Minarskii, A. M., and Rodin, P. B. “Critical voltage growth rate when initiating the ultrafast impact ionization front in a diode structure.” Semiconductors 34.6 (2000): 665-667. 11 Rodin, P., et al. “Superfast fronts of impact ionization in initially unbiased layered semiconductor structures.” Journal of applied physics 92.4 (2002): 1971-1980. 12 Rodin, Pavel, et al. “Tunneling-assisted impact ionization fronts in semiconductors.” Journal of applied physics 92.2 (2002): 958-964. 13 Lyubutin, Sergei K., et al. “High-power ultrafast current switching by a silicon sharpener operating at an electric field close to the threshold of the Zener breakdown.” IEEE Transactions on Plasma Science 38.10 (2010): 2627-2632. 14 Brylevskiy, Victor, et al. “Picosecond-Range Avalanche Switching Initiated by a Steep High-Voltage Pulse: Si Bulk Samples Versus Layered pn Junction Structures.” physica status solidi (b) 256.6 (2019): 1800520.