Method for synchronizing an active load modulation clock within a transponder, and corresponding transponder

Abstract

A transponder communicates with a reader using active load modulation. The transponder includes a digital phase locked loop (DPLL), which, in operation, generates an active load modulation (ALM) carrier clock synchronized to carrier clock of the reader. Between transmission of data frames, the DPLL is placed in a lock mode of operation in which a feedback loop of the DPLL is closed. Within a transmitted data frame having a duration, the DPLL is placed, for the duration of the transmitted data frame, in a hold mode of operation in which the feedback loop is opened. A phase of the ALM carrier clock is adjusted at least once during the duration of the transmitted data frame.

Claims

1. A method, comprising: generating an active load modulation (ALM) carrier clock of a transponder synchronized to a carrier clock of a reader using a digital phase locked loop (DPLL), the DPLL having a frequency which is a multiple N of a frequency of the carrier clock of the reader, where N is an integer value; and transmitting, using a near field communication protocol, data frames from the transponder to the reader using the ALM carrier clock, the generating the ALM carrier clock including: between transmission of data frames, placing said DPLL in a lock mode of operation in which a feedback loop is closed; and within a transmitted data frame having a duration, placing, for the duration of the transmitted data frame, said DPLL in a hold mode of operation in which the feedback loop is opened; and adjusting a phase of said ALM carrier clock at least one time during the duration of the transmitted data frame.

2. The method according to claim 1, comprising adjusting the phase of said ALM carrier clock several times within each transmitted data frame.

3. The method according to claim 1, comprising: generating, using a digitally controlled oscillator having an oscillator frequency which is the multiple N times the frequency of the carrier clock of the reader, an oscillator signal; and dividing, using a divider, the oscillator signal by the multiple N.

4. The method according to claim 1, wherein the DPLL comprises a digitally controlled oscillator and the method includes adjusting a frequency of said digitally controlled oscillator based on an adjustment to the phase of said ALM carrier clock.

5. A device, comprising: means for generating an active load modulation (ALM) carrier clock synchronized to a carrier clock of a reader, the means having a frequency which is a multiple N of a frequency of the carrier clock of the reader, where N is an integer value; and means for transmitting data frames to the reader using the ALM carrier clock, wherein the generating the ALM carrier clock includes: between transmission of data frames, placing the means for generating in a lock mode of operation in which a feedback loop of the means for generating is closed; and within a transmitted data frame having a duration, placing, for the duration of the transmitted data frame, the means for generating in a hold mode of operation in which the feedback loop is opened; and adjusting a phase of said ALM carrier clock at least once during the duration of the transmitted data frame.

6. The device of claim 5 wherein adjusting the phase of said ALM carrier clock at least once during the duration comprises adjusting the ALM carrier clock a plurality of times within each transmitted data frame.

7. The device of claim 5 wherein the means for generating comprises: digitally controlled oscillating means having an oscillator frequency which is the multiple N times the frequency of the carrier clock of the reader, wherein the digitally controlled oscillating means, in operation, generates an oscillator signal; and means for dividing the oscillator signal by the multiple N.

8. The device of claim 7 wherein adjusting the phase of the ALM carrier clock comprises controlling a parameter of the means for dividing.

9. The device of claim 8 wherein said divider comprises a counter, which, in operation, performs said division by the multiple N and outputs said ALM carrier clock, and controlling the parameter of the means for dividing comprises resetting the counter to a determined value based on a previous phase shift between the carrier clock of the reader and the ALM carrier clock of the means for generating in lock mode.

10. The device of claim 5 wherein the means for transmitting transmits near field communication protocol signals.

11. A device, comprising: a digital phase locked loop (DPLL) including a phase frequency detector, a digital loop filter, a digitally controlled oscillator (DCO) and a divider, wherein the DPLL, in operation, generates an active load modulation (ALM) carrier clock synchronized to a reader carrier clock, the DPLL having a frequency which is a multiple N of a frequency of the carrier clock of the reader, where N is an integer value; frequency correction circuitry coupled to the DPPL; and transmission circuitry, which, in operation, transmits data frames to the reader using the ALM carrier clock, wherein the frequency correction circuitry, in operation, determines a frequency difference during transmission of a data frame and generates a control signal to adjust a frequency of the DCO based on the determined frequency difference, wherein the generating the ALM carrier clock includes: between transmission of data frames, placing said DPLL in a lock mode of operation in which a feedback loop of the DPLL is closed; and within a transmitted data frame having a duration, placing, for the duration of the transmitted data frame, said DPLL in a hold mode of operation in which the feedback loop is opened; and adjusting a phase of said ALM carrier clock at least once during the duration of the transmitted data frame.

12. The device of claim 11 wherein adjusting the phase of said ALM carrier clock at least once during the duration comprises adjusting the ALM carrier clock a plurality of times within each transmitted data frame.

13. The device of claim 11 wherein the divider comprises a counter, which, in operation, divides an output of the DCO by the multiple N and outputs the ALM carrier clock, and, in operation, the counter is reset to a determined value based on a previous phase shift between the carrier clock of the reader and the ALM carrier clock of the DPLL in lock mode.

14. The device claim 13 wherein the frequency correction circuitry, in operation, determines the frequency difference based on a difference between the determined value and an actual value of the counter when the counter is reset to said determined value.

15. The device of claim 11 wherein the frequency correction circuitry includes an adder coupled between the digital loop filter and the DCO, and the adder, in operation, modifies a DCO control word generated by the digital loop filter based on the determined frequency difference.

16. The device of claim 11 wherein the transmission circuitry, in operation, transmits near field communication protocol signals.

17. A system, comprising: a tag reader, which, in operation, transmits a reader carrier clock; and a tag including: a digital phase locked loop (DPLL) including a phase frequency detector, a digital loop filter, a digitally controlled oscillator (DCO) and a divider, wherein the DPLL, in operation, generates an active load modulation (ALM) carrier clock synchronized to a reader carrier clock, the DPLL having a frequency which is a multiple N of a frequency of the carrier clock of the reader, where N is an integer value; frequency correction circuitry coupled to the DPPL; and transmission circuitry, which, in operation, transmits data frames to the reader using the ALM carrier clock, wherein the frequency correction circuitry, in operation, determines a frequency difference during transmission of a data frame and generates a control signal to adjust a frequency of the DCO based on the determined frequency difference, wherein the generating the ALM carrier clock includes: between transmission of data frames, placing said DPLL in a lock mode of operation in which a feedback loop of the DPLL is closed; and within a transmitted data frame having a duration, placing, for the duration of the transmitted data frame, said DPLL in a hold mode of operation in which the feedback loop is opened; and adjusting a phase of said ALM carrier clock at least once during the duration of the transmitted data frame.

18. The system of claim 17 wherein adjusting the phase of said ALM carrier clock at least once during the duration comprises adjusting the ALM carrier clock a plurality of times within each transmitted data frame.

19. The system of claim 17 wherein the divider comprises a counter, which, in operation, divides an output of the DCO by the multiple N and outputs the ALM carrier clock, and, in operation, the counter is reset to a determined value based on a previous phase shift between the carrier clock of the reader and the ALM carrier clock of the DPLL in lock mode.

20. The system of claim 19 wherein the frequency correction circuitry, in operation, determines the frequency difference based on a difference between the determined value and an actual value of the counter when the counter is reset to said determined value.

21. The system of claim 17 wherein the frequency correction circuitry includes an adder coupled between the digital loop filter and the DCO, and the adder, in operation, modifies a DCO control word generated by the digital loop filter based on the determined frequency difference.

22. The system of claim 17 wherein the transmission circuitry, in operation, transmits near field communication protocol signals.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) FIG. 1 is a functional block diagram of an embodiment of a system including a transponder and a reader.

(2) FIG. 2 illustrates an example bit period of an ISO/IEC 14443 type B bit.

(3) FIG. 3 illustrates an example of a series of bits 1, 0, 1, 0 contained in a data signal.

(4) FIG. 4 illustrates an example of a byte of data of a data frame.

(5) FIG. 5 illustrates example bursts of an ALM carrier signal.

(6) FIG. 6 illustrates an example burst signal and a corresponding signal STXA at an antenna.

(7) FIG. 7 is a functional block diagram of an embodiment of a digital phase-locked-loop.

(8) FIG. 8 is a functional block diagram of an embodiment of a counter of a digital phase-locked-loop.

(9) FIG. 9 is a functional block diagram of an embodiment of a counter of a digital phase-locked-loop.

(10) FIGS. 10 and 11 are timing diagrams illustrating an embodiment of resetting a counter.

(11) FIGS. 12 and 13 are timing diagrams illustrating an embodiment of resetting a counter.

(12) FIG. 14 is a functional block diagram of an embodiment of a divider of a digital phase-locked-loop.

(13) FIG. 15 is a functional block diagram of an embodiment of a divider of a digital phase-locked-loop.

DETAILED DESCRIPTION

(14) In the following description, certain details are set forth in order to provide a thorough understanding of various embodiments of devices, systems, methods and articles. However, one of skill in the art will understand that other embodiments may be practiced without these details. In other instances, well-known structures and methods associated with, for example, circuits, such as transistors, multipliers, adders, dividers, comparators, integrated circuits, logic gates, finite state machines, RFID tags, RFID readers, antennas, memories, bus systems, etc., have not been shown or described in detail in some figures to avoid unnecessarily obscuring descriptions of the embodiments.

(15) Unless the context requires otherwise, throughout the specification and claims which follow, the word comprise and variations thereof, such as comprising, and comprises, are to be construed in an open, inclusive sense, that is, as including, but not limited to.

(16) Reference throughout this specification to one embodiment, or an embodiment means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases in one embodiment, or in an embodiment in various places throughout this specification are not necessarily referring to the same embodiment, or to all embodiments. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments to obtain further embodiments.

(17) The headings are provided for convenience only, and do not interpret the scope or meaning of this disclosure.

(18) The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes of various elements and angles are not drawn to scale, and some of these elements are enlarged and positioned to improve drawing legibility. Further, the particular shapes of the elements as drawn are not necessarily intended to convey any information regarding the actual shape of particular elements, and have been selected solely for ease of recognition in the drawings.

(19) On FIG. 1, which is a functional block diagram of a system 100, reference TG designates a transponder or tag configured to wireless communicate towards a reader RD reading active load modulation ALM according for example to ISO/IEC 14443 type B protocol.

(20) The transponder TG comprises transmission means (e.g., circuitry) configured to transmit frames including ALM carrier bursts to the reader RD through an antenna ANT.

(21) Said antenna comprises an inductive element L as well as one or several capacitors C.

(22) The transponder comprises a demodulation circuit 10 coupled to a decoding circuit 12 for receiving data from the reader RD through antenna ANT.

(23) The decoding circuit 12 provides data to a processing unit or circuit 13, for example a processor, a processing core, etc., which provides also data to be sent to the reader.

(24) The data may be for example application data of a NFC (Near Field Communication) application such as transaction, payment, etc.

(25) A circuit 11 extracts a clock CKR having a frequency equal to the reader carrier frequency fc, which is for example equal to 13.56 MHz in ISO/IEC 14443. The clock CKR is called reader carrier clock.

(26) The transmission means comprises encoding means (e.g., an encoder circuit) 14 configured to perform here a Binary Phase Shift Keying (BPSK) data encoding.

(27) The encoding means 14 provides to modulating means (e.g., a modulator circuit) 17 (e.g., belonging to the transmission means) a data modulating signal SD using a subcarrier (here a 847.5 KHz subcarrier).

(28) As illustrated in FIG. 2, one bit period of a bit b to be transmitted contains 8 subcarrier periods T1, which corresponds for example to ISO/IEC 14443 type B 106 kbps. In other words 8 subcarrier periods are used for a bit rate of 106 kbps (fc/128). At higher bit rates the number of subcarrier period is lower.

(29) The logical value of the bit b depends on the state high or low of the beginning of the bit period. For example, a bit period beginning with a high state and finishing with a low state may be considered as being a logical 1 whereas a bit period beginning with a low state and finishing with a high state may be considered as being a logical 0. Of course, this convention could be inverted.

(30) FIG. 3 illustrates an example of a series of bits 1, 0, 1, 0 contained in a data signal SD.

(31) Data communication between the card or tag and reader is performed using an LSB-first data format. Each byte BY of data is transmitted with a 0 start bit and a 1 stop bit as shown in FIG. 4. The stop bit, start bit, and each data bit are one elementary time unit (ETU) in length (9.439 S). ISO/IEC 14443 defines a character (a byte) as comprising a start bit, eight data bits (LSB-first, MSB-last), and a stop bit.

(32) Further each frame FR comprises before the first data byte BY, a so called Start of Frame (SOF) including at least 10 bits 0 and 2 bits 1.

(33) The modulation means 17 receive the modulating data signal SD as well as an ALM clock, called ALM carrier clock, CKALM advantageously provided by a digital phase locked loop (DPLL) circuit 16. The modulation means 17 are configured to perform a subcarrier modulation with said data encoding for generating a signal STX to antenna ANT.

(34) This signal STX comprises, as illustrated in FIG. 5, bursts BST of ALM carrier SC (said ALM carrier SC having a frequency equal here to 13.56 MHz).

(35) Two consecutive bursts BST are separated by a gap wherein no signal is transmitted from the transponder to the reader.

(36) Each half period of the subcarrier period T1 during which there is a signal transmission contains 8 periods of the carrier signal SC.

(37) The signal STX and the corresponding signal STXA at the antenna are illustrated in FIG. 6.

(38) As illustrated in this FIG. 6, each generation of ALM carrier burst BST produces after said generation, signal oscillation OSC at the antenna which can decay due to specific damping means, if any, or which can naturally decrease if for example the quality factor of the antenna is moderate, for example smaller than or equal to 8 as disclosed for example in European patent application n 17169020 mentioned above.

(39) On FIG. 6, the signal SRD present at the antenna corresponds to the reader carrier signal present on transponder antenna.

(40) If we refer now again to FIG. 3, it appears that some phase changes PCH1, PCH2, PCH3 may occur during frame transmission.

(41) Each phase change occurs when two consecutive bits having two different logical values are transmitted.

(42) Depending on the transition 1 to 0 or 0 to 1 between two bits, the phase change may occur during a gap where there is no signal transmission from the transponder as for example phase changes PCH1 and PCH3 or during a period where there is signal transmission as for example phase change PCH2.

(43) In other words, as illustrated on FIG. 5, a phase change like a phase change PCH1 occurs when no burst is generated during the half period Ta2 of the sub carrier preceding the phase change PCH1 and the half period Ta1 following this phase change.

(44) Turning now again to FIG. 1, synchronization means configured to perform synchronization between the reader carrier clock CKR and the ALM carrier clock CKALM comprises the digital phase locked loop (DPLL) 16 adapted to receive the reader carrier clock CKR and to generate the ALM carrier clock CKLM.

(45) The transponder further comprises first correction means or phase correction circuitry 18 configured to deliver a correction signal, for example a presetting value PRS to the DPLL to correct the phase of the ALM carrier clock CKALM in order to keep the variation of phase difference between the ALM carrier clock CKLM and the reader carrier clock CKR inside a target range.

(46) The transponder further comprises control means or loop control circuit 15 configured to deliver a control signal SCTRL to place outside of each transmitted frame FR, said digital phase locked loop 16 in a lock mode in which the feedback loop is closed and to place within each transmitted frame FR said digital phase locked loop in an hold mode in which the feedback loop is opened and to activate the first correction means at least one time within each transmitted frame. In an embodiment, two control signals may be employed (e.g., a control signal to control application of feedback and a control signal to activate phase correction).

(47) The control means 15 may be implemented as a software module or by a logic circuit.

(48) When the control signal SCTRL has a first logical value, the DPLL 16 is put in a hold mode in which the feedback loop is opened, inside each transmitted frame.

(49) And, outside each transmitted frame, the control signal STRL has a second logical value, in response of which the DPLL 16 is put in a lock mode closing the feedback loop for performing frequency synchronization between clocks CKR and CKALM.

(50) As illustrated in FIG. 7, the DPLL 16 comprises a time to digital converter based phase frequency detector 160 followed by a digital loop filter 161 followed by a digitally controlled oscillator (DCO) 162 followed by a feedback loop including a divider 163. The output of the divider is connected to the second entry of the time to digital converter based phase frequency detector 160.

(51) Efficient implementation (small in size) may include running of DCO at high frequency (few hundred MHz or higher). It is the reason why the divider block is here provided to generate the ALM carrier clock CKALM to be in phase with the reader carrier clock (having a frequency equal here to 13.56 MHz).

(52) The first input of the time to digital converter based phase frequency detector 160 receives the clock CKR extracted from the reader carrier signal.

(53) The DCO is controlled by a DCO control word delivered by the digital loop filter 161.

(54) When, in response to the control signal SCTRL, the DPLL is put in hold mode, the feedback loop is opened and the last DCO control word before opening the loop, is stored and used to control the DCO in the hold mode.

(55) As the DCO control is digital, the only source of frequency difference in system using DCO is difference of frequency generated by PLL system in which DCO is induced and the input carrier signal at the moment before the PLL is put on hold. DCO frequency at given control word value only drifts in case supply voltage or temperature change. These changes are negligible in time period which corresponds to duration of transponder reply (few tens of ms).

(56) Therefore, it can be supposed that the DCO frequency does not vary inside a transponder reply frame FR. As the DCO frequency does not change inside the transponder reply frame, it is thus not necessary to lock the DPLL 16 inside the transponder reply frame FR to correct the frequency. It is thus sufficient to only correct the phase of the ALM clock CKALM.

(57) In other words, DPLL only runs outside of transponder reply frame, which means that loop filter characteristic only has to be optimized for this case. Phase adjustment can also be done theoretically at least one time within the frame FR. Thus, specific damping system can be simplified or it may be in some cases not be needed at all.

(58) Practically, in order to avoid to implement a too precise DCO, an embodiment may adjust the phase several times within each transmitted frame FR.

(59) For example, a phase adjustment may be performed between each burst BST or at each phase changes of the PCH1 or PCH3 type (FIG. 3) or, at each phase change PCH1.

(60) According to the embodiment disclosed on FIG. 7, the divider 163 is provided with a new input which is adapted to receive the presetting value PRS in order to reset the state of the divider to this presetting value.

(61) As the generated ALM clock is not exactly the same as reader carrier clock, the phase difference between the two signals drifts in time. In order to keep phase drift inside the specified limits, the phase is corrected by presetting the divider at least one time inside each transmitted frame FR. Granularity of such phase adjustment is defined by ratio between DCO frequency and reader carrier frequency. To simplify the divider this ratio may be set to be an integer value. This defines granularity of phase adjustment to be 360/n. This granularity is an additional contribution to phase variation and has to be taken in account. If for example the DCO frequency is set to 64 times transponder carrier frequency, one divider count corresponds to 360/64 (5.625), which is also granularity of phase adjustment system. This is variation of phase due to granularity of phase adjustment system.

(62) To resume, the DPLL 16 operates in the following way: DPLL only runs outside of transponder reply frame where the reader carrier clock is always present on DPLL input. Before start of transponder reply frame the DPLL feedback loop is put on hold, the value of DCO control word on output of digital loop filter is stored and used to define DCO frequency during complete transponder reply frame. Inside transponder reply frame the phase of generated ALM clock CKALM is occasionally corrected by resetting the divider with the presetting value PRS.

(63) According to an embodiment illustrated in FIG. 8, the divider 163 comprises a counter 1630 configured to receive the oscillator signal outputted by the DCO and to perform division by N (here N=64) for outputting said ALM carrier clock CKALM.

(64) Generally speaking the first correction means 18 are configured to control a parameter of said divider, here by resetting the counter 1630 to the presetting value PRS, in presence of a reset pulse RSP.

(65) As illustrated in FIG. 9, the counter 1630 comprises several flip-flops, the last flip-flop delivering the clock CKALM.

(66) And, the presetting value PRS is here a digital word, stored for example in a register of said first correction means, adapted to reset the several flip-flops in order to give to the counter 1630 said presetting value.

(67) Generally speaking, the presetting value corresponds to a phase shift between the reader carrier clock CKR and the outputted ALM clock CKLALM when the digital phase locked loop 16 is in its locked mode.

(68) More precisely, FIGS. 10 and 11 illustrate a first example of resetting the counter 1630 with a presetting value.

(69) FIG. 10 illustrates diagrammatically the temporal evolutions of the clock CKR, the clock CKALM and the counter values of the counter 1630 when the DPLL is in its locked mode and when there is no phase shift between the signals CKR and CKALM in the locked mode.

(70) FIG. 11 illustrates the temporal evolutions of the same signals CKR and CKALM as well as the counter values when the DPLL is in its hold mode.

(71) In this example, at one time, the phase difference between the two signals CKR and CKALM is equal to N periods of the digitally controlled oscillator. Thus, when the counter is reset in response to the reset pulse RSP, the presetting value is equal to 0 because in this embodiment, there is no phase shift between the clock CKR and the clock CKALM in the locked mode of the DPLL.

(72) After this phase adjustment, the signal CKALM and the signal CKR are again aligned and IFS synchronization has been performed.

(73) FIGS. 12 and 13 illustrate the case where there is a phase shift of 10 periods of the oscillator signal delivered by the digitally controlled oscillator between the clock CKR and the clock CKALM in the lock mode of the DPLL 16.

(74) Thus, as illustrated in FIG. 13, when the DPLL is in its hold mode, the counter is reset to the presetting value equal to 64-10 in response to the reset pulse RSP in order to obtain again a phase shift of 10 periods of the oscillator signal between clock CKR and clock CKALM.

(75) In the embodiment disclosed in FIG. 14, the divider 163 comprises a Johnson counter configured to perform division by N (here division by 64) and to deliver several output signals having different phases PH0-PHn.

(76) And, the first correction means or phase correction circuit 18 are configured to correct the phase of the ALM carrier clock CKALM by selecting the output signal having a phase which is the closest of a desired phase corresponding to the phase shift between the reader carrier clock and the outputted ALM clock when the DPLL is in its lock mode.

(77) More precisely, in this example, if we assume that we had a phase shift between the signal CKR and CKALM equal to 10 periods of the oscillator signal when the DPLL was in its lock mode, the first correction means will send an adjustment signal PHJ in order to select the tenth phase PH9.

(78) By adding a digital processing block it is additionally possible to reduce the difference between generated ALM clock and reader carrier clock frequencies inside a transmitted frame FR without locking the DPLL loop. This can be done by observing the difference between the divider presetting value and the actual state of divider at the moment where the reset pulse is emitted (e.g., at the moment where the reset is done with the presetting value). This difference provides information about the phase error which was accumulated in time period between two synchronization time points from which difference of the two frequencies can be calculated. Information about calculated frequency difference can be then used to correct the DCO frequency.

(79) FIG. 15 depicts system shown on FIG. 7 to which possibility to correct DCO frequency inside transmitted frame FR was added.

(80) Second correction means are provided comprising determination means or frequency correction circuitry 1800 configured to determine the difference between the presetting value PRS and the actual value of the counter when the counter is reset to said resetting value, and to determine from said difference a frequency difference.

(81) Said second correction means are configured to use said frequency difference for correcting the frequency of the digitally controlled oscillator 162.

(82) As illustrated, an adder 1801 is provided for adding the frequency difference to DCO control word which is output from digital loop filter 161.

(83) The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.

(84) These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.