Apparatus for generating high pulse voltage

Abstract

Apparatus for generating high pulse voltage comprises a high DC voltage source, a low DC voltage source, an inductive load, two controllable gates, a controllable switch and, connected in series, a capacitor, a booster diode and an additional controllable switch, as well as a controllable pulse duration converter for pulses from a rectangular pulse generator. The preceding connection of the booster diode anode with the negative terminal of the low DC voltage source ensured by the pulse duration converter and second controllable switch correlates the booster diode switching time with the moment of closing the both controllable gates. Thus, the pulse noise present in the prior art designs is eliminated, and the level of interference emitted into the surroundings is decreased.

Claims

1. An apparatus for generating high pulse voltage, the apparatus comprising: a high DC voltage source (HDCVS); a first capacitor connected by a first plate thereof to a positive terminal of the HDCVS and connected by a second plate thereof to a negative terminal of the HDCVS; a first controllable gate connected by a first terminal thereof to the positive terminal of the HDCVS; an inductive load connected by a first terminal thereof to a second terminal of the first controllable gate; a second controllable gate connected by a first terminal thereof to a second terminal of the inductive load; a limiting resistor connected by one terminal thereof to a second terminal of the second controllable gate and connected by another terminal thereof to the negative terminal of the HDCVS; a low DC voltage source (LDCVS) connected by a negative terminal thereof to the negative terminal of the HDCVS; a square wave generator connected by an output thereof to a control input of the second controllable gate and connected by power inputs thereof to respective terminals of the LDCVS; a first diode; a second capacitor connected by a first plate thereof to a cathode of the first diode and connected by a second plate thereof to the second terminal of the first controllable gate; a second diode connected by a cathode thereof to the first terminal of the inductive load and connected by an anode thereof to the negative terminal of the HDCVS; a third diode connected by an anode thereof to the second terminal of the inductive load and connected by a cathode thereof to the positive terminal of the HDCVS; a controllable switch connected by a first input thereof to the first plate of the second capacitor, connected by a second input thereof to the second plate of the second capacitor, connected by an output thereof to a control input of the first controllable gate, and connected by a control input thereof to the output of the square wave generator, the apparatus further comprising a second controllable switch and a square pulse duration converter, the converter being connected by an input thereof to the output of the square wave generator and connected by an output thereof to a control input of the second controllable switch connected by a first input thereof to the negative terminal of the LDCVS, connected by a second input thereof to the positive terminal of the LDCVS and connected by an output thereof to an anode of the first diode.

2. The apparatus according to claim 1, wherein the connection between the output of the square wave generator and the control input of the second controllable gate is made via a buffer matching stage.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) The proposed apparatus for generating high pulse voltage explained in the ensuing description and drawings where

(2) FIG. 1 shows a functional diagram of the apparatus and

(3) FIG. 2 presents voltage charts illustrating the operation of the apparatus.

DETAILED DESCRIPTION

(4) The proposed apparatus for generating high pulse voltage comprises: an HDCVS 1; a first (storage) capacitor 2 connected by one (first) plate 3 thereof to a positive terminal 4 of the HDCVS 1 and connected by another (second) plate 5 thereof to a negative terminal 6 of the HDCVS 1; a first controllable gate 7 (including, for example, a MOS-transistor) connected by a first terminal 8 (drain of the MOS-transistor) thereof to the positive terminal 4 of the HDCVS 1; an inductive load 9 connected by one (first) terminal 10 thereof to a second terminal 11 (source of the MOS-transistor) of the first controllable gate 7; a second controllable gate 12 (including, for example, a MOS-transistor) connected by a first terminal 13 (drain of the MOS-transistor) thereof to a second terminal 14 of the inductive load 9; a limiting resistor 15 connected by one terminal 16 thereof to another terminal 17 (source of the MOS-transistor) of the second controllable gate 12 and connected by another terminal 18 thereof to the negative terminal 6 of the HDCVS 1; a LDCVS 19 connected by a negative terminal 20 thereof to the negative terminal 6 of the HDCVS 1; a square wave generator 21 connected by an output 22 thereof to an input 23 of a buffer matching stage 24, an output 25 of the stage 24 being connected to a control input 26 (gate of the MOS-transistor) of the second controllable gate 12, power inputs 27 and 28 of the square wave generator 21 being connected to output terminals 29 and 20 of the LDCVS 19, respectively; a first (booster) diode 30; a second (booster) capacitor 31 connected by a first plate 32 thereof to a cathode 33 of the first diode 30 and connected by a second plate 34 thereof to the second terminal 11 of the first controllable gate 7; a second (first pick-off) diode 35 connected by a cathode 36 thereof to the first terminal 10 of the inductive load 9 and connected by an anode 37 thereof to the negative terminal 6 of the HDCVS 1; a third (second pick-off) diode 38 connected by an anode 39 thereof to the second terminal 14 of the inductive load 9 and connected by a cathode 40 thereof to the positive terminal 4 of the HDCVS 1; a first (main) controllable switch 41 connected by a first input 42 thereof to the first plate 32 of the second capacitor 31, connected by a second input 43 thereof to the second plate 34 of the second capacitor 31, connected by an output 44 to a control input (gate of the MOS-transistor) 45 of the first controllable gate 7, and connected by a control input 46 thereof to the output 22 of the square wave generator 21; a second (additional) controllable switch 47 connected by one (first) input 48 thereof to the negative terminal 20 of the LDCVS 19, connected by a second input 51 thereof to the positive terminal 29 of the LDCVS 19, and connected by an output 49 thereof to an anode 50 of the first diode 30; a square pulse duration converter 52 connected by an input 53 thereof to the output 22 of the square wave generator 21, connected by an output 54 thereof to a control input 55 of the second (additional) controllable switch 47, and connected by power inputs 56, 57 to respective outputs 29, 20 of the LDCVS 19.

(5) The charts of FIG. 2 of voltage acting in the apparatus illustrate:

(6) (a)constant voltage U.sub.0 of the HDCVS 1;

(7) (b)control square pulses of preset duration .sub.p and a pulse-repetition period of T at the output 22 of the square wave generator 21;

(8) (c)control square pulses at the input 26 (at the gate of the MOS-transistor) of the second controlled gate 12;

(9) (d)pulse voltage at the second terminal 11 of the first controlled gate 7 (at the MOS-transistor source);

(10) (e)pulse voltage at the first terminal 13 of the second controlled gate 12 (at the MOS-transistor drain);

(11) (f)converted (additional) square pulses of duration .sub.conv at the output 54 of the square pulse duration converter 52, >.sub.diode where a duration of the protective time interval ensuring preceding connection of the anode 50 of the diode 30 to the negative terminal 20 of the LDCVS 19, and .sub.diode is a switching time of the high voltage diode 30;

(12) (g)succession of states (diode on.sub.diode (diode switching time)diode off) of the first diode 30.

(13) Chart (g) also shows conventionally a moment of pulse noise potential generation, present in prior art and absent in proposed design.

(14) The proposed apparatus for generating high pulse voltage operates as follows.

(15) Subject to having DC voltage at the power inputs 27, 28 of the square wave generator 21 which comes from the terminals 29, 20 of the LDCVS 19, the square wave generator 21 produces square pulses of duration .sub.p and period of T (FIG. 2b).

(16) Then, square pulses of duration .sub.p pass from the output 22 of the generator 21 via the buffer matching stage 24 (input 23 and output 25) to the control input 26 of the second controlled gate 12 (to the MOS-transistor gate) (FIG. 2c) which results in closing the second controllable gate 12.

(17) Simultaneously, square pulses of duration .sub.p pass from the output 22 of the generator 21 to the control input 46 of first controlled switch 41. As a result, potential, exceeding potential of the second terminal 11 of the first controllable gate 7 (the source of the MOS-transistor) by value almost equal to output voltage of the LDCVS 19, passes to the control input 45 of the first controllable gate 7 (the gate of the MOS-transistor thereof) from the second (booster) capacitor 31.

(18) Arrival of this potential closes the first controllable gate 7 almost simultaneously with the second controllable gate 12 (chart 2d) causing current to flow through the inductive load 9 along the circuit: the positive terminal 4 of the HDCVS 1the closed first controllable gate 7the inductive load 9the closed second controllable gate 12the limiting resistor 15the negative terminal 6 of the HDCVS 1.

(19) Closing the both controllable gates 7 and 12 causes potential of the first terminal 10 of the inductive load 9 to become almost equal to potential of the positive terminal 4 of the HDCVS 1 (because resistance of the closed first controllable gate 7 is negligible, and voltage drop thereon is also negligible) and causes potential of the second terminal 14 of the inductive load 9 to become almost equal to potential of the negative terminal 6 of the HDCVS 1 (because resistance of the closed second controllable gate 12 and the limiting resistor 15 is negligible, and voltage drop thereon is also negligible). Accordingly, potential difference between the terminals 10 and 14 of the inductive load 9 becomes close to output voltage of the HDCVS 1. At that moment, energy storing takes place in the inductive load (forward stroke, FIG. 2c).

(20) After completion of square pulse of duration .sub.p passing to the control input 45 of the first controlled gate 7 (to the gate of the MOS-transistor thereof) and, via the buffer matching stage 24, to the control input 26 of the second controlled gate 12 (to the gate of the MOS-transistor thereof), the both controllable gates 7 and 12 switch to open state (back stroke, FIG. 2c). At this moment, potential difference between the terminals 10 and 14 of the inductive load 9 changes sign thereof, pulse voltage emerges at the first terminal 13 of the second controlled gate 12 (at the drain of the MOS-transistor, FIG. 2e), self-induced emf emerges in the inductive load 9, and stored energy is passed to effective load (not shown). In this way, DC voltage of the HDCVS 1 (FIG. 2a) is converted into high pulse voltage.

(21) Upon opening the first, 7, and second, 12, controllable gates, high voltage emerges between the terminals 10 and 14 of the inductive load 9 because of self-induced emf. As soon as this high voltage exceeds output voltage of the HDCVS 1, the second diode (first pick-off) 35 and the third (second pick-off) diode 38 open, and current starts flowing through them in the following circuit: the negative terminal 6 of the HDCVS 1the second (first pick-off) diode 35the inductive load 9the third (second pick-off) diode 38the first (storage) capacitor 2the negative terminal 6 of the HDCVS 1. Consequently, in addition to energy delivery to effective load, storing energy in the storage capacitor 2 takes place (contributing to enhancing efficiency of both proposed design and the design-prototype which also uses this technique).

(22) In addition to ensuring closing the both controllable gates 7 and 12, square pulses of duration .sub.p from the output 22 of the square wave generator 21 also arrive at the control input 53 of the square pulse duration converter 52. At the output 54 thereof, a converted additional square pulse of duration .sub.conv appears (FIG. 20 passing to the control input 55 of the second (additional) controlled switch 47.

(23) Pulse of duration .sub.conv causes coupling the output 49 (connected to the anode 50 of the first diode 30) of the second (additional) switch 47 to the second input 51 thereof (connected to the positive terminal 29 of the LDCVS 19). As a result, voltage close by value to output voltage of the LDCVS 19 emerges between the plates 32 and 34 of the second, booster, capacitor 31.

(24) When the HDCVS 1 and LDCVS 19 are initially turned on, the second, booster, capacitor 31 is discharged, the first controllable gate 7 is permanently open, and the second controllable gate 12 is periodically closed by square pulses of duration .sub.p coming to the control input 26 thereof from the output 22 of the square wave generator 21 via the buffer matching stage 24. In this mode, current charging the second, booster, capacitor 31 flows in the circuit: the positive terminal 29 of the LDCVS 19the second controllable switch 47the first, booster, diode 30the second, booster, capacitor 31the inductive load 9the closed second controllable gate 12the limiting resistor 15the negative terminal 20 of the LDCVS 19.

(25) On the other hand, in steady-state operation (where the both controllable gates 7 and 12 are almost simultaneously closed when main square pulse of duration .sub.p acts and are open when it is absent), recharging of the second, boost, capacitor 31 and, hence, voltage recovery between the plates 32 and 34 thereof takes place. This process occurs during back stroke (FIG. 2c) due to current charging the second, booster, capacitor 31 in the circuit: the positive terminal 29 of the LDCVS 19the second controllable switch 47the first, booster, diode 30the second, booster, capacitor 31the first pick-off diode 35 (said earlier to be open during back stroke)the negative terminal 20 of the LDCVS 19. That way, the second, booster, capacitor in steady-state operation recharges time after time up to voltage close to output voltage of the LDCVS 19, thus enabling closing the first controllable gate 7 in the next period T as described earlier.

(26) After completion of control pulse of duration .sub.conv (FIG. 2f) at the control input 55 of the second, additional, switch 47, the latter connects the first input 48 thereof (connected to the negative terminal 20 of the LDCVS 19) to the output 49 thereof (connected to the anode 50 of the first, booster, diode 30).

(27) The first, booster, diode 30 becomes, therefore, non-conductive because potential of the second plate 34 of the second, booster, capacitor 31 at that time is close to potential of the negative terminal 20 of the LDCVS 19. Voltage between the plates 32 and 34 thereof is about output voltage of the LDCVS 19, i.e. voltage close to output voltage of the LDCVS 19 is applied to the cathode 33 of the first, booster, diode 30, whereas the anode 50 thereof turns out to be connected to the negative terminal 20 of the LDCVS 19, which means that the diode is connected reversely. Because of transit time of the first, booster, diode 30, it becomes non-conductive during time interval of .sub.diode (FIG. 2g).

(28) In the proposed apparatus for generating high pulse voltage, therefore, no in-rush current emerges through the incompletely closed first, booster, diode 30 when high voltage appears in the inductive load 9. In prior art designs of similar use, this in-rush current shows itself.

(29) Therefore, the proposed design fulfils same functions as the design-prototype having advantage of it in decreased level of noise radiated into surrounding environment.

(30) Functional units composing the apparatus can be implemented in different ways.

(31) Used for the square wave generator 21, for example, can be a chip acting as PW modulator, such as A7985A, or PF modulator, such as FAN-6300H, etc.

(32) For both, or each of, transistors of the first and second controllable gates 7 and 12, MOS-transistors or IGBT can be used, and gate itself can comprise additional technique improving operational quality thereof.

(33) The inductive load 9 including a winding on a core can be either a primary winding of a transformer with a rectifier connected to a secondary winding thereof, or a coil of an electromagnet converting pulses in an inductive load into armature travel, or any other inductance delivering power to a terminal unit.

(34) The pick-off diodes 35, 38 can include any unilateral conductivity device such as MOS-transistors, IGBT, etc.

(35) The buffer stage 24, meant to match moments of feeding control pulses to the inputs of the first, 7, and second, 12, controllable gates, can include, for example, a delay element and an amplifier connected in series, or can be absent at all.

(36) All other units composing the apparatus for generating high pulse voltage are well known in the art and described in public sources relating to pulse technique and radioelectronics.