Dual-series varactor EPI

Abstract

A semiconductor device includes a first varactor diode and a second varactor diode. The second varactor diode is coupled in series with the first varactor diode and vertically disposed over the first varactor diode. By vertically disposing the second varactor diode over the first varactor diode, the space occupied by the pair of varactor diodes can be significantly reduced.

Claims

1. A semiconductor device comprising: a first varactor diode comprising a first plurality of epitaxial layers, wherein the first plurality of epitaxial layers comprises: a first anode contact layer; a first anode layer over the first anode contact layer; a first varactor layer over the first anode layer; and a first cathode contact layer over the first varactor layer; and a second varactor diode coupled in series with the first varactor diode and comprising a second plurality of epitaxial layers, which are over the first plurality of epitaxial layers, wherein the second plurality of epitaxial layers comprises: a second anode contact layer over the first cathode contact layer; a second anode layer over the second anode contact layer; a second varactor layer over the second anode layer; and a second cathode contact layer over the second varactor layer.

2. The semiconductor device of claim 1 wherein the first varactor diode further comprises: an anode contact on the first anode contact layer; and a cathode contact on the first cathode contact layer.

3. The semiconductor device of claim 2 wherein the second varactor diode further comprises: an anode contact on the second anode contact layer; and a cathode contact on the second cathode contact layer.

4. The semiconductor device of claim 3 further comprising a metallization layer connecting the cathode contact of the first varactor diode to the anode contact of the second varactor diode.

5. The semiconductor device of claim 3 further comprising: a first etch stop layer between the first anode contact layer and the first anode layer; a second etch stop layer between the first cathode contact layer and the second anode contact layer; and a third etch stop layer between the second anode contact layer and the second anode layer.

6. The semiconductor device of claim 5 wherein: the first anode contact layer forms a first mesa; the first etch stop layer, the first anode layer, the first varactor layer, and the first cathode contact layer form a second mesa over the first mesa; the second etch stop layer and the second anode contact layer form a third mesa over the second mesa; and the third etch stop layer, the second anode layer, the second varactor layer, and the second cathode contact layer form a fourth mesa over the third mesa.

7. The semiconductor device of claim 6 wherein: the anode contact of the first varactor diode is an ohmic contact on the first mesa; the cathode contact of the first varactor diode is an ohmic contact on the second mesa; the anode contact of the second varactor diode is an ohmic contact on the third mesa; and the cathode contact of the second varactor diode is an ohmic contact on the fourth mesa.

8. The semiconductor device of claim 5 wherein: the first anode contact layer, the first anode layer, the first varactor layer, the first cathode contact layer, the second anode contact layer, the second anode layer, the second varactor layer, and the second cathode contact layer comprise gallium arsenide; and the first etch stop layer, the second etch stop layer, and the third etch stop layer comprise one of aluminum gallium arsenide and indium gallium phosphide.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

(2) FIGS. 1A and 1B show a single varactor diode.

(3) FIG. 2 shows a number of varactor diodes stacked in an alternating-polarity configuration.

(4) FIG. 3 shows a number of varactor diodes connected in series.

(5) FIG. 4 shows the physical layout of a number of varactor diodes coupled in series.

(6) FIG. 5 shows a dual-stack varactor according to one embodiment of the present disclosure.

(7) FIG. 6 shows a dual-stack varactor according to an additional embodiment of the present disclosure.

(8) FIG. 7 is a flow diagram illustrating a method for manufacturing an epitaxial stack for a dual-stack varactor according to one embodiment of the present disclosure.

(9) FIG. 8 is a flow diagram illustrating a method for manufacturing a dual-stack varactor from an epitaxial stack as shown in FIG. 7 according to one embodiment of the present disclosure.

DETAILED DESCRIPTION

(10) The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

(11) FIG. 5 shows a dual-stack varactor 14 according to one embodiment of the present disclosure. The dual-stack varactor 14 includes a first cathode contact layer 16, a first etch stop layer 18 over the first cathode contact layer 16, a first cathode layer 20 over the first etch stop layer 18, a first varactor layer 22 over the first cathode layer 20, a first anode contact layer 24 over the first varactor layer 22, a second etch stop layer 26 over the first anode contact layer 24, a second cathode contact layer 28 over the second etch stop layer 26, a third etch stop layer 30 over the second cathode contact layer 28, a second cathode layer 32 over the third etch stop layer 30, a second varactor layer 34 over the second cathode layer 32, and a second anode contact layer 36 over the second varactor layer 34.

(12) The dual-stack varactor 14 is formed as a number of different mesas in order to allow contacts to be placed on the various layers therein. The first cathode contact layer 16 forms a first mesa 38 on top of which a first ohmic contact 40, which may be separated into a pair of ohmic contacts, is located. The first ohmic contact(s) 40 effectively forms a cathode contact of a first varactor diode in the dual-stack varactor 14. The first etch stop layer 18, the first cathode layer 20, the first varactor layer 22, and the first anode contact layer 24 form a second mesa 42 on top of which a second ohmic contact 44, which may be separated into a pair of ohmic contacts, is located. The second ohmic contact(s) 44 effectively form an anode contact of the first varactor diode in the dual-stack varactor 14. The second etch stop layer 26 and the second cathode contact layer 28 form a third mesa 46 on top of which a third ohmic contact 48, which may be separated into a pair of ohmic contacts, is located. The third ohmic contact(s) 48 effectively form a cathode contact of a second varactor diode in the dual-stack varactor 14. Finally, the third etch stop layer 30, the second cathode layer 32, the second varactor layer 34, and the second anode contact layer 36 form a fourth mesa 50 on top of which a fourth ohmic contact 52 is located. The fourth ohmic contact 52 effectively forms an anode contact of the second varactor diode in the dual-stack varactor 14. A metallization layer 54 connects the second ohmic contact(s) 44 to the third ohmic contact(s) 48. Accordingly, a pair of series-connected varactor diodes are formed between the first ohmic contact(s) 40 and the fourth ohmic contact 52.

(13) Due to the fact that two varactor diodes 10 are vertically disposed in the dual-stack varactor 14 with a footprint that is comparable to a single-stack varactor, the number of varactor diodes per unit area can effectively be doubled when using the dual-stack varactor 14. Accordingly, significant reductions in the size of circuitry such as that shown in FIGS. 2 and 3 can be achieved. Such size reductions may result in similar reductions in the cost of the circuitry.

(14) In one embodiment, the first cathode contact layer 16 is a heavily doped p-layer with a thickness between about 0.4 m and 2.0 m and a doping concentration between about 110.sup.19 cm.sup.3 and 410.sup.19 cm.sup.3. The first etch stop layer 18 may be a heavily doped p-layer with a thickness between about 0.005 m and 0.03 m and a doping concentration between about 110.sup.19 cm.sup.3 and 410.sup.19 cm.sup.3. The first cathode layer 20 may be a heavily doped p-layer with a thickness between about 0.05 m and 0.2 m and a doping concentration between about 110.sup.19 cm.sup.3 and 410.sup.19 cm.sup.3. The first varactor layer 22 may be a lightly doped n-layer with a thickness between about 0.5 m and 2.0 m and a doping concentration between about 110.sup.15 cm.sup.3 and 110.sup.17 cm.sup.3. The first anode contact layer 24 may be a heavily doped n-layer with a thickness between about 0.1 m and 0.5 m and a doping concentration between about 110.sup.18 cm.sup.3 and 510.sup.18 cm.sup.3. The second etch stop layer 26 may be a n+ layer with a thickness between about 0.005 m and 0.03 m and a doping concentration between about 110.sup.18 cm.sup.3 and 510.sup.18 cm.sup.3. The second cathode contact layer 28 may be a heavily-doped p-layer with a thickness between about 0.05 m and 0.2 m and a doping concentration between about 110.sup.19 cm.sup.3 and 410.sup.19 cm.sup.3. The third etch stop layer 30 may be a heavily-doped p-layer with a thickness between about 0.005 m and 0.03 m and a doping concentration between about 110.sup.19 cm.sup.3 and 410.sup.19 cm.sup.3. The second cathode layer 32 may be a heavily doped p-layer with a thickness between about 0.05 m and 0.2 m and a doping concentration between about 110.sup.19 cm.sup.3 and 410.sup.19 cm.sup.3. The second varactor layer 34 may be a lightly-doped n-layer with a thickness between about 0.5 m and 2.0 m and a doping concentration between about 110.sup.15 cm.sup.3 and 110.sup.17 cm.sup.3. The second anode contact layer 36 may be a heavily-doped n-layer with a thickness between about 0.05 m and 0.2 m and a doping concentration between about 110.sup.18 cm.sup.3 and 510.sup.18 cm.sup.3. The n-dopants used in the n-layers described above may include silicon (Si), tellurium (Te), or the like. The p-dopants used in the p-layers described above may include carbon (C), beryllium (Be), zinc (Zn), or the like. Notably, the foregoing thicknesses and doping concentration for the various layers in the dual-stack varactor 14 are merely illustrative. Any number of suitable thicknesses or doping concentrations may be used for the layers in the dual-stack varactor 14 without departing from the principles of the present disclosure.

(15) In one embodiment, the first cathode contact layer 16, the first cathode layer 20, the varactor layer 22, the first anode contact layer 24, the second cathode contact layer 28, the second cathode layer 32, the second varactor layer 34, and the second anode contact layer 36 are all gallium arsenide (GaAs). The first etch stop layer 18, the second etch stop layer 26, and the third etch stop layer 30 may be aluminum gallium arsenide (AlGaAs) or indium gallium arsenide (InGaAs). The first ohmic contact(s) 40 may comprise titanium-platinum-gold (TiPtAu). The second ohmic contact(s) 44 may comprise gold-germanium-nickel-gold (AuGeNiAu). The third ohmic contact(s) 48 may comprise titanium-plantium-gold (TiPtAu). The fourth ohmic contact 52 may comprise titanium-tungsten (TiW). Finally, the metallization layer 54 may comprise titanium/gold (Ti/Au). Notably, the foregoing materials for the dual-stack varactor 14 are merely illustrative, and any number of different materials may be used for the various layers without departing from the principles of the present disclosure.

(16) FIG. 6 shows a dual-stack varactor 56 according to an additional embodiment of the present disclosure. The dual-stack varactor 56 shown in FIG. 6 is substantially similar to that shown in FIG. 5, except that the varactor diodes in the dual-stack varactor 56 are reversed. Accordingly, the dual-stack varactor 56 includes a first anode contact layer 58, a first etch stop layer 60 over the first anode contact layer 58, a first anode layer 62, a first varactor layer 64 over the first anode layer 62, a first cathode contact layer 66 over the first varactor layer 64, a second etch stop layer 68 over the first cathode contact layer 66, a second anode contact layer 70 over the second etch stop layer 68, a third etch stop layer 72 over the second anode contact layer 70, a second anode layer 74 over the third etch stop layer 72, a second varactor layer 76 over the second anode layer 74, and a second cathode contact layer 78 over the second varactor layer 76.

(17) The dual-stack varactor 56 is formed as a number of different mesas in order to allow contacts to be placed on the various layers therein. The first anode contact layer 58 forms a first mesa 80 on top of which a first ohmic contact 82, which may be separated into a pair of ohmic contacts, is located. The first ohmic contact(s) 82 effectively forms an anode contact of a first varactor diode in the dual-stack varactor 56. The first etch stop layer 60, the first anode layer 62, the first varactor layer 64, and the first cathode contact layer 66 form a second mesa 84 on top of which a second ohmic contact 86, which may be separated into a pair of ohmic contacts, is located. The second ohmic contact(s) 86 effectively forms a cathode contact of the first varactor diode. The second etch stop layer 68 and the second anode contact layer 70 form a third mesa 88 on top of which a third ohmic contact 90, which may be separated into a pair of ohmic contacts, is located. The third ohmic contact(s) 90 effectively forms an anode contact of a second varactor diode in the dual-stack varactor 56. The third etch stop layer 72, the second anode layer 74, the second varactor layer 76, and the second cathode contact layer 78 form a fourth mesa 92 on top of which a fourth ohmic contact 94 is located. The fourth ohmic contact 94 effectively forms a cathode contact of the second varactor diode. A metallization layer 96 connects the second ohmic contact(s) 86 to the third ohmic contact(s) 90. Accordingly, a pair of series-connected varactor diodes are formed between the first ohmic contact(s) 82 and the fourth ohmic contact 94.

(18) Due to the fact that two varactor diodes are vertically disposed in the dual-stack varactor 56 with a footprint that is comparable to a single-stack varactor, the number of varactor diodes per unit area can effectively be doubled when using the dual-stack varactor 56. Accordingly, significant reductions in the size of circuitry such as that shown in FIGS. 2 and 3 can be achieved. Such size reductions may result in similar reductions in the cost of the circuitry.

(19) In one embodiment, the first anode contact layer 58 is a heavily doped n-layer with a thickness between about 0.4 m and 2.0 m and a doping concentration between about 110.sup.18 cm.sup.3 and 510.sup.18 cm.sup.3. The first etch stop layer 60 may be a heavily doped n-layer with a thickness between about 0.005 m and 0.03 m and a doping concentration between about 110.sup.18 cm.sup.3 and 510.sup.18 cm.sup.3. The first anode layer 62 may be a heavily doped n-layer with a thickness between about 0.05 m and 0.2 m and a doping concentration between about 110.sup.18 cm.sup.3 and 510.sup.18 cm.sup.3. The first varactor layer 64 may be a lightly doped n-layer with a thickness between about 0.5 m and 2.0 m and a doping concentration between about 110.sup.15 cm.sup.3 and 110.sup.17 cm.sup.3. The first cathode contact layer 66 may be a heavily doped p-layer with a thickness between about 0.05 m and 0.2 m and a doping concentration between about 110.sup.19 cm.sup.3 and 410.sup.19 cm.sup.3. The second etch stop layer 68 may be a p+ layer with a thickness between about 0.005 m and 0.03 m and a doping concentration between about 110.sup.19 cm.sup.3 and 410.sup.19 cm.sup.3. The second anode contact layer 70 may be a heavily doped n-layer with a thickness between about 0.05 m and 0.5 m and a doping concentration between about 110.sup.18 cm.sup.3 and 510.sup.18 cm.sup.3. The third etch stop layer 72 may be a heavily doped n-layer with a thickness between about 0.005 m and 0.03 m and a doping concentration between about 110.sup.18 cm.sup.3 and 510.sup.18 cm.sup.3. The second anode layer 74 may be a heavily doped n-layer with a thickness between about 0.05 m and 0.2 m and a doping concentration between about 110.sup.18 cm.sup.3 and 510.sup.18 cm.sup.3. The second varactor layer 76 may be a lightly doped n-layer with a thickness between about 0.5 m and 2.0 m and a doping concentration between about 110.sup.15 cm.sup.3 and 110.sup.17 cm.sup.3. Finally, the second cathode contact layer 78 may be a heavily doped p-layer with a thickness between about 0.05 m and 0.2 um and a doping concentration between about 110.sup.19 cm.sup.3 and 410.sup.19 cm.sup.3. Notably, the foregoing thicknesses and doping concentrations for the various layers in the dual stack varactor 56 are merely illustrative. Any number of suitable thicknesses or doping concentrations may be used for the layers in the dual-stack varactor 56 without departing from the principles of the present disclosure.

(20) In one embodiment, the first anode contact layer 58, the first anode layer 62, the first varactor layer 64, the first cathode contact layer 66, the second anode contact layer 70, the second anode layer 74, the second varactor layer 76, and the second cathode contact layer comprise gallium arsenide (GaAs). The first etch stop layer 60, the second etch stop layer 68, and the third etch stop layer 72 may be aluminum gallium arsenide (AlGaAs) or indium gallium arsenide (InGaAs). The first ohmic contact(s) 82 may comprise gold-germanium-nickel-gold (AuGeNiAu). The second ohmic contact(s) 86 may comprise titanium-platinum-gold (TiPtAu). The third ohmic contact(s) 90 may comprise gold-germanium-nickel-gold (AuGeNiAu). The fourth ohmic contact 94 may comprise titanium-tungsten (TiW). Notably, the foregoing materials for the dual-stack varactor 56 are merely illustrative, and any number of different materials may be used for the various layers without departing from the principles of the present disclosure.

(21) While FIGS. 5 and 6 illustrate only two varactor diodes vertically stacked with respect to one another, the principles of the present disclosure may be used to stack any number of varactor diodes on top of one another.

(22) FIG. 7 is a flow diagram illustrating a method for manufacturing the epitaxial stack making up the dual-stack varactor 14 shown in FIG. 5. The epitaxial stack of the dual stack varactor 56 shown in FIG. 6 may be made by a similar process. First, the first anode contact layer 16 is provided (step 100). The first etch stop layer 18 is provided over the first anode contact layer 16 (step 102). The first cathode layer 20 is provided over the first etch stop layer 18 (step 104). The first varactor layer 22 is provided over the first cathode layer 20 (step 106). The first anode contact layer 24 is provided over the first varactor layer 22 (step 108). The second etch stop layer 26 is provided over the first anode contact layer 24 (step 110). The second cathode contact layer 28 is provided over the second etch stop layer 26 (step 112). The third etch stop layer 30 is provided over the second cathode contact layer 28 (step 114). The second cathode layer 32 is provided over the third etch stop layer 30 (step 116). The second varactor layer 34 is provided over the second cathode layer 32 (step 118). The second anode contact layer 36 is provided over the second varactor layer (step 120). Any suitable epitaxial growth or deposition process may be used to provide the layers as described above without departing from the principles of the present disclosure.

(23) FIG. 8 is a flow diagram illustrating a method for constructing the dual-stack varactor 14 discussed above with respect to FIG. 5 from the epitaxial stack described above with respect to FIG. 7. A similar process may be used to construct the dual-stack varactor 56 shown in FIG. 6. First, the fourth ohmic contact 52 is provided on the second anode contact layer 36 (step 200). The fourth ohmic contact 52, the second anode contact layer 36, the second varactor layer 34, and the second cathode layer 32 are then selectively etched using any number of masking and etching processes (step 202). Notably, the material of the third etch stop layer 30 is not compatible with the etching process used in step 202, and therefore the etching process does not affect the third etch stop layer 30. Accordingly, a separate etch process using a different etch process and/or chemistry is then used to selectively etch away the third etch stop layer 30 to form the fourth mesa 50 (step 204). Notably, the material of the second cathode contact layer 28 is not compatible with the etching process used in step 204, and therefore the etching process does not affect the second cathode contact layer 28. Accordingly, a separate etch process using a different etch process and/or chemistry is then used to selectively etch away the second cathode contact layer 28 (step 206). As discussed above, the second etch stop layer 26 is not affected by the etch process in step 206, and thus a separate etching process is used to selectively etch the second etch stop layer 26 to form the second mesa 46 (step 208). The first anode contact layer 24, the first varactor layer 22, and the first cathode layer 20 are then selectively etched (step 210). A separate etching process is then used to selectively etch the first etch stop layer 18 to form the first mesa 38 and the second mesa 42 (step 212). The first ohmic contact(s) 40, the second ohmic contact(s) 42, and the third ohmic contact(s) are then provided (step 214). Finally, the metallization layer 54 is provided (step 216). As will be appreciated by those of ordinary skill in the art, any number of masking and etching processes may be used to form the dual-stack varactor 14. All of these processes are contemplated herein.

(24) Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.