Circuit board and method for production thereof

Abstract

A circuit board (10, 10, 10) includes at last one insulating substrate layer (SL1, SL2, SL3, SL4, SL5) and a plurality of electrically conductive copper coats (C1, C2, C3) arranged on the at least one insulating substrate layer (SL1, SL2, SL3, SL4, SL5), wherein at least one of the electrically conductive copper coats (C1, C2, C3) is coated at least on both sides with a layer (HSI, HS2, HS3) made of a material for inhibiting electromigration, wherein on a layer (HS1, HS2) made of a material for inhibiting electromigration a further metal layer (M1, M2, M3, M3) is provided, which is in turn coated with a further layer (HS3, HS3) made of a material for inhibiting electromigration.

Claims

1. A circuit board, comprising: at least one insulating substrate layer and a multiplicity of electrically conductive copper layers arranged on the at least one insulating substrate layer; and at least one of the electrically conductive copper layers is coated on both sides with an intermediate layer and an upper layer, respectively, for inhibiting electromigration, a further metal layer being provided on the upper layer for inhibiting electromigration, which further metal layer is in turn coated with a further layer for inhibiting electromigration, the intermediate layer being disposed between the at least one insulating substrate layer and the at least one of the electrically conductive copper layers.

2. The circuit board as claimed in claim 1, wherein at least one bore is provided, which connects at least two copper layers and on an inner wall of which the further layer for inhibiting electromigration is applied.

3. The circuit board as claimed in claim 2, wherein the bore is a through-contact, a buried bore or a blind hole.

4. The circuit board as claimed in claim 1, wherein a material for inhibiting electromigration is zinc, brass, a layer sequence comprising nickel or a nickel compound.

5. The circuit board as claimed in claim 1, and further comprising a solder resist covering, the further layer for inhibiting electromigration being provided between an uppermost copper layer and the solder resist covering.

6. The circuit board as claimed in claim 5, wherein a region used to form a connection position does not have a solder resist covering, and a surface material of the connection position is formed by an inhibition layer of a material for inhibiting electromigration, which is a different material than the further layer for inhibiting electromigration provided below the solder resist covering.

7. A method for producing a circuit board, the method comprising the following steps: forming a layer sequence of a substrate layer and a copper layer with an intermediate layer for inhibiting electromigration; applying an upper layer for inhibiting electromigration onto the copper layer; depositing a further metal layer onto the upper layer for inhibiting electromigration; etching the layer sequence formed, in order to form conductor structures; depositing a further layer for inhibiting electromigration.

8. The method as claimed in claim 7, wherein the forming step comprises the following steps: providing a substrate layer; applying the intermediate layer for inhibiting electromigration onto the substrate layer; applying the copper layer.

9. The method as claimed in claim 7, wherein the forming step comprises the following steps: providing the substrate layer; providing a copper foil which has a bonding layer suitable for inhibiting electromigration, the copper foil forming the copper layer; applying the copper foil onto the substrate layer in such a way that the bonding layer is applied in order to form an inhibition layer suitable for inhibiting electromigration on the substrate layer and comes to lie between the substrate layer and the copper layer formed by the copper foil.

10. The method as claimed in claim 7, wherein the forming step comprises providing a copper-masked substrate layer which has a layer suitable for inhibiting electromigration provided in between a copper sheet or lining forming the copper layer.

11. The method as claimed in claim 7, and further comprising, after the step of forming the layer sequence, the step: boring the substrate layer with the copper layer and the intermediate layer for inhibiting electromigration.

12. The method as claimed in claim 7, and further comprising the step of forming further circuit board layers by pressing together the layer sequence with further substrate layers.

13. The method as claimed in claim 7, wherein a material for inhibiting electromigration is selected from the group consisting of zinc, brass, nickel or nickel compounds.

14. The method as claimed in claim 13, wherein inner-lying n layers for inhibiting electromigration are formed from zinc or brass or nickel compounds, and external layers for inhibiting electromigration are formed from nickel compounds.

15. The method as claimed in claim 7, and further comprising the step of forming a a connection position surrounded by solder resist on the circuit board with the following steps: applying a solder resist covering on an external inhibition layer of a first material for inhibiting electromigration on the surface of a circuit board; removing the solder resist in a region intended as a connection position above the inhibition layer; removing the first material of the inhibition layer in the region intended as a connection position; forming the connection position by applying a layer of a second material for inhibiting electromigration in the uncovered region.

Description

BRIEF DESCRIPTION OF THE DRAWING

(1) FIG. 1 shows a schematic sectional representation of one exemplary embodiment of a multilayer circuit board according to the invention.

(2) FIG. 2 shows a schematic sectional representation of an alternative exemplary embodiment of a multilayer circuit board according to the invention with a blind hole.

(3) FIG. 3 shows a detail of the circuit board of FIG. 2 with an alternatively configured blind hole as a further exemplary embodiment.

(4) FIG. 4 shows as a further exemplary embodiment a schematic sectional representation of a two-layer circuit board according to the invention.

(5) FIG. 5 shows as a further exemplary embodiment a schematic sectional representation of a detail a surface of a circuit board according to the invention with solder resist covering.

DETAILED DESCRIPTION

(6) Parts which correspond to one another are provided with the same references in all the figures.

(7) FIG. 1 shows a schematic sectional representation of one exemplary embodiment of a circuit board 10 according to the invention. The section plane of the representation extends essentially perpendicularly to an extent plane spanned by the circuit board 10.

(8) The circuit board 10 comprises a layer structure known per se, consisting of a multiplicity of electrically insulating substrate layers SL1, SL2, SL3, SL4 and SL5, namely a central substrate layer SL1, inner-lying substrate layers SL2, SL3 respectively arranged below and above the central layer, and external substrate layers SL4, SL5 respectively adjacent to the two inner-lying substrate layers SL2, SL3. The substrate layers SL1 to SL5 are, for example, formed from a glass fiber-reinforced epoxy resin. The substrate layers SL1 SL5 are firmly connected to one another, for example by pressing or adhesive bonding.

(9) The substrate layers SL1 to SL5 comprise electrically conductive copper layers C1, C2 and C3. The electrically conductive copper layers C1 to C3 form electrically conductive structures or layers within the circuit board 10. In particular, the copper layers C1 to C3 are used as conductor tracks or conductor paths and are used for electrical connection of electronic component parts (not represented), with which the circuit board 10 is fitted and which from a circuit arrangement. For instance, electronic component parts (not represented), for example transistors, resistors, semiconductor components and the like may be arranged on one or both of the external substrate layers SL4, SL5 and electrically connected to the electrically conductive copper layers by means of soldering, bonding and/or adhesive bonding.

(10) According to the invention, the copper layers C1 to C3 have a lower inhibition layer HS1 and an upper inhibition layer HS2 respectively on a lower side and an upper side. In the present case, an inhibition layer is intended to mean a layer of a material which is suitable for inhibiting electromigration from the neighboring metal (copper) layer. Such materials may (not exclusively), be zinc, brass, nickel compounds such as nickel-gold (NiAu) or nickel-palladium-gold (NiPdAu), or alternatively tin or nonmetallic materials.

(11) The terms lower side and upper side of a copper layer are in the present case respectively intended to mean a surface facing toward the associated substrate layer or close the substrate layer (lower side), and a surface facing away from the associated substrate layer or remote from the substrate (upper side), independently of whether the copper layer is applied above or below the substrate layer (i.e. independently of the orientation of the representation in the figure). Or, in other words the terms lower side and upper side are independent of above and below in the figure representation, but instead relate to the relationship between the substrate layer and the copper layer.

(12) In order, as already explained in the introduction, to reinforce the copper layers C1 to C3 and/or increase their conductance, all or some of the copper layers C1 to C3 may be coated with a further metal layer. In the exemplary embodiment represented, the first copper layers C1 on the central substrate layer SL1 and the third copper layers C3 on the outer substrate layers SL4 and SL5, respectively, are provided with a further metal layer M1 or M3 on their respective inhibition layer. However, fewer or further copper layers may also be provided with a further metal layer.

(13) In the case of bores (through-contacts, vias, buried bores, blind holes), the further metal layer represents the metallization of the bore inner wall which is conventional in the prior art.

(14) According to the invention, the further metal layer is applied on the respective upper inhibition layer HS2 of the corresponding copper layer C1, C3. A further inhibition layer HS3 is applied on the further metal layer M1, M3. Besides protection against the CAF effect, this also leads to corrosion protection.

(15) In the case of the further inhibition layer HS3 on the outer levels, i.e. the uncovered inhibition layer, it is recommendable to form it from a corrosion-resistant and/or readily solderable material (or a material sequence), for example NiAu or NiPdAu. As an alternative, in this case as well a zinc layer or a layer containing zinc is also possible. As already indicated, it is however also possible to form this uncovered inhibition layer directly on the copper layer 3 when a required conductance of this copper layer is achieved even without a further metal layer M3.

(16) In the scope of their technical knowledge depending on design-technology and method-technology requirements, the person skilled in the art may decide whether the inhibition layers should all consist of the same material or should consist of different materials. In principle, any desired material combination of inhibition layers within a circuit board is possible.

(17) In the exemplary embodiment represented, outer copper structures C3 are electrically conductively connected to one another by means of a through-contact 12. The through-contact 12 is produced by a bore through the substrate layers SL1 to SL5. As a first layer inside the bore, the inhibition layer HS2 is provided, with which the outer copper layer C3 is also coated. This has the effect that the further metal layer M3 subsequently provided in order to increase the electrical conductance is protected with respect to other electrically conductive structures in the multilayer circuit board 10 against CAF effects (this inhibition layer HS2 therefore represents the lower inhibition layer for the further metal layer M3, while at the same time it represents the upper inhibition layer in relation to the outer copper layer C3). The inhibition layer HS2 may be applied in one working step both on the copper layer C1/C3 and on the bore inner wall. It may, however, also be recommendable to apply the inhibition layer on the copper layer C1/C3 and on the bore inner wall in separate working steps, for example when different materials are desired.

(18) The inhibition layer HS3 of the external substrate layers SL4 and SL5, which may for example (as already mentioned) be formed as a nickel-gold layer or nickel-palladium-gold layer or even as a zinc layer or brass layer, is then applied on the further metal layer M3 in the bore 12.

(19) The electrically conductive copper layers C2 applied on the two inner-lying substrate layers SL2 and SL3 also have on their upper side a thin inhibition layer HS2, which is preferably corrosion-resistant. Solderability of this inhibition layer HS2 on the inner-lying copper layers C2 is not absolutely necessary since no electronic component parts are applied on these copper layers. If fitting of inner-lying surfaces with electronic components is intended, good solderability of the inner-lying inhibition layer HS2 would correspondingly also be required.

(20) In the exemplary embodiment represented, the inhibition layer HS2 on the inner-lying copper layer C2 is formed from a zinc layer or brass layer. Zinc and brass are particularly highly suitable as corrosion protection and form a barrier on the electrically conductive copper structures against release of copper constituents of the electrically conductive copper structures. The CAF effect is thereby reliably avoided or at least reduced.

(21) The exemplary embodiment represented furthermore comprises a so-called buried bore 14, also referred to as a buried via. By means of the buried bore 14, inner-lying copper structures C1 of the central substrate layer SL1 are electrically conductively connected to one another. In a similar way to the through-contact 12, the buried bore 14 has a thin inhibition layer HS2 on an inner wall in order to reliably avoid or at least minimize the CAF effect. A further metal layer M1 is applied on the inhibition layer HS2, and an inhibition layer HS3 is in turn provided on this metal layer in order to also protect the further metal layer M1 against the CAF effect. Both the base copper layer C1 and the further metal layer M1 therefore have respectively an inhibition layer on both sides, the upper inhibition layer of the copper layer representing the lower inhibition layer of the further metal layer.

(22) The exemplary embodiment of FIG. 1 serves merely for illustration purposes. In particular, it should be stated that the invention is not restricted to the represented combination of internal and external layers, as well as through-contacts and buried bores, but that any desired combinations of these elements are available to the person skilled in the art when designing a circuit board structure.

(23) In the exemplary embodiments of FIGS. 2 and 3, in addition the circuit board 10 also comprises a so-called blind hole 16 (blind via). The blind hole 16 electrically conductively connects the electrically conductive copper layer C3 of the upper (in the representation of the figures) external substrate layer SL5 to the electrically conductive copper layer C1 of the central substrate layer SL1. The blind hole 16 is furthermore provided with an inhibition layer HS2, which is formed in a similar way to the described inhibition layer HS2 of the through-contact 12 and is applied directly onto an inner wall of the blind hole 16.

(24) Expediently, the inhibition layers HS2 of the through-contact 12 and of the blind hole 16 are deposited simultaneously in the production method. As an alternative, however, this may also be carried out at different times.

(25) In order to increase the electrical conductance, the inhibition layer HS2 is coated with a further metal layer. In the case of the exemplary embodiment of FIG. 2, this may be a complete metal filling M3. As an alternative thereto, however, it may also be a metal layer M3 which follows the deepening of the blind hole 16, as is shown by way of example in FIG. 3. In both variants, an inhibition layer HS3 is then again formed on the metal layer M3 or M3. In the example of FIG. 2, the inhibition layer HS3 closes off the blind hole 16 horizontally, while in the example of FIG. 3 the inhibition layer HS3 extends along the metal layer M3 into the blind hole 16.

(26) As can be seen in the representations of FIGS. 2 and 3, the inhibition layer HS2 of the blind hole 16 is led out onto the upper external substrate layer SL5 and extends in a section parallel to the surface of the substrate layer SL5, while covering the copper layer C3 arranged on the upper external substrate layer SL5. This led-out section of the inhibition layer HS2 is in turn provided with a material of the metal filling M3, M3, which is applied as a layer on the external section of the inhibition layer HS2.

(27) FIG. 4 shows as a further exemplary embodiment a schematic sectional representation of a two-layer circuit board 10 according to the invention having only one substrate layer SL1 and a through-contact 12.

(28) The circuit board 10 of the exemplary embodiment of FIG. 4 is configured as a double-sided circuit board, on the opposite outer surfaces of which electrically conductive copper structures C1 are applied, these being electrically conductively connected to one another by means of the through-contact 12.

(29) In order to produce a circuit board according to the invention, the person skilled in the art may use materials and method sequences which are known per se, and which therefore need not be explained in detail and at length below.

(30) In the simple case of the exemplary embodiment represented in FIG. 4, a substrate layer SL1 is provided, on which a first copper layer C1 is applied or deposited in a manner known per se after a first inhibition layer HS1 has been applied. As an alternative, the copper layer C1 may be applied with the aid of a copper foil which already comprises on one side a layer with a material suitable as an inhibition layer. Lastly, as a further alternative, a copper-masked substrate layer may be provided, on which a layer suitable as an inhibition layer is likewise already present below the copper layer (i.e. between the substrate layer and the copper layer). Typically, suitable copper foils with a brass coating to improve the adhesion properties of the Cu foil are commercially available.

(31) Subsequently, a further inhibition layer (inhibition layer HS2) is applied onto the copper layer C1. This may be done currentlessly or galvanically (for example electroless zinc deposition or chemical deposition of brass) respectively with a predetermined layer thickness of at least 100 nm, typically from 100 nm to 1500 nm. It would also be conceivable to produce brass from the Cu structures and a zinc coating by carrying out a thermal process during the production of the multilayer circuit board.

(32) In the case of applying a through-bore, as in the case of the through-contact 12 of FIG. 4, the boring step is carried out before the application of the second or upper inhibition layer HS2. Then, the inhibition layer HS2 may subsequently also be introduced into the bore in order to cover the inner wall of the through-contact in one method step (after the inner wall has previously been cleaned and made capable of receiving deposition in the manner known to the person skilled in the art). The inhibition layer HS2 may be chemically deposited on the inner wall of the through-contact (or also of the buried bore according to the exemplary embodiments of FIGS. 1 and 2). For example, this is done with chemical bath deposition. The electrically nonconductive borehole wall is to this end previously rendered conductive by means of a circuit board technique known to the person skilled in the art, in order to provide it with the inhibition layer by means of a galvanic process.

(33) The further metal layer M1 may subsequently be deposited galvanically onto the inhibition layer. To this end, for example, copper is deposited on the inhibition layer. The inhibition layer in these cases consists of a suitable metal, or a suitable metal compound, so as to permit the subsequent galvanic deposition.

(34) In an etching process, the desired conductor structures are provided by etching the applied layers down to the substrate layer, and in a subsequent step the deposition of a further (in the case of the example of FIG. 4 outer) inhibition layer HS3 is carried out. The further inhibition layer HS3 is applied in such a way that it covers the conductor structures fully, i.e. not only on the surface but also laterally (conductor side edges) as can be seen clearly in the figures and is illustrated in FIG. 4 by means of drawn arrows P. In particular, the further inhibition layer HS3 also extends through the entire through-contact 12 (or alternatively the buried bore 14 of FIG. 1).

(35) If a PCB is intended to comprise a plurality of substrate layers, the described process is repeated by pressing the first (central) substrate layer SL1 with the structures provided thereon together with further substrate layers SL2, SL3, on which in turn further copper layers are correspondingly applied and/or boring is carried out. For example, the circuit board shown in the exemplary embodiment of FIG. 4 may be used as a basis for pressing together with further substrate layers applied above and below. By entry of the resin liquefied during the pressing process into the through-bore, a buried bore is then provided.

(36) On electrically conductive copper layers of external substrate layers (such as the copper layer C1 in the exemplary embodiment of FIG. 4 or the copper layer C3 in the case of the exemplary embodiments of FIGS. 1 to 3), a metal or a metal compound is preferably likewise respectively, for example, electrolessly deposited in order to form an external inhibition layer HS3. For example, a nickel-gold compound is chemically deposited as a metal compound. Care is additionally be taken regarding solderability of the material for the inhibition layer of external copper layers, for which reason nickel-gold is particularly suitable. As an alternative, a less expensive material, for example zinc or tin, may also be used.

(37) In the case of circuit boards in which a solder resist covering is to be provided on the surface, the procedure may for example be carried out as in the further exemplary embodiment represented in FIG. 5.

(38) FIG. 5 shows a schematic sectional representation of a detail of a surface of a circuit board 10 according to the invention, having a solder resist covering 20 applied on the surface. In a similar way as in the exemplary embodiment of FIG. 1, the circuit board 10 has a through-contact 12 on the left-hand side in the representation of FIG. 5. On the surface of the circuit board, i.e. on the upper side of the upper substrate layer SL5, the layer sequence according to the invention, consisting of a lower inhibition layer HS1, a copper layer C3, an upper inhibition layer HS2, a further metal layer M3 and a further inhibition layer HS3, forms a conductor track 30 which leads to a connection position 40 on the right-hand side of the circuit board 10. The connection position 40 is free of solder resist but otherwise enclosed by the solder resist covering 20.

(39) In order to form the connection position 40, the following procedure is carried out: after the application of the further metal layer M3 as described, and the subsequent etching process to form the conductor track 30, an inhibition layer HS3 is applied, which fully covers the further metal layer and also (at the edges) the underlying layers. The inhibition layer HS3 is preferably a material which is economical but performs well in the inhibition of electromigration, for example zinc or brass. Next, the inhibition layer HS3 covering 20 over the entire surface of the circuit board 10 and are covered with the solder resist. In the region of the connection position to be formed, the solder resist is removed, i.e. the connection position is uncovered. The further inhibition layer HS3 of zinc or brass is then removed again in the uncovered region, and as an alternative material a further inhibition layer HS3 of nickel or a nickel compound, or a layer sequence comprising nickel or a nickel compound, is applied (NiAu or NiPdAu). A or the soldering process, an adhesive-bonding process or a wire-bonding process may then be carried out on this connection position 40. Besides the costs (a layer of zinc or brass is much more economical than a layer sequence comprising gold or palladium), criteria for the material selection are in this case the respective properties of the materials in relation to the further preparation or processing on the respective inhibition layer (such as adhesion properties for solder resist, soldering properties for the connection position, etc.).

(40) Of course, the described procedure may also be carried out in a different geometry or with a different layer structure, for example without a further metal layer M3.