Abstract
Analog multipliers circuits can provide signal processing asynchronously and clock free and with low power consumptions, which can be advantageous, including in emerging mobile, portable, and at edge or near sensor artificial intelligence (AI) and machine learning (ML) applications. As such, analog multipliers can process signals memory-free in AI and ML applications, which avoids the power consumption and latency delays attributed to memory read-write cycles in conventional AI and ML digital processors. Based on standard digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of multi-quadrant current-mode analog multiplier (iMULT) circuits that can be utilized in current-mode multiply-accumulate (iMAC) circuits and artificial neural network (ANN) end-applications that require high-volumes, low costs, medium precision, low power consumptions, and clock free asynchronous signal processing.
Claims
1. A mixed-signal current-mode multi-quadrant data-converter qDC system in an integrated circuit, the qDC system comprising: at least one qDAC of a plurality of bipolar digital-input to unipolar current analog-output converters (qDAC), each qDAC comprising: a digital signal conditioning circuit (dSC circuit) comprising a digital-input magnitude port (D.sub.MAG port) having a plurality of bits, a sign digital-input port (D.sub.SIGN port) that is 1-bit wide, and a digital output port (Dour port) having a plurality of bits; the dSC circuit comprising a plurality of Exclusive NOR gates (XNOR gates), each XNOR gate comprising a B digital-input port, (B.sub.XNOR port), a C digital-input port (C.sub.XNOR port), and a D digital-output port (D.sub.XNOR port); the B.sub.XNOR port of each XNOR gate of the plurality of XNOR gates coupled to the D.sub.SIGN port; the C.sub.XNOR port of each XNOR gate of the plurality of XNOR gates coupled to a corresponding bit of the D.sub.MAG port; the D.sub.XNOR port of each XNOR gate of the plurality of XNOR gates coupled to a corresponding bit of the D.sub.OUT port; a current mode Digital-to-Analog-Converter (iDAC) comprising a digital-input port (Di.sub.DAC port), a current analog-output port (Io.sub.DAC port), and a reference current analog-input port (Ir.sub.DAC port); the Di.sub.DAC port coupled to the D.sub.XNOR port; wherein the D.sub.MAG port and the D.sub.SIGN port comprise a bipolar digital-input port for receiving a bipolar digital input word (W.sub.D word) having a digital Most-Significant-Bit (W.sub.MSB bit) corresponding to the D.sub.SIGN port and a unipolar magnitude digital word (|W.sub.D| word) corresponding to the D.sub.MAG port; and wherein the Io.sub.DAC port generates a unipolar current analog-output signal (|W.sub.A| analog signal) that is responsive to a unipolar digital word (|W.sub.D| digital word) at the Di.sub.DAC port.
2. The mixed-signal current-mode multi-quadrant data-converter qDC system in an integrated circuit of claim 1, the qDC system further comprising: the at least one qDAC further comprising: an analog current-mode polarity conditioning circuit (iPC circuit) comprising a current analog-input port (Ii.sub.PC port), a sign control digital-input port (Si.sub.PC port), and a differential current analog-output port comprising an Io+.sub.PC port and an Io.sub.PC port; the D.sub.SIGN port of the qDAC coupled to the Si.sub.PC port; the Io.sub.DAC port of the qDAC coupled to the Ii.sub.PC port; and wherein if the Si.sub.PC port is asserted to an ON state, then a current signal flowing through the Ii.sub.PC port is steered onto the Io+.sub.PC port, else onto the Io.sub.PC port.
3. The mixed-signal current-mode multi-quadrant data-converter qDC system in an integrated circuit of claim 2, the qDC system further comprising a current mirror (CM) comprising an input port (CM.sub.I port) and an output port (CM.sub.O port); the Io+.sub.PC port of the iPC circuit coupled to the CM.sub.O port; the Io+.sub.PC port of the iPC circuit coupled to the CM.sub.I port; and wherein a bipolar current analog-output signal (W.sub.A signal) is generated at the CM.sub.O port that is equivalent to the W.sub.D word.
4. The mixed-signal current-mode multi-quadrant data-converter qDC system in an integrated circuit of claim 1, the qDC system further comprising wherein the at least one qDAC is a scalar qDAC; an at least one current mirror (CM) comprising an input port (CM.sub.I port) and an at least one output port (CM.sub.O port); the Io.sub.DAC port of the scalar qDAC coupled to the CM.sub.I port; the at least one CM.sub.O port coupled to the Ir.sub.DAC port of an at least one other qDAC of the plurality of qDACs; an at least one polarity XNOR gate (pXNOR gate) comprising a first digital-input port, a second digital-input port, and a digital-output port; an at least one analog current-mode polarity conditioning circuit (iPC circuit) comprising a current analog-input port (Ii.sub.PC port), a sign control digital-input port (Si.sub.PC port), and a differential current analog-output port comprising an Io+.sub.PC port and an Io.sub.PC port; the Io.sub.DAC port of the at least one other qDAC coupled with the Ii.sub.PC port of the at least one iPC circuit; the digital-output port of the at least one pXNOR gate coupled with the Si.sub.PC port of the at least one iPC circuit; the D.sub.SIGN port of the of the at least one qDAC coupled to the first digital-input port of the at least one pXNOR gate; and the D.sub.SIGN port of the of the scalar qDAC coupled to the second digital-input port of the at least one pXNOR gate.
5. The mixed-signal current-mode multi-quadrant data-converter qDC system in an integrated circuit of claim 1, the qDC system further comprising a plurality of bipolar digital-input to unipolar current analog-output multipliers (qMULT multiplier), an at least one qMULT multiplier comprising: an at least one first qDAC (EqDAC) of the plurality of qDACs; an at least one second qDAC (FqDAC) of the plurality of qDACs; an at least one XNOR gate (pXNOR gate) comprising a first digital-input port, a second digital-input port, and a digital-output port; an at least one analog current-mode polarity conditioning circuit (iPC circuit) comprising a current analog-input port (Ii.sub.PC port), a sign control digital-input port (Si.sub.PC port), and a differential current analog-output port comprising an Io+.sub.PC port and an Io.sub.PC port; the Io.sub.DAC port of the iDAC of the at least one EqDAC coupled with the Ir.sub.DAC port of the iDAC of the at least one FqDAC; the Io.sub.DAC port of the iDAC of the at least one FqDAC coupled with the Ii.sub.PC port of the at least one iPC circuit; the D.sub.SIGN port of the dSC circuit of the at least one EqDAC coupled with the first digital-input port of the at least one pXNOR gate; the D.sub.SIGN port of the dSC circuit of the at least one FqDAC, coupled with the second digital-input port of the at least one pXNOR gate; the digital output port of the at least one pXNOR gate coupled with the Si.sub.PC port of the at least one iPC circuit; and wherein if the Si.sub.PC port is asserted to an ON state, then a current signal flowing through the Ii.sub.PC port of the at least one iPC circuit is steered onto the Io+.sub.PC port of the at least one iPC circuit, else onto the Io.sub.PC port of the at least one iPC circuit.
6. The mixed-signal current-mode multi-quadrant data-converter qDC system in an integrated circuit of claim 5, the qDC system further comprising for the at least one iPC circuit of the at least one qMULT multiplier, the Io+.sub.PC port coupled to an I+ port; for the at least one iPC circuit of the at least one qMULT multiplier, the Io.sub.PC port coupled to an I port; an at least one analog current mirror (CM) comprising a current analog-input port (CM.sub.I port) and a current analog-output port (CM.sub.O port); the I+ port coupled to the CM.sub.O port of the at least one CM; the I port coupled to the CM.sub.I port of the at least one CM; and wherein an at least one bipolar summation current analog-output signal (EF signal) is generated at the CM.sub.O port.
7. A mixed-signal current-mode multi-quadrant scalar multiplier SqMULT method in an integrated circuit, the SqMULT method comprising: operating a plurality of transistors (T.sub.LOG transistor), each T.sub.LOG transistor having a logarithmic relationship between an input voltage analog port (A.sub.V port) of the T.sub.LOG transistor and an output current analog port (A.sub.I port) of the T.sub.LOG transistor; operating a reference T.sub.LOG transistor (Tr.sub.LOG transistor), a scalar T.sub.LOG transistor (Ts.sub.LOG transistor), an at least one X T.sub.LOG transistor (Tx.sub.LOG transistor), and an at least one O T.sub.LOG transistor (To.sub.LOG transistor); supplying a reference current (I.sub.R current) to the A.sub.I port of the Tr.sub.LOG transistor; supplying a scalar current (I.sub.S current) to the A.sub.I port of the Ts.sub.LOG transistor; supplying an at least one X current (I.sub.X current) to the A.sub.I port of an at least one Tx.sub.LOG transistor; generating a difference voltage (V.sub.S-R voltage) between the A.sub.V port of the Ts.sub.LOG transistor and the A.sub.V port of the Tr.sub.LOG transistor; generating a corresponding at least one difference voltage (V.sub.O-X voltage) between an at least one A.sub.V port of the at least one To.sub.LOG transistor and a corresponding at least one A.sub.V port of a corresponding at least one Tx.sub.LOG transistor; and generating a corresponding at least one O current (I.sub.O current) through an at least one A.sub.I port of a corresponding at least one To.sub.LOG transistor by substantially equalizing the V.sub.S-R voltage with the corresponding at least one V.sub.O-X voltage.
8. The mixed-signal current-mode multi-quadrant scalar multiplier SqMULT method in an integrated circuit of claim 7, the SqMULT method further comprising: operating a plurality of iSC circuits, each iSC circuit receiving a bipolar current analog-input signal (W.sub.A signal) and generating a unipolar current analog-output signal (|W.sub.A| signal) as a magnitude of the W.sub.A signal, and generating a sign digital-output bit (S bit) as the sign of the W.sub.A signal; generating the I.sub.S current by a first |W.sub.A| signal (|W.sub.AS| signal) of a first S iSC circuit of the plurality of iSC circuits; generating a first S bit (S.sub.S bit) of the first S iSC circuit of the plurality of iSC circuits; generating the at least one I.sub.X current by a corresponding at least one |W.sub.A| signal (|W.sub.AX| signal) of a corresponding at least one X iSC circuit of the plurality of iSC circuits; generating an at least one S bit (S.sub.X bit) of the corresponding at least one X iSC circuit of the plurality of iSC circuits; generating a plurality of Io currents; operating a plurality of iPC circuits, each iPC circuit corresponding to and receiving one of the Io currents into an Ii.sub.PC port of the corresponding iPC, steering the corresponding I.sub.O current from the Ii.sub.PC port onto an at least one of an Io+.sub.PC port and an Io.sub.PC port of the corresponding iPC circuit responsive to a signal at an Si.sub.PC port of the corresponding iPC circuit, wherein each iPC circuit comprises a current analog-input port (Ii.sub.PC port), a sign control digital-input port (Si.sub.PC port), and a differential current analog-output port comprising an Io+.sub.PC port and an Io.sub.PC port; and controlling the Si.sub.PC port of the corresponding iPC circuit by a logical combination of the corresponding at least one S.sub.X bit and the corresponding at least one S.sub.S bit.
9. The mixed-signal current-mode multi-quadrant scalar multiplier SqMULT method in an integrated circuit of claim 7, the SqMULT method further comprising: operating a plurality of digital signal conditioning circuits (dSC circuit); receiving a bipolar digital-input word (W.sub.D word) into an at least one of a plurality of corresponding dSC circuits, and generating a unipolar digital-output word (|W.sub.D| word) as a magnitude of the W.sub.D word, and generating a sign digital-output bit (S.sub.D bit) as a Most-Significant-Bit (MSB) of the W.sub.D word; operating a plurality of current-mode Digital-To-Analog-Converters (iDAC); receiving a |W.sub.D| word of a corresponding dSC circuit into an at least one of a plurality of corresponding iDACs, and generating a current analog output signal (|W.sub.A| word); generating a plurality of Io currents; operating a plurality of iPC circuits, each iPC circuit corresponding to and receiving one of the Io currents into an Ii.sub.PC port of the corresponding iPC, steering the corresponding I.sub.O current from the Ii.sub.PC port onto an at least one of an Io+.sub.PC port and an Io.sub.PC port of the corresponding iPC circuit responsive to a signal at an Si.sub.PC port of the corresponding iPC circuit, wherein each iPC circuit comprises a current analog-input port (Ii.sub.PC port), a sign control digital-input port (Si.sub.PC port), and a differential current analog-output port comprising an Io+.sub.PC port and an Io.sub.PC port; generating the I.sub.S current by a first |W.sub.A| signal (|W.sub.AS| signal) of a first S iDAC of a corresponding at least one S iDAC of the plurality of iDACs; generating a first S bit (S.sub.D bit) of a first S dSC circuit of the plurality of dSC circuits; generating the at least one I.sub.X current by a corresponding at least one |W.sub.A| signal (|W.sub.AX| signal) of a corresponding at least one iDAC of the plurality of iDACs; generating an at least one S bit (S.sub.X bit) of a corresponding at least one X dSC circuit of the plurality of dSC circuits; and controlling a corresponding at least one Si.sub.PC port of a corresponding at least one iPC circuit of the plurality of the iPC circuits by logical combination of the corresponding at least one S.sub.X bit and the corresponding at least one S.sub.S bit.
10. The mixed-signal current-mode multi-quadrant scalar multiplier SqMULT method in an integrated circuit of claim 7, the SqMULT method further comprising: wherein each T.sub.LOG of the plurality of T.sub.LOGS is at least one of a bipolar junction transistor (T.sub.BJT) and a Metal-Oxide-Semiconductor-Field-Effect-Transistor (T.sub.MOSFET); wherein each T.sub.BJT having a collector terminal, a base terminal, and an emitter terminal, wherein the input port of the T.sub.LOG transistor is between the base terminal and the emitter terminal, constituting the voltage analog port (A.sub.V port), and the output port of the T.sub.LOG transistor is the collector terminal, constituting the current analog port (A.sub.I port); and wherein each T.sub.MOSFET having a drain terminal, a gate terminal, and a source terminal, wherein the input port of the T.sub.LOG transistor is between the gate terminal and the source terminal, constituting the voltage analog port (A.sub.V port), and the output port of the T.sub.LOG transistor is the drain terminal, constituting the current analog port (A.sub.I port).
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) FIG. 1A is a simplified circuit schematic illustrating an analog current-mode signal conditioning (iSC.sub.1a) circuit.
(2) FIG. 1B is a simplified circuit schematic illustrating a digital signal conditioning (dSC.sub.1b) circuit.
(3) FIG. 1C is a simplified circuit schematic illustrating a digital polarity conditioning (dPC.sub.1c) circuit.
(4) FIG. 1D is a simplified circuit schematic illustrating an analog current-mode polarity conditioning (iPC.sub.1d) circuit.
(5) FIG. 1E is a simplified circuit schematic illustrating another analog current-mode polarity conditioning (iPC.sub.1e) circuit.
(6) FIG. 2A is a simplified block diagram illustrating a mixed-mode bipolar data-converter (BiDC) method.
(7) FIG. 2B is a simplified block diagram illustrating a bipolar current-mode digital-to-analog converter (BiDAC) that utilizes the BiDC method illustrated in FIG. 2A.
(8) FIG. 2C is a simplified block diagram illustrating a bipolar current-mode analog-to-digital converter (BiADC) that utilizes the BiDC method illustrated in FIG. 2A.
(9) FIG. 3A is a simplified block diagram illustrating a multi-quadrant multiplier (qMULT) method.
(10) FIG. 3B is a simplified block diagram illustrating a multi-quadrant analog current-input to analog current-output multiplier (qiMULT.sub.3b) utilizing the qMULT method illustrated in FIG. 3A.
(11) FIG. 3C is a simplified block diagram illustrating a multi-quadrant digital input to analog current output multiplier (qiMULT.sub.3c) utilizing the qMULT method illustrated in FIG. 3A.
(12) FIG. 3D is a simplified block diagram illustrating another multi-quadrant analog current-input to analog current-output multiplier (qiMULT.sub.3d) utilizing the qMULT method illustrated in FIG. 3A.
(13) FIG. 3E illustrates a SPICE circuit simulation showing the input-output and linearity waveforms of the qiMULT.sub.3c of FIG. 3C.
(14) FIG. 3F illustrates a SPICE circuit simulation showing the input-output and linearity waveforms of the qiMULT.sub.3d of FIG. 3D.
(15) FIG. 3G illustrates a SPICE circuit simulation showing the input-output and linearity waveforms of the qiMULT.sub.3b of FIG. 3B.
(16) FIG. 4A illustrates a multiple-channel multi-quadrant analog current-input to current-output scalar multiplier (SqiMULT.sub.4a)
(17) FIG. 4B illustrates a multiple-channel multi-quadrant digital-input to current-output scalar multiplier (SqiMULT.sub.4b).
(18) FIG. 4C illustrates another multiple-channel multi-quadrant analog current-input to current-output scalar multiplier (SqiMULT.sub.4c).
(19) FIG. 4D is a simplified block diagram illustrating a multi-quadrant digital input to analog current output multiply-accumulate (qiMAC.sub.4d) utilizing qiMULT.sub.3c illustrated in FIG. 3D.
(20) FIG. 5A illustrates another multiple-channel multi-quadrant analog current-input to current-output scalar multiplier (SqiMULT.sub.5a)
(21) FIG. 5B illustrates another multiple-channel multi-quadrant digital-input to current-output scalar multiplier (SqiMULT.sub.5b).
SUMMARY OF THE DISCLOSURE
(22) An aspect of the present disclosure is a mixed-signal multi-quadrant data-converter (qDC) method in an integrated circuit, the qDC method comprising: converting a bipolar signal (E) to a unipolar signal (|E|), wherein the |E| is generated by a signal conditioner (SC) circuit; generating a sign signal (eS) indicating the polarity of the E, wherein the eS is generated by the SC circuit; converting the |E| to another form of a unipolar signal (|E|), wherein the |E| is generated by a single-quadrant Data-Converter (DC); and converting the |E| to another form of a bipolar signal (E), wherein the E is generated by a polarity conditioning circuit (PC), and wherein the polarity of E signal is programmed by the eS. The mixed-signal multi-quadrant data-converter (qDC) method in an integrated circuit, the qDC method further comprising: wherein the single-quadrant DC is at least one of a Digital-to-Analog Converter (DAC) and an Analog-to-Digital Converter (ADC). The mixed-signal multi-quadrant data-converter (qDC) method in an integrated circuit, the qDC method further comprising: operating the single-quadrant DC in current mode. The mixed-signal multi-quadrant data-converter (qDC) meth in an integrated circuit, the qDC method further comprising wherein if |E| is an analog signal, then |E| is a digital signal, and wherein if |E| is an analog signal, then |E| is a digital signal. The mixed-signal multi-quadrant data-converter (qDC) method in an integrated circuit, the qDC method further comprising: wherein the SC circuit is at least one of a full-wave rectifier circuit and an absolute-value circuit.
(23) An aspect of the present disclosure is a mixed-signal multi-quadrant multiplier (qMULT) method in an integrated circuit, the qMULT method comprising: converting an E bipolar signal (E) to an E unipolar signal (|E|), wherein the |E| is generated by a signal conditioner (SCE) circuit; generating an E sign signal (eS) indicating the polarity of the E, wherein the eS signal is generated by the SCE circuit; converting an F bipolar signal (F) to an F unipolar signal (|F|), wherein the |F| is generated by a signal conditioner (SCF) circuit; generating an F sign signal (fS) indicating the polarity of the F, wherein the fS signal is generated by the SCF circuit; multiplying |E| by |F| as a ratio of a unipolar reference signal (G) to generate a unipolar product signal (|E||F|/G), wherein the |E||F|/G signal is generated by a single-quadrant multiplier; and converting the |E||F|/G to a bipolar multi-quadrant product signal (|E||F|/G), wherein the |E||F|/G signal is generated by a polarity conditioning (PC) circuit wherein the polarity of |E||F|/G signal is accomplished by programming the PC circuit with the eS and fS signals. The mixed-signal multi-quadrant multiplier (qMULT) method in an integrated circuit, the qMULT method further comprising: wherein the single-quadrant multiplier is a single-quadrant analog multiplier. The mixed-signal multi-quadrant multiplier (qMULT) method in an integrated circuit, the qMULT method further comprising: wherein the single-quadrant analog multiplier operates in current mode. The mixed-signal multi-quadrant multiplier (qMULT) method in an integrated circuit, the qMULT method further comprising: wherein the single-quadrant multiplier utilizes a single-quadrant Digital-to-Analog Converter (DACE), wherein DACE's output is inputted to a reference port of a single quadrant Digital-to-Analog Converter (DACF). The mixed-signal multi-quadrant multiplier (qMULT) method in an integrated circuit, the qMULT method further comprising: wherein the single-quadrant DACE and DACF operates in current mode. The mixed-signal multi-quadrant multiplier (qMULT) method of in an integrated circuit, the qMULT method further comprising: wherein the single-quadrant multiplier utilizes a single-quadrant Analog-to-Digital Converter (ADCE), wherein ADCE's output is inputted to a digital input port of a single quadrant Digital-to-Analog Converter (DACF). The mixed-signal multi-quadrant multiplier (qMULT) method in an integrated circuit, the qMULT method further comprising: wherein the single-quadrant ADCE and DACF operates in current mode. The mixed-signal multi-quadrant multiplier (qMULT) method in an integrated circuit, the qMULT method further comprising: wherein the single-quadrant Data-Converters (DC) is a current-mode Data-Converter (iDC). The mixed-signal multi-quadrant multiplier (qMULT) method of claim 6 in an integrated circuit, the qMULT method further comprising: Wherein the SCE circuit is at least one of full-wave rectifier circuit and an absolute-value circuit.
(24) An aspect of the present disclosure is a mixed-signal multi-quadrant scalar multiplier (SqMULT) method in an integrated circuit, the SqMULT method comprising: converting a scalar E bipolar signal (E) to a scalar E unipolar signal (|E|), wherein the |E| is generated by a scalar E signal conditioner (SCE) circuit; generating a scalar E sign signal (eS) indicating the polarity of the scalar E, wherein the eS is generated by the scalar SCE circuit; converting a plurality of F bipolar signals (pF) to a plurality of F unipolar signals (|pF|), wherein the |pF| is respectively generated by a plurality of F signal conditioners (pSCF) circuits; generating a plurality of F sign signals (pfS) indicating the polarity of the plurality of Fs, wherein pfS is respectively generated by the plurality of the pSCF circuits; multiplying |E| by the plurality of |pF| as a ratio of a unipolar reference signal (G) to generate a plurality of scaled unipolar product signals (|E||pF|/G), wherein the |E||pF|/G is respectively generated by a plurality of single-quadrant multipliers; converting the plurality of |E||pF|/G to a plurality of scaled bipolar multi-quadrant product signals (|E||pF|/G) utilizing respectively a plurality of polarity conditioning circuits (pPC), wherein the eS and the respective plurality of p f S program the polarity of the pPCs, and wherein the pPCs generate the respective plurality of the |E||pF|/G. The mixed-signal multi-quadrant scalar multiplier (SqMULT) method in an integrated circuit, the SqMULT method further comprising: wherein the plurality of single-quadrant multipliers utilize a plurality of single-quadrant Data-Converters (pDC). The mixed-signal multi-quadrant scalar multiplier (SqMULT) method in an integrated circuit, the SqMULT method further comprising: wherein the pDCs operate in current mode. The mixed-signal multi-quadrant scalar multiplier (SqMULT) method in an integrated circuit, the SqMULT method further comprising: wherein the plurality of SCF circuit is at least one of a plurality of full-wave rectifier circuits and a plurality of absolute-value circuits. The mixed-signal multi-quadrant scalar multiplier (SqMULT) method in an integrated circuit, the SqMULT method further comprising: wherein the plurality of single-quadrant multipliers utilize a plurality of single-quadrant analog multipliers (pMULT). The mixed-signal multi-quadrant scalar multiplier (SqMULT) method of claim 15 in an integrated circuit, the SqMULT method further comprising: wherein the pMULTs operate in current mode.
DETAILED DESCRIPTION
(25) Numerous embodiments are described in the present application and are presented for illustrative purposes only and is not intended to be exhaustive. The embodiments were chosen and described to explain principles of operation and their practical applications. The present disclosure is not a literal description of all embodiments of the disclosure(s). The described embodiments also are not, and are not intended to be, limiting in any sense. One of ordinary skill in the art will recognize that the disclosed embodiment(s) may be practiced with various modifications and alterations, such as structural, logical, and electrical modifications. For example, the present disclosure is not a listing of features which must necessarily be present in all embodiments. On the contrary, a variety of components are described to illustrate the wide variety of possible embodiments of the present disclosure(s). Although particular features of the disclosed embodiments may be described with reference to one or more particular embodiments and/or drawings, it should be understood that such features are not limited to usage in the one or more particular embodiments or drawings with reference to which they are described, unless expressly specified otherwise. The scope of the disclosure is to be defined by the claims.
(26) Although process (or method) steps may be described or claimed in a particular sequential order, such processes may be configured to work in different orders. In other words, any sequence or order of steps that may be explicitly described or claimed does not necessarily indicate a requirement that the steps be performed in that order. The steps of processes described herein may be performed in any order possible. Further, some steps may be performed simultaneously despite being described or implied as occurring non-simultaneously (e.g., because one step is described after the other step). Moreover, the illustration of a process by its depiction in a drawing does not imply that the illustrated process is exclusive of other variations and modifications thereto, does not imply that the illustrated process or any of its steps are necessary to the embodiment(s). In addition, although a process may be described as including a plurality of steps, that does not imply that all or any of the steps are essential or required. Various other embodiments within the scope of the described disclosure(s) include other processes that omit some or all of the described steps. In addition, although a circuit may be described as including a plurality of components, aspects, steps, qualities, characteristics and/or features, that does not indicate that any or all of the plurality are essential or required. Various other embodiments may include other circuit elements or limitations that omit some or all of the described plurality.
(27) Note that all the figures comprised of circuits, blocks, or systems illustrated in this disclosure are powered up by positive power supply V.sub.DD and negative power supply V.sub.SS, wherein V.sub.SS can be connected to the ground potential or zero volts. A bipolar signal is one that spans across two polarities (e.g., bipolar signal represents a signal that spans between positive and negative ranges). A unipolar signal is one that spans across one polarity (e.g., unipolar signal represents a signal that spans between positive and zero ranges). Terms FET is Field-Effect-Transistor; MOS is Metal-Oxide-Semiconductor. MOSFET is MOS FET. PMOS is P-channel or P-type MOS. NMOS is N-channel or N-type MOS. BiCMOS is Bipolar CMOS. The term BIT is Bipolar-Junction Transistor. The terms port or terminal are used interchangeably throughout this disclosure. The terms power supply voltage or supply voltage are used interchangeably throughout this disclosure. The body terminal of NMOSFET can be connected to its source terminal of NMOSFET or to V.sub.SS, throughout this disclosure. Additionally, the body terminal of PMOSFET can be connected to the source terminal of PMOSFET or to V.sub.DD throughout this disclosure. The term V.sub.GS or v.sub.GS are gate-to-source voltage for a MOSFET. The term V.sub.DS is drain-to-source voltage for a MOSFET. The term I.sub.DS or I.sub.D is drain current of a MOSFET (e.g., also I.sub.M1 or Id.sub.M1, or I.sub.D.sub.M1 is drain current of M.sub.1 that is a MOSFET, or I.sub.MF1.sub.5a is drain current of MF1.sub.5a which is a FET referred to as MF1 in FIG. 5A). The term V.sub.BE or v.sub.BE is base-to-emitter voltage of a BJT. The term I.sub.C is collector current of a BJT and I.sub.E Is emitter current of a BJT (e.g., also Ie.sub.Q1 or Ic.sub.q1 or I.sub.CE.sub.Q1 is a current of Q.sub.1 wherein Q.sub.1 is a BJT). Channel width over channel length is W/L which is the size of a MOSFET. This disclosure utilizes transistors (T) whose input-voltage (v.sub.I) to output-current (i.sub.O) transfer function approximately follows an exponential profile. The term MSB is most-significant-bit. The term LSB is least-significant-bit. Digital to Analog Converter is DAC and current mode DAC is iDAC. Analog to Digital to Converter is ADC and current mode ADC is iADC. SPICE is Simulation Program with Integrated Circuits Emphasis.
(28) The CMOSFETs, that operate in the subthreshold region, follow an approximate exponential v.sub.I to i.sub.O transfer function that can approximately be represented as follows:
(29)
wherein for a MOSFET: the V.sub.TH is threshold voltage, v.sub.GS is voltage between gate-terminal to source-terminal, i.sub.D is current through the drain terminal,
(30)
is a channel-width over channel-length ratio, V.sub.t is thermal voltage, n is slope factor, I.sub.DO is the characteristics current when v.sub.GSV.sub.TH. Note that in the case of a MOSFET operating in subthreshold, v.sub.I corresponds to v.sub.GS, and i.sub.O corresponds to i.sub.D or i.sub.DS. Moreover, note that for two equally sized and same type subthreshold MOSFET
(31)
where v.sub.GS1 and v.sub.GS2 are the first and second MOSFET's v.sub.GSs or v.sub.Is, and i.sub.D1, i.sub.D2 are the first and second MOSFET's i.sub.Ds or i.sub.Os. Note that throughout this disclosure, MOSFETs that operate in subthreshold have equal
(32)
unless otherwise specified. Unless otherwise specified, n stands for nano or 10.sup.9, stands for micro or 10.sup.6, and m stands for milli or 10.sup.3. The term plurality (p) of channels refers to p>2.
(33) Note that other manufacturing technologies, such as Bipolar, BiCMOS, and others can utilize this disclosure in whole or part.
(34) This disclosure presents several SPICE circuit simulations illustrating functionality, and feasibility of the disclosed embodiments. These simulations are not intended to guarantee the embodiment's performance to a particular range of specifications. Note that circuit simulations use the TOPSPICE simulator, and are based on approximate device models for a typical mainstream0.18 m CMOS process fabrication.
(35) Throughout this disclosure, analog multipliers (iMULT) circuits operate in current-mode and generally have the following benefits:
(36) First, the disclosed multi-quadrant multiplier utilizes only one single-quadrant multiplier, which keeps the circuit simple and save on die area and cost.
(37) Second, analog iMULT circuits in this disclosure can operate at higher speeds because they operate in current-mode, which is inherently fast.
(38) Third, given that the core of the disclosed multi-quadrant multiplier utilizes only one single-quadrant multiplier, the linearity of each of the four quadrant's transfer function match each other.
(39) Fourth, signal processing, that occurs within the nodes of iMULT and iMAC circuits in current mode, have small voltage swings (while retaining their speed and dynamic range benefits) which also enables operating the current-mode with lower power supply voltages.
(40) Fifth, because the core of the disclosed multi-quadrant multiplier utilizes only one single-quadrant multiplier, the dynamic response at each of the respective multiplier's four quadrant match each other.
(41) Sixth, the disclosed analog iMULT circuits operating in current mode, facilitates simple, low cost, and fast summation and or subtraction functions. For example, summation of plurality of analog currents could be accomplished by coupling the current signals. Depending on accuracy and speed requirements, subtraction of analog current signals could be accomplished by utilizing a current mirror where the two analog current signals are applied to the opposite side of the current mirror, for example.
(42) Seventh, majority of iMULT disclosed here, can operate with low power supplies since their operating headroom can be limited by a FET's V.sub.GS V.sub.DS, and naturally operating at low power supply voltages reduces power consumption.
(43) Eighth, operating the CMOSFETs, where applicable, in subthreshold enables analog iMULT circuits to operate with ultra-low currents, even lower power supplies, and ultra-low power consumption suitable for mobile applications, especially in mobile and portable and on-sensor AI & ML applications that may require numerous ultra-low current and low voltage supply analog iMULT circuits for computation.
(44) Ninth, iMULT can be arranged to generate non-linear outputs such as in square input-output transfer function or inverse input-output transfer functions. For example, by applying the same input to the two inputs of a multiplier, a square of the input can be generated at the output of the multiplier.
(45) Tenth, the disclosed analog iMULT circuits not requiring any capacitors nor any resistors, which reduces die size and die cost, and facilitates fabricating analog iMULT circuits in standard digital CMOS manufacturing that is not only low cost, but also main-stream and readily available for high-volume mass production applications, and proven for being rugged and having high quality.
(46) Eleventh, the disclosed analog iMULT circuits are free of clock, suitable for asynchronous (clock free) computation. As such, there is no clock related noise on power supplies and there is no dynamic power consumption due to a digital logic.
(47) Twelfth, the disclosed analog iMULT circuits are arranged in a symmetric, matched, and scaled manner. This trait facilitates devices parameters to track each other over process, temperature, and operating condition variations. Accordingly, the disclosed analog iMULT circuit's temperature coefficient and power supply rejection performance can be enhanced.
(48) Thirteenth, while digital computation is generally accurate but its higher power consumption may not be suitable for some low power applications. Current-mode analog and mixed-signal computation that is disclosed here leverage the trade off in analog signal processing between low power and analog accuracy in form of signal degradation, but not total failures. This trait can provide the AI & ML end-application with approximate results to work with instead of experiencing failed results.
(49) Fourteenth, utilizing plurality of analog inputs that are summed at an plurality of inputs or outputs of iMULTs (to arrange an analog scalar iMAC) would attenuate the statistical contribution of such cumulative analog random errors (such as random noise, offset, mismatches, linearity, gain, drift, etc.) at the summing nodes where plurality of analog iMULT currents are coupled (which are generated via the iDACs). The statistical contribution of such cumulative analog random errors, at the summing node, is the square root of the sum of the squares of such random error terms.
(50) Fifteenth, voltage mode multiplier's full-scale input and output voltage signal swings are restricted by power supply voltage levels. However, so long as operational transistor headroom is complied with, the disclosed analog current-mode iMULT and siMAC input and output current signals can span between zero and full scale, generally independent of the power supply voltage level.
(51) Sixteenth, the present disclosure provides iMULT and iMAC circuits that enable AI and ML applications to process information at or near edge and sensors which improves privacy, instead of sending information on the cloud.
(52) Seventeenth, the present disclosure provides iMULT and iMAC circuits for AI and ML applications that can run asynchronously which reduces latency and provides real-time computation.
(53) Eighteenth, the present disclosure provides iMULT and iMAC circuits AI and ML applications that can run asynchronously which frees the computation from read-write cycles to and from memory, which reduces dynamic power consumption and reduces memory area on chip.
Section 1ADescription of FIG. 1A
(54) FIG. 1A is a simplified circuit schematic illustrating an analog current-mode signal conditioning (iSC.sub.1a) circuit.
(55) The disclosed iSC.sub.1a embodiment illustrated in FIG. 1A receives a bipolar signal at its input Ii.sub.1a and generates a unipolar signal at its output Io.sub.1a and a sign (polarity) signal S.sub.1a. The disclosed embodiment illustrated in the iSC.sub.1a circuit of FIG. 1A performs the function of a full-wave rectifier or absolute-value circuit, in current mode. It would be obvious to one skilled in the art to utilize other full-wave rectifier or absolute-value circuits or variation of iSC.sub.1a. When iSC.sub.1a current input signal's polarity is positive, M1.sub.1a turns-off (which starves M5.sub.1a and M6.sub.1a from operating current). Here, M2.sub.1a turns-on and steers the Ii.sub.1a current signal into M3.sub.1a which is then mirrored through M4.sub.1a and onto the Io.sub.1a as the current output of iSC.sub.1a. Concurrently, S.sub.1a provides a sign signal reflecting the positive polarity of the bipolar signal at iSC.sub.1a's input Ii.sub.1a. Conversely, when iSC.sub.1a current input signal's polarity is negative, M2.sub.1a turns-off. Here, M1.sub.1a turns-on and steers the Ii.sub.1a, current signal into M5.sub.1a which is then mirrored through M6.sub.1a and flown onto M3.sub.1a which is mirrored again onto M4.sub.1a as Io.sub.1a, the current output of iSC.sub.1a. Concurrently, S.sub.1a provides a sign signal reflecting the negative polarity of the bipolar signal at iSC.sub.1a's input Ii.sub.1a.
(56) Note that the current mirrors M3.sub.1a-M4.sub.1a and M5.sub.1a-M6.sub.1a can be cascoded to improve the mirrors output impedance and matching. Moreover, to improve the dynamic response of the iSC.sub.1a, a small DC injection current could be provided to the mirrors (and subtracted from output) to keep the mirrors alive during zero-scale transients. Additionally, note that the amplifier functions A1.sub.1a and A2.sub.1a can utilize low cost and simple single stage common-source amplifiers (comprising of a FET and a current source each)
(57) The disclosed iSC.sub.1a operates in current mode and as such it possesses the relevant benefits listed earlier in the DETAILED DESCRIPTION introductions section the pertain to the disclosed circuits, which operate in current-mode.
Section 1BDescription of FIG. 1B
(58) FIG. 1B is a simplified circuit schematic illustrating a digital signal conditioning (dSC.sub.1b) circuit.
(59) The disclosed dSC.sub.1b embodiment illustrated in FIG. 1B operates based on sign-magnitude method of representing positive and negative numbers on both side of zero. Accordingly, the Most-Significant-Bit (MSB) of the digital input data represents the sign of the digital input date and the remaining digital input data bits represent the magnitude (or absolute value) of the digital input data. Here, dSC.sub.1b receives the digital input data Di.sub.1b that is m-bits wide. As noted, the sign of Di.sub.1b is represented by its MSB here. As such, dSC.sub.1b passes on the MSB as the (sign-bit) to the output signal S.sub.1b. The remaining sequence of m1 bits of the digital input data are coupled to the respective sequence of the first input ports of m1 Exclusive NORs (m1 of XNOR.sub.1bs). The MSB of Di.sub.1b is coupled to the second input ports of the m1 of XNOR.sub.1bs. Accordingly, dSC.sub.1b generate a m1 bits wide word, Do.sub.1b, at the m1 outputs of the XNOR.sub.1bs, which represents the magnitude word bits. Note that it would be obvious to one skilled in the art to utilize other digital binary formatting methods, including but not limited to, 2's complement, 1's complement, and offset-binary.
Section 1CDescription of FIG. 1C
(60) FIG. 1C is a simplified circuit schematic illustrating a digital polarity conditioning (dPC.sub.1c) circuit.
(61) The disclosed dPC.sub.1c embodiment illustrated in FIG. 1C also operates based on sign-magnitude method of representing positive and negative numbers on both side of zero. The dPC.sub.1c receives the digital input data Di.sub.1c that is m1 bits wide that are fed onto the respective sequence of the first input ports of m1 Exclusive NORs (m1 of XNOR.sub.1cs). The second input ports of the m1 of XNOR.sub.1cs is coupled to the S.sub.1c that is a sign-bit digital input signal. Here, S.sub.1c digital input bit is assigned the Most-Significant-Bit (MSB) of the digital out data Do.sub.1c. Accordingly, dPC.sub.1c generate a m1 bits wide word, Do.sub.1c, at the m1 outputs of the XOR.sub.1cs which is combined with the S.sub.1c signal (as Do.sub.1c's MSB) to make up the digital output word at Do.sub.1c. As stated earlier, it would be obvious to one skilled in the art to utilize other digital binary formatting methods, including but not limited to, 2's complement, 1's complement, and offset-binary, amongst others.
Section 1DDescription of FIG. 1D
(62) FIG. 1D is a simplified circuit schematic illustrating an analog current-mode polarity conditioning (iPC.sub.1d) circuit.
(63) The disclosed iPC.sub.1d embodiment illustrated in FIG. 1D receives a digital-input sign signal S.sub.1d and an analog input-current magnitude signal Ii.sub.1d. When S.sub.1d's polarity is positive, then M2.sub.1d is turned-off and M1.sub.1d is turned-on which steers Ii.sub.1d onto M3.sub.1d that is mirrored through M4.sub.1d and sourced onto an analog current output at Io.sub.1d. Conversely, when S.sub.1d's polarity is negative, then M1.sub.1d is turned-off and M2.sub.1d is turned-on which steers Ii.sub.1d through M2.sub.1d and onto an analog current output at Io.sub.1d.
(64) Note that the current mirrors M3.sub.1d-M4.sub.1d can be cascoded to improve the mirrors output impedance and matching. Moreover, to improve the dynamic response of the iPC.sub.1d, a small DC injection current could be provided to the mirrors (and subtracted from output) to keep the mirrors alive during zero-scale transients.
(65) The disclosed iPC.sub.1d operates in current mode and as such it possesses the relevant benefits listed earlier in the DETAILED DESCRIPTION introductions section that pertain to the disclosed circuits operating in current-mode.
Section 1EDescription of FIG. 1E
(66) FIG. 1E is a simplified circuit schematic illustrating another analog current-mode polarity conditioning (iPC.sub.1e) circuit.
(67) The disclosed iPC.sub.1e embodiment illustrated in FIG. 1E receives two digital-input sign signals eS.sub.1e and fS.sub.1e, and an analog input-current magnitude signal Ii.sub.1e. The pair of eS.sub.1e and fS.sub.1e polarity signals are inputted to an exclusive NOR (XNOR.sub.1e). When the output of XNOR.sub.1e's polarity is positive, then M2.sub.1e is turned-off and M1.sub.1e is turned-on which steers Ii.sub.1e onto M3.sub.1e that is mirrored through M4.sub.1e and sourced onto an analog current output at Io.sub.1e. Conversely, when the output of XNOR.sub.1e's polarity is negative, then M1.sub.1e is turned-off and M2.sub.1e is turned-on which steers Ii.sub.1e through M2.sub.1e and onto the analog current output at Io.sub.1e.
(68) Note that the current mirrors M3.sub.1e-M4.sub.1e can be cascoded to improve the mirrors output impedance and matching. Moreover, to improve the dynamic response of the iPC.sub.1e, a small DC injection current could be provided to the mirrors (and subtracted from output) to keep the mirrors alive during zero-scale transients.
(69) The disclosed iPC.sub.1e operates in current mode and as such it possesses the relevant benefits listed earlier in the DETAILED DESCRIPTION introductions section that pertain to the disclosed circuits operating in current-mode.
Section 2ADescription of FIG. 2A
(70) FIG. 2A is a simplified block diagram illustrating a mixed-mode (multi-quadrant) bipolar data-converter (BiDC) method.
(71) In the disclosed BiDC method of FIG. 2A, a bipolar-input signal E.sub.2a is inputted to a signal conditioning block (SC.sub.2a). The SC.sub.2a generate a unipolar-output signal (|E.sub.2a|) and a sign signal (eS.sub.2a). The eS.sub.2a represents the sign of the bipolar-input signal. Next, the unipolar signal |E.sub.2a| is inputted onto a unipolar-input to unipolar-output (single-quadrant) data-converter (DC.sub.2a). The DC.sub.2a converts the data that is the unipolar signal |E.sub.2a| to another form of a data that is a unipolar signal (|E.sub.2a|) at its output. Lastly, a unipolar-input to bipolar-output polarity conditioning block (PC.sub.2a) is inputted with the |E.sub.2a| and the sign signal eS.sub.2a. The PC.sub.2a generates a (multi-quadrant)E.sub.2a which is another form of the bipolar-input signal E.sub.2a. The disclosed method attains improved cost-performance advantages for utilizing unipolar data converter (combined with front-end signal conditioning and back-end polarity conditioning) to preform bipolar data conversion.
Section 2BDescription of FIG. 2B
(72) FIG. 2B is a simplified block diagram illustrating a (multi-quadrant) bipolar current-mode digital-to-analog converter (BiDAC) that utilizes the BiDC method disclosed in Section 2A.
(73) In the disclosed embodiment of FIG. 2B, a digital-input signal E.sub.2b is inputted to a digital-input to digital-output signal conditioning block (SC.sub.2b). The SC.sub.2b can utilize a circuit embodiment such as (dSC.sub.1b) that is disclosed in section 1B and illustrated in FIG. 1B. As such, the dSC.sub.2b generate a digital-output magnitude signal (|E.sub.2b|) that is m1 bits wide. The dSC.sub.2b also generate a sign signal (eS.sub.2b), which is the MSB of the digital-input signal E.sub.2b. The m1 bits wide digital magnitude signal |E.sub.2b| is inputted to a (single-quadrant) unipolar iDAC.sub.2b's digital input port Di.sub.2b that is also m1 bits wide. Concurrently, the unipolar iDAC.sub.2b receives a reference current signal (G.sub.2b) at its reference input port Ref.sub.2b. Next, the unipolar iDAC.sub.2b generates a unipolar (magnitude) analog current output signal (|E.sub.2b|) at its current output port Ao.sub.2b. Note that |E.sub.2b| represents the analog form of the magnitude portion of the digital-input signal E.sub.2b. Then, the unipolar magnitude analog current signal |E.sub.2b| is inputted onto an analog current mode polarity conditioning block (iPC.sub.2b). The iPC.sub.2b can utilize a circuit embodiment such as (iPC.sub.1d) that is disclosed in section 1D and illustrated in FIG. 1D. The iPC.sub.2b also receives the sign signal eS.sub.2b. Thus, the iPC.sub.2b generates a (multi-quadrant) bipolar analog current output signal E.sub.2b, which represents a (multi-quadrant) bipolar analog from of the digital-input signal E.sub.2b.
(74) As stated earlier, it would be obvious to one skilled in the art to utilize other digital binary formatting methods, including but not limited to, 2's complement, 1's complement, and offset-binary.
(75) The disclosed BiDAC of FIG. 2B operates in current mode and as such it possesses the relevant benefits listed earlier in the DETAILED DESCRIPTION introductions section the pertain to the disclosed circuits that operate in current-mode. Also, a unipolar iDAC is generally smaller, faster, lower power, and less complex than for example a bipolar iDAC. Accordingly, to perform digital-input to bipolar-analog-output data-conversion, a combined digital signal conditioning (dSC) plus a unipolar iDAC plus analog polarity conditioning (iPC) circuits can provide improved cost-performance traits as compared to a bipolar iDAC.
Section 2CDescription of FIG. 2C
(76) FIG. 2C is a simplified block diagram illustrating a (multi-quadrant) bipolar current-mode analog-to-digital converter (BiADC) that utilizes the BiDC method disclosed in Section 2A.
(77) In the disclosed embodiment of FIG. 2C, a bipolar analog current input signal E.sub.2c is inputted to an analog-input to analog-output signal conditioning block (iSC.sub.2c). The iSC.sub.2c can utilize a circuit embodiment such as iSC.sub.1a that is disclosed in section 1A and illustrated in FIG. 1A. As such, the iSC.sub.2c generate a unipolar analog-output current magnitude signal (|E.sub.2c|). The iSC.sub.2, also generate a sign signal (eS.sub.2c), which indicates the polarity of the digital-input signal E.sub.2c. Then unipolar analog current magnitude signal |E.sub.2c| is inputted to a (single-quadrant) unipolar iADC.sub.2c's analog current input port Ai.sub.2c. Concurrently, the unipolar iADC.sub.2c receives a reference current signal (G.sub.2c) at its reference input port Ref.sub.2c. Next, the unipolar iADC.sub.2c generates a unipolar (magnitude) digital output signal (|E.sub.2c|) at its digital output port Do.sub.2c. Note that |E.sub.2c| represents the digital form of the magnitude portion of the bipolar analog-input signal E.sub.2c. Then, the unipolar magnitude analog current signal |E.sub.2c| is inputted onto a digital polarity conditioning block (dPC.sub.2c). The dPC.sub.2c can utilize a circuit embodiment such as (dPC.sub.1d) that is disclosed in section 1C and illustrated in FIG. 1C. The dPC.sub.2c also receives the sign signal eS.sub.2c that is the MSB of the digital-output word. Thus, the dPC.sub.2c generates a digital output word (signal) E.sub.2c, which represents a digital from of the bipolar analog input signal E.sub.2c.
(78) As stated earlier, it would be obvious to one skilled in the art to utilize other digital binary formatting methods, including but not limited to, 2'a complement, 1's complement, and offset-binary.
(79) The disclosed BiADC of FIG. 2C operates in current mode and as such it possesses the relevant benefits listed earlier in the DETAILED DESCRIPTION section. Also, a unipolar iADC is generally smaller, faster, lower power, and less complex than a bipolar iADC. Accordingly, to perform digital-input to bipolar-analog-output data-conversion, a combined digital signal conditioning (dSC) plus a unipolar iADC plus an analog polarity conditioning (iPC) circuits can provide improved cost-performance traits as compared to a bipolar iADC.
Section 3ADescription of FIG. 3A
(80) FIG. 3A is a simplified block diagram illustrating a multi-quadrant multiplier (qMULT) method.
(81) In the disclosed qMULT method of FIG. 3A, an E bipolar input signal (E.sub.3a) is inputted to an E signal conditioning block (SCE.sub.3a). The SCE.sub.3a, generate an E unipolar signal (|E.sub.3a|). The SCE.sub.3a, also generates an E sign signal (eS.sub.3a), which indicates the polarity of the E bipolar input signal E.sub.3a. Similarly, a F bipolar input signal (F.sub.3a) is inputted to a F signal conditioning block (SCF.sub.3a). The SCF.sub.3a, generate a F unipolar signal (|F.sub.3a|). The SCF.sub.3a, also generates a F sign signal (fS.sub.3a), which indicates the polarity of the F bipolar input signal F.sub.3a. Then, a single-quadrant multiplier block (MULT.sub.3a) receives the unipolar signals |E.sub.3a| and |F.sub.3a|. The MULT.sub.3a generates a single-quadrant (unipolar) product signal |E.sub.3a||F.sub.3a, |/G.sub.3a, wherein G.sub.3a is a reference signal. Next, the single-quadrant product signal |E.sub.3a||F.sub.3a|/G.sub.3a is inputted to a polarity conditioning block (PC.sub.3a). The PC.sub.3a, also receives the E and F sign signals, eS.sub.3a and fS.sub.3a and generates a multi-quadrant product signal E.sub.3aF.sub.3a/G.sub.3a. Compared to a more complicated, bigger, and slower multi-quadrant multiplier that perform multi-quadrant multiplication, the disclosed method utilizes a simpler, smaller, and faster single-quadrant multiplier (combined with front-end signal conditioning and back-end polarity conditioning functions) to preform multi-quadrant multiplication.
Section 3BDescription of FIG. 3B
(82) FIG. 3B is a simplified block diagram illustrating a multi-quadrant analog current-input to analog current-output multiplier (qiMULT.sub.3b) utilizing the qMULT method disclosed in section 3A.
(83) In the disclosed qiMULT.sub.3b of FIG. 3B, an E bipolar current input signal (E.sub.3b) is inputted to an E current signal conditioner (iSCE.sub.3b). The iSCE.sub.3b can utilize a circuit embodiment such as iSC.sub.1a that is disclosed in section 1A and illustrated in FIG. 1A. The SCE.sub.3b generate an E unipolar output current signal (|E.sub.3b|). The SCE.sub.3b also generates an E sign signal (eS.sub.3b), which indicates the polarity of the E bipolar current input signal E.sub.3b. Similarly, a F bipolar current input signal (F.sub.3b) is inputted to a F current signal conditioner (iSCF.sub.3b). Additionally, the iSCF.sub.3b can utilize a circuit embodiment such as iSC.sub.1a that is disclosed in section 1A and illustrated in FIG. 1A. The iSCF.sub.3b generate a F unipolar current signal (|F.sub.3b|). The iSCF.sub.3b also generates a F sign signal (fS.sub.3b), which indicates the polarity of the F bipolar current input signal F.sub.3b. Utilizing identical circuits for iSCF.sub.3b and iSCF.sub.3b would improve matching between E and F current signal conditioning paths. Then, a single-quadrant current multiplier (iMULT.sub.3b) receives the unipolar current signals |E.sub.3b| and |F.sub.3b|. The iMULT.sub.3b generates a single-quadrant (unipolar) product current signal |E.sub.3b||F.sub.3b|/G.sub.3b, wherein G.sub.3b is a reference current signal. Next, the single-quadrant product current signal |E.sub.3b||F.sub.3b|/G.sub.3b is inputted to a current-mode polarity conditioner (iPC.sub.3b). The iPC.sub.3b can utilize a circuit embodiment such as iPC.sub.1e that is disclosed in section 1E and illustrated in FIG. 1E. The iPC.sub.3b also receives the E and F sign signals, eS.sub.3b and fS.sub.3b and generates a multi-quadrant product current signal E.sub.3bF.sub.3b/G.sub.3b.
(84) Refer to section 3G and FIG. 3G which is a circuit simulation describing and illustrating the input-output waveforms of the qiMULT.sub.3b of FIG. 3B.
(85) Additionally, refer to section 4A and FIG. 4A which discloses a multiple-channel multi-quadrant analog current-input to current-output scalar multiplier (SqiMULT.sub.4A) that utilizes plurality of qiMULT.sub.3b.
(86) The disclosed qiMULT.sub.3b of FIG. 3B operates in current mode and as such it possesses the relevant benefits listed earlier in the DETAILED DESCRIPTION section. Moreover, as compared to a more complicated, bigger, and slower multi-quadrant current mode multiplier, the disclosed method utilizes a simpler, smaller, and faster single-quadrant multiplier (combined with front-end signal conditioning and back-end polarity conditioning circuits) to preform multi-quadrant multiplication.
Section 3CDescription of FIG. 3C
(87) FIG. 3C is a simplified block diagram illustrating a multi-quadrant digital input to analog current output multiplier (qiMULT.sub.3c) utilizing the qMULT method disclosed in section 3A.
(88) In the disclosed qiMULT.sub.3c of FIG. 3C, an E digital input signal (E.sub.3c), which is m bits wide, is inputted to an E digital signal conditioner (dSCE.sub.3c), which operates in sign-magnitude method. As stated earlier, besides the sign-magnitude method, it would be obvious to one skilled in the art to utilize other digital binary formatting methods, including but not limited to, 2's complement, 1's complement, and offset-binary, amongst others. The dSCE.sub.3, can utilize a circuit embodiment such as dSC.sub.1b that is disclosed in section 1B and illustrated in FIG. 1B. The dSCE.sub.3c generate a magnitude E digital signal (|E.sub.3c|), which is m1 bits wide. The dSCE.sub.3c also generates an E digital sign signal (eS.sub.3c), which indicates the polarity of the E digital input signal E.sub.3c, which is the MSB of the E.sub.3c digital signal.
(89) Similarly, a F digital input signal that is m-bits wide (F.sub.3c) is inputted to a F digital signal conditioner (dSCF.sub.3c). Moreover, the dSCF.sub.3c can utilize a circuit embodiment such as dSC.sub.1b that is disclosed in section 1B and illustrated in FIG. 1B. The dSCF.sub.3c generate a magnitude F digital signal (|F.sub.3c|), which is m1 bits wide. The dSCF.sub.3c also generates a F sign signal (fS.sub.3c), which indicates the polarity of the F digital input signal F.sub.3c, which is the MSB of the F.sub.3c digital signal.
(90) Then, the |E.sub.3c| and |F.sub.3c| magnitude digital signals are inputted to a pair single-quadrant iDACs configured in multiplying DAC mode, as follows: An E single-quadrant iDACE.sub.3c receives a reference current signal G.sub.3c at its' current reference port RefE.sub.3c. The iDACE.sub.3c receives the E magnitude digital signals |E.sub.3c| at its digital input port DiE.sub.3c, and generates an E analog unipolar current signal |E.sub.3c| at its current output port (AoE.sub.3c). Concurrently, a F single-quadrant iDACF.sub.3c receives (as its reference current signal) the |E.sub.3| from iDACE.sub.3c at its' current reference port RefF.sub.3c. Concurrently, the iDACF.sub.3c receives the F magnitude digital signals |F.sub.3c| at its digital input port DiF.sub.3c, and generates a F analog unipolar current signal at its current output port (AoF.sub.3c). This single-quadrant (unipolar) analog current signal at the AoF.sub.3c output port is a single-quadrant (unipolar) product current signal representing |E.sub.3c||F.sub.3c|/G.sub.3c, wherein G.sub.3c is a reference current signal.
(91) Next, the single-quadrant product current signal |E.sub.3c||F.sub.3c|/G.sub.3c is inputted to a current-mode polarity conditioner (iPC.sub.3c). The iPC.sub.3c can utilize a circuit embodiment such as iPC.sub.1e that is disclosed in section 1E and illustrated in FIG. 1E. The iPC.sub.3c also receives the E and F sign signals, eS.sub.3c and fS.sub.3c and generates a multi-quadrant product current signal E.sub.3cF.sub.3c/G.sub.3c.
(92) Refer to section 3E and FIG. 3E which is a circuit simulation describing and illustrating the input-output waveforms of the qiMULT.sub.3c of FIG. 3C.
(93) Moreover, refer to section 4B and FIG. 4B which discloses a multiple-channel multi-quadrant mixed-mode digital-input to current-output scalar multiplier (SqiMULT.sub.4b) that utilizes plurality of qiMULT.sub.3c.
(94) The disclosed qiMULT.sub.3c of FIG. 3C operates in current mode and as such it possesses the relevant benefits listed earlier in the DETAILED DESCRIPTION section. Also, as compared to a more complicated, bigger, and slower multi-quadrant current mode multiplier, the disclosed method utilizes a simpler, smaller, and faster single-quadrant multiplier (combined with front-end signal conditioning and back-end polarity conditioning circuits) to preform multi-quadrant multiplication.
Section 3DDescription of FIG. 3D
(95) FIG. 3D is a simplified block diagram illustrating another multi-quadrant analog current-input to analog current-output multiplier (qiMULT.sub.3d) utilizing the qMULT method disclosed in section 3A.
(96) In the disclosed qiMULT.sub.3d of FIG. 3D, an E analog current-input signal (E.sub.3d), that is inputted to an E analog current signal conditioner (iSCE.sub.3d). The iSCE.sub.3d can utilize a circuit embodiment such as iSC.sub.1a that is disclosed in section 1A and illustrated in FIG. 1A. The iSCE.sub.3d generate a unipolar current signal (|E.sub.3d|). The iSCE.sub.3d also generates an E digital sign signal (eS.sub.3d), which indicates the polarity of the E.sub.3d.
(97) Similarly, an F analog current-input signal (F.sub.3d) is inputted to an F analog current signal conditioner (iSCF.sub.3d). Furthermore, the iSCF.sub.3d can utilize a circuit embodiment such as iSC.sub.1a that is disclosed in section 1A and illustrated in FIG. 1A. The iSCF.sub.3d generate a unipolar current signal (|F.sub.3d|). The iSCF.sub.3d also generates a F sign signal (fS.sub.3d), which indicates the polarity of the F.sub.3d.
(98) Then, the |E.sub.3d| and |F.sub.3d| unipolar analog current signals are inputted to single-quadrant iADC and iDAC to perform a single quadrant multiplication as follows: A single-quadrant iADC.sub.3d receives a reference current signal G.sub.ad at its' current reference port RefE.sub.3d. The iADC.sub.3d receives the unipolar analog current signals |E.sub.3d| at its analog input port AiE.sub.3d, and generates a m1 bits wide digital signal |E.sub.3d| at its digital output port (DoE.sub.3d). Concurrently, a F single-quadrant iDAC.sub.3d receives a reference current signal |F.sub.3d| from iSCF.sub.3d at its' current reference port RefF.sub.3d. The iDAC.sub.3d receives the F magnitude digital signal |E.sub.3d| at its digital input port DiF.sub.3d, and generates an analog unipolar current signal at its current output port (AoF.sub.3d). This single-quadrant (unipolar) analog current signal at the AoF.sub.3d is a single-quadrant (unipolar) product current signal |E.sub.3d||F.sub.3d|/G.sub.3d, wherein G.sub.ad is a reference current signal.
(99) Next, the single-quadrant product current signal |E.sub.3d||F.sub.3d|/G.sub.3d is inputted to a current-mode polarity conditioner (iPC.sub.3d). The iPC.sub.3d can utilize a circuit embodiment such as iPC.sub.1e that is disclosed in section 1E and illustrated in FIG. 1E. The iPC.sub.3d also receives the E and F sign signals, eS.sub.3d and fS.sub.3d and generates a multi-quadrant product current signal E.sub.3dF.sub.3d/G.sub.3d.
(100) Refer to section 3F and FIG. 3F which is a circuit simulation describing and illustrating the input-output waveforms of the qiMULT.sub.3d of FIG. 3D.
(101) Furthermore, refer to section 4C and FIG. 4C which discloses a multiple-channel multi-quadrant mixed-mode current-input to current-output scalar multiplier (SqiMULT.sub.4c) that utilizes plurality of qiMULT.sub.3d.
(102) The disclosed qiMULT.sub.3d of FIG. 3D operates in current mode and as such it possesses the relevant benefits listed earlier in the DETAILED DESCRIPTION section. Additionally, as compared to a more complicated, bigger, and slower multi-quadrant current mode multiplier, the disclosed method utilizes a simpler, smaller, and faster single-quadrant multiplier (combined with front-end signal conditioning and back-end polarity conditioning) to preform multi-quadrant multiplication.
Section 3EDescription of FIG. 3E
(103) FIG. 3E, including an upper-graph and a lower-graph, is a SPICE circuit simulation showing the input-output and linearity waveforms of the multi-quadrant digital input to analog current output multiplier (qiMULT.sub.3c) of FIG. 3C in section 3C.
(104) For illustrative clarity, the digital input signals E.sub.3c and F.sub.3c of qiMULT.sub.3c of FIG. 3C are fed into an ideal iDAC to provide their analog current signal equivalents I.sub.E and I.sub.E, respectively, that are plotted and marked in the lower-graph of FIG. 3E. The E.sub.3c and F.sub.3c digital input signals (and their representative analog current signals I.sub.E and I.sub.F) are ramped up and down, respectively, between negative-full-scale (indicated as 0 on the vertical axis of lower-graph of FIG. 3E) and positive-full-scale (indicated as +1 on the vertical axis of lower-graph of FIG. 3E). The zero-scale is depicted as point on the vertical axis of the lower-graph of FIG. 3E. Additionally, an ideal multiplication result Io.sub.ideal=I.sub.EI.sub.E/I.sub.R is plotted and marked in the lower-graph of FIG. 3E, wherein I.sub.R is the reference current signal G.sub.3c.
(105) In FIG. 3C in section 3C, the output of qiMULT.sub.3c (which is the output of iPC.sub.3c) is Io.sub.sim. For illustrative clarity of FIG. 3E and to avoid overlapping Io.sub.ideal over Io.sub.sim, the Io.sub.sim is inverted, and plotted in the lower-graph of FIG. 3E. The Io.sub.sim in FIG. 3E represents the multi-quadrant product output current signal E.sub.3cF.sub.3c/G.sub.3c of FIG. 3C.
(106) The upper-graph of FIG. 3E is a plot of the linearity error in % of full scale that is the difference between the Io.sub.ideal and Io.sub.sim (the output current signal of the qiMULT.sub.3c simulated results). Note that the single-quadrant iDACE.sub.3c and iDACF.sub.3c of FIG. 3C each have 6-bits of resolution (m=6), whose LSB amounts to .sup.6=1.6% of full-scale. Furthermore, note that for illustrative clarity the iDACE.sub.3c and iDACF.sub.3c gain errors and offset are adjusted for (with respect to full-scale). As shown in the upper-graph of FIG. 3E is a plot of the linearity error in % of the multi-quadrant digital input to analog current output multiplier (qiMULT.sub.3c) that peaks to about 1.6% at the two full-scale ends (note that 1.fwdarw.+1 full-scale for FIG. 3E is illustrated based on 0.fwdarw.1 full-scale).
Section 3FDescription of FIG. 3F
(107) FIG. 3F, including an upper-graph and a lower-graph, is a SPICE circuit simulation showing the input-output and linearity waveforms of the multi-quadrant digital input to analog current output multiplier (qiMULT.sub.3d) of FIG. 3D in section 3D.
(108) The input current signals E.sub.3d and F.sub.3d of qiMULT.sub.3d of FIG. 3D are marked as I.sub.E and I.sub.F, respectively, in the lower-graph of FIG. 3F. The E.sub.3d and F.sub.3d digital input signals (i.e., I.sub.E and I.sub.F) are ramped up and down, respectively, between negative-full-scale (indicated as 1 on the vertical axis of lower-graph of FIG. 3F) and positive-full-scale (indicated as +1 on the vertical axis of lower-graph of FIG. 3F). The zero-scale is depicted as 0 point on the vertical axis of the lower-graph of FIG. 3F. Moreover, an ideal multiplication result Io.sub.ideal=I.sub.EI.sub.F/I.sub.R is plotted and marked in the lower-graph of FIG. 3F, wherein I.sub.R is the reference current signal G.sub.ad.
(109) In FIG. 3D in section 3D, the output of qiMULT.sub.3d (which is the output of iPC.sub.3d) is Io.sub.sim. For illustrative clarity of FIG. 3F and to avoid overlapping Io.sub.ideal over Io.sub.sim, the Io.sub.sim is inverted, and plotted in the lower-graph of FIG. 3D. The Io.sub.sim in FIG. 3F represents the multi-quadrant product output current signal E.sub.3dF.sub.3d/G.sub.3d of FIG. 3D.
(110) The upper-graph of FIG. 3F is a plot of the linearity error in % of full scale that is the difference between the Io.sub.ideal and Io.sub.sim which is the output current signal of the qiMULT.sub.3d simulated results. Note that the single-quadrant iADCE.sub.3d and iDACF.sub.3d of FIG. 3D each have 4-bits of resolution (m=4), whose LSB amounts to .sup.4=6.25% of full-scale. Additionally, note that for illustrative clarity the iADCE.sub.3d and iDACF.sub.3d gain errors and offset are adjusted for (with respect to full-scale). As shown in the upper-graph of FIG. 3F is a plot of the linearity error in % of the multi-quadrant analog input to analog current output multiplier (qiMULT.sub.3d) that peaks to about 6% at the two negative and positive full-scale ends.
Section 3GDescription of FIG. 3G
(111) FIG. 3G, including an upper-graph, a middle-graph, and a lower-graph, is a SPICE circuit simulation showing the input-output and linearity waveforms of the multi-quadrant digital input to analog current output multiplier (qiMULT.sub.3b) of FIG. 3B in section 3B.
(112) The input current signals E.sub.3b and F.sub.3b of qiMULT.sub.3b of FIG. 3B are marked as I.sub.E and I.sub.F, respectively, in the lower-graph of FIG. 3G. The E.sub.3b and F.sub.3b digital input signals (i.e., I.sub.E and I.sub.F) are ramped up and down, respectively, between negative-full-scale (indicated as 1 on the vertical axis of lower-graph of FIG. 3G) and positive-full-scale (indicated as +1 on the vertical axis of lower-graph of FIG. 3G). The zero-scale is depicted as 0 point on the vertical axis of the lower-graph of FIG. 3G. Also, an ideal multiplication result Io.sub.ideal=I.sub.E|.sub.F/I.sub.R is plotted and marked in the lower-graph of FIG. 3G, wherein I.sub.R is the reference current signal G.sub.3b. Note that for clarity of illustration, Io.sub.ideal is plotted with small offset to avoid graphical overlap with Io.sub.sim.
(113) Moreover, Io.sub.sim that is the output signal of qiMULT.sub.3b of FIG. 3B in section 3B is also plotted in the lower-graph of FIG. 3G. The output signal of qiMULT.sub.3b is a SPICE circuit simulation in the lower-graph of FIG. 3G that graphs Io.sub.sim which represents the simulated multi-quadrant product output current signal E.sub.3bF.sub.3b/G.sub.3b of FIG. 3B.
(114) The middle-graph of FIG. 3G is a plot of power supply current consumption (I.sub.DD). Note that the iMULT.sub.3b utilized in this simulation operates in the subthreshold region which contributes to ultra-low I.sub.DD spanning from about 200 nA to 100 nA, depending on I.sub.E and I.sub.F values.
(115) The upper-graph of FIG. 3G is a plot of the linearity error in % of full scale that is the difference between the Io.sub.ideal and Io.sub.sim, which is the output current signal of the qiMULT.sub.3b simulated results. The linearity error in % is plotted with positive power supply (V.sub.DD) ranging from V.sub.DD=1v to V.sub.DD=0.8v to V.sub.DD=0.7v, which indicates performance to specification in sub-1V power supply conditions, while the input signals I.sub.E and I.sub.F span between positive to negative full-scale ranges. Note that the single-quadrant CMOS iMULT.sub.3b of FIG. 3B that operates in the subthreshold region simulations indicates a linearity of about 1% (note that the single-quadrant CMOS iMULT.sub.3b is not shown by itself). As shown in the upper-graph of FIG. 3G is a plot of the linearity error in % of the multi-quadrant analog input to analog current output multiplier (qiMULT.sub.3d) also peaks to about 1% (adjusted for iMULT.sub.3b's gain error) between the two negative and positive full-scale ends.
Section 4ADescription of FIG. 4A
(116) FIG. 4A illustrates a multiple-channel multi-quadrant analog current-input to current-output scalar multiplier (SqiMULT.sub.4a)
(117) As stated earlier, SqiMULT.sub.4A of FIG. 4A utilizes plurality of qiMULT.sub.3b illustrated earlier in FIG. 3B and disclosed in section 3B. Additionally, refer to section 3G and FIG. 3G which is a circuit simulation describing and illustrating the input-output waveforms of the qiMULT.sub.3b of FIG. 3B that is utilized here in FIG. 4A.
(118) In the disclosed SqiMULT.sub.4a of FIG. 4A, an E bipolar current input signal (E.sub.4a that is a scalar signal) is inputted to an E current signal conditioner (iSCE.sub.4a). The iSCE.sub.4a can utilize a modified version of the circuit embodiment such as iSC.sub.1a that is disclosed in section 1A. To facilitate multiplying a scalar signal E.sub.4a to a plurality of signals (e.g., p=3 as in three channels F1.sub.4a, F2.sub.4a, F3.sub.4a), the iSC.sub.1a of FIG. 1A can be re-arranged with three additional same size FETs in parallel with M4.sub.1a to generate three replicates of |E.sub.4a|. The iSCE.sub.4a also generates an E sign signal (eS.sub.4a), which indicates the polarity of the E.sub.4a.
(119) Note that number of channels can be a sea of channels (plurality>2) depending on the end-application, but for descriptive clarity, 3-channels are illustrated and describe here.
(120) In the first channel, a F1 bipolar current input signal (F1.sub.4a) is inputted to a F1 current signal conditioner (iSCH.sub.4a). Moreover, the iSCH.sub.4a can utilize a circuit embodiment such as iSC.sub.1a that is disclosed in section 1A and illustrated in FIG. 1A. The iSCH.sub.4a generate a F1 unipolar current signal (|F1.sub.4a|). The iSCH.sub.4a also generates a F1 sign signal (fS1.sub.4a), which indicates the polarity of the F1.sub.4a. Then, a single-quadrant current multiplier (iMULT1.sub.4a) is inputted with the |F1.sub.4a| and the (scalar signal which is the) unipolar current signals |E.sub.4a|. Accordingly, the iMULT1.sub.4a generates a single-quadrant (unipolar) product current signal that represents |E.sub.4a||F1.sub.4a|/G.sub.4a, wherein G.sub.4a is a reference current signal. Next, the single-quadrant product current signal |E.sub.4a||F1.sub.4a|/G.sub.4a is inputted to a current-mode polarity conditioner (iPC1.sub.4a). The iPC1.sub.4a can utilize a circuit embodiment such as iPC.sub.1e that is disclosed in section 1E and illustrated in FIG. 1E. The iPC1.sub.4a is also inputted with the E and F1 sign signals, eS.sub.4a and fS1.sub.4a, and it generates a multi-quadrant product current signal that represents E.sub.4aF1.sub.4a/G.sub.4a.
(121) In the second channel, a F2 bipolar current input signal (F2.sub.4a) is inputted to a F2 current signal conditioner (iSCF2.sub.4a). Moreover, the iSCF2.sub.4a can utilize a circuit embodiment such as iSC.sub.1a that is disclosed in section 1A and illustrated in FIG. 1A. The iSCF2.sub.14a generate a F2 unipolar current signal (|F2.sub.4a|). The iSCF2.sub.4a also generates a F2 sign signal (fS2.sub.4a), which indicates the polarity of the F2.sub.4a. Then, a single-quadrant current multiplier (iMULT2.sub.4a) is inputted with the |F2.sub.4a| and the (scalar signal which is the) unipolar current signals |E.sub.4a|. Accordingly, the iMULT2.sub.4a generates a single-quadrant (unipolar) product current signal that represents |E.sub.4a||F2.sub.4a|/G.sub.4a, wherein G.sub.4a is a reference current signal. Next, the single-quadrant product current signal |E.sub.4a||F2.sub.4a|/G.sub.4a is inputted to a current-mode polarity conditioner (iPC2.sub.4a). The iPC2.sub.4a can utilize a circuit embodiment such as iPC.sub.1e that is disclosed in section 1E and illustrated in FIG. 1E. The iPC2.sub.4a is also inputted with the E and F2 sign signals, eS.sub.4a and fS2.sub.4a, and it generates a multi-quadrant product current signal that represents E.sub.4aF2.sub.4a/G.sub.4a.
(122) In the third channel, a F3 bipolar current input signal (F3.sub.4a) is inputted to a F3 current signal conditioner (iSCF3.sub.4a). Moreover, the iSCF3.sub.4a can utilize a circuit embodiment such as iSC.sub.1a that is disclosed in section 1A and illustrated in FIG. 1A. The iSCF3.sub.14a generate a F3 unipolar current signal (|F3.sub.4a|). The iSCF3.sub.4a also generates a F3 sign signal (fS3.sub.4a), which indicates the polarity of the F3.sub.4a. Then, a single-quadrant current multiplier (iMULT3.sub.4a) is inputted with the |F3.sub.4a| and the (scalar signal which is the) unipolar current signals |E.sub.4a|. Accordingly, the iMULT3.sub.4a generates a single-quadrant (unipolar) product current signal that represents |E.sub.4a||F3.sub.4a|/G.sub.4a, wherein G.sub.4a is a reference current signal. Next, the single-quadrant product current signal |E.sub.4a||F3.sub.4a|/G.sub.4a is inputted to a current-mode polarity conditioner (iPC3.sub.4a). The iPC3.sub.4a can utilize a circuit embodiment such as iPC.sub.1e that is disclosed in section 1E and illustrated in FIG. 1E. The iPC3.sub.4a is also inputted with the E and F3 sign signals, eS.sub.4a and fS3.sub.4a, and it generates a multi-quadrant product current signal that represents E.sub.4aF3.sub.4a/G.sub.4a.
(123) The disclosed SqiMULT.sub.4a of FIG. 4A operates in current mode and as such it possesses the relevant benefits listed earlier in the DETAILED DESCRIPTION section. Moreover, as compared to a more complicated, bigger, and slower multi-quadrant current mode multiplier, the disclosed method utilizes a simpler, smaller, and faster single-quadrant multiplier (combined with front-end signal conditioning and back-end polarity conditioning) to preform multi-quadrant multiplication. Additionally, matching between the plurality of channel outputs is improved since identical arrangements for iPC1.sub.4a-iPC2.sub.4a-iPC3.sub.4a, and identical arrangements for iMULT1.sub.4a-iMULT2.sub.4a-iMULT3.sub.4a, and identical arrangements for iSCE.sub.4a-iSCH.sub.4a-iSCF2.sub.4a-iSCF3.sub.4a can be utilized in SqiMULT.sub.4a.
Section 4BDescription of FIG. 4B
(124) FIG. 4B illustrates a multiple-channel multi-quadrant digital-input to current-output scalar multiplier (SqiMULT.sub.4b).
(125) As stated earlier, SqiMULT.sub.4b of FIG. 4B utilizes plurality of qiMULT.sub.3c illustrated earlier in FIG. 3C and disclosed in section 3C. Please refer to section 3E and FIG. 3E which is a circuit simulation describing and illustrating the input-output waveforms of the qiMULT.sub.3c of FIG. 3C that is utilized here in FIG. 4B.
(126) In the disclosed SqiMULT.sub.4b of FIG. 4B, an E digital-input signal (E.sub.4b), which is m bits wide, is inputted to an E digital signal conditioner (dSCE.sub.4b), which operates in sign-magnitude method. Note that E.sub.4b is the scalar signal that can be multiplied with plurality of signals (e.g., F1.sub.4b, F2.sub.4b, F3.sub.4b, and so on), which will be described shortly. As stated earlier, besides the sign-magnitude method, it would be obvious to one skilled in the art to utilize other digital binary formatting methods, including but not limited to, 2's complement, 1's complement, and offset-binary, amongst others. The dSCE.sub.4b can utilize a circuit embodiment such as dSC.sub.1b that is disclosed in section 1B and illustrated in FIG. 1B. The dSCE.sub.4b generates a magnitude E digital signal (|E.sub.4b|), which is m1 bits wide. The dSCE.sub.4b also generates an E digital sign signal (eS.sub.4b), which indicates the polarity of the E.sub.4b, which is the MSB of the E.sub.4b digital signal here. An E single-quadrant iDACE.sub.4b receives a reference current signal G.sub.4b at its' current reference port RefE.sub.4b. The iDACE.sub.4b receives the E magnitude digital signals |E.sub.4b| at its digital input port DiE.sub.4b, and generates an E analog unipolar current signal |E.sub.4b| at its current output port (AoE.sub.4b). The unipolar current signal |E.sub.4b| can be replicated (e.g., via a current mirror) plurality of instances (e.g., p=3) to provide the scalar signal (|E.sub.4b|) to be multiplied with plurality of signals (e.g., |F1.sub.4b|, |F2.sub.4b|, and |F3.sub.4b|), which will be described next.
(127) Note that number of channels can be a sea of channels (plurality >2) depending on the end-application, but for clarity's sake 3-channels are illustrated and describe here.
(128) In the first channel, a F1 digital input signal that is m-bits wide (F1.sub.4b) is inputted to a F1 digital signal conditioner (dSCF1.sub.4b). The dSCF1.sub.4b can utilize a circuit embodiment such as dSC.sub.1b that is disclosed in section 1B and illustrated in FIG. 1B. The dSCF1.sub.4b generate a magnitude digital signal (|F1.sub.4b|), which is m1 bits wide. The dSCF1.sub.4b also generates a sign signal (fS1.sub.4b) that is the MSB of the F1.sub.4b digital signal, which indicates the polarity of the digital input signal F1.sub.4b. Concurrently, the current signal |E.sub.4b| from iDACE.sub.4b's output is inputted to a current reference port RefF1.sub.4b of a single-quadrant iDACF1.sub.4b. The magnitude digital signal |F1.sub.4b| is inputted to the digital input port DiF1.sub.4b of the iDACF1.sub.4b, which generates an analog unipolar current signal at iDACF1.sub.4b's current output port (AoF1.sub.4b). This signal at AoF1.sub.4b port represents |E.sub.4b||F1.sub.4b|/G.sub.4b, wherein G.sub.4b is a reference current signal. Next, the unipolar product current signal |E.sub.4b||F1.sub.4b|/G.sub.4b is inputted to a current-mode polarity conditioner (iPC1.sub.4b). The iPC1.sub.4b can utilize a circuit embodiment such as iPC.sub.1e that is disclosed in section 1E and illustrated in FIG. 1E. The iPC1.sub.4b also receives the E and F1 sign signals, eS.sub.4b and fS1.sub.4b, and accordingly generates a multi-quadrant product current signal that represents E.sub.4bF1.sub.4b/G.sub.4b.
(129) In the second channel, a F2 digital input signal that is m-bits wide (F2.sub.4b) is inputted to a F2 digital signal conditioner (dSCF2.sub.4b). The dSCF2.sub.4b can also utilize a circuit embodiment such as dSC.sub.1b that is disclosed in section 1B and illustrated in FIG. 1B. The dSCF2.sub.4b generate a magnitude digital signal (|F2.sub.4b|), which is m1 bits wide. The dSCF2.sub.4b also generates a sign signal (fS2.sub.4b) that is the MSB of the F2.sub.4b digital signal, which indicates the polarity of the digital input signal F2.sub.4b. Concurrently, the current signal |E.sub.4b| from iDACE.sub.4b's output is inputted to a current reference port RefF2.sub.4b of a single-quadrant iDACF2.sub.4b. The magnitude digital signal |F2.sub.4b| is inputted to the digital input port DiF2.sub.4b of the iDACF2.sub.4b, which generates an analog unipolar current signal at iDACF2.sub.4b's current output port (AoF2.sub.4b). This signal at AoF2.sub.4b port represents I.sub.4b||F2.sub.4b|/G.sub.4b, wherein G.sub.4b is a reference current signal. Next, the unipolar product current signal |E.sub.4b||F2.sub.4b|/G.sub.4b is inputted to a current-mode polarity conditioner (iPC2.sub.4b). The iPC2.sub.4b can utilize a circuit embodiment such as iPC.sub.1e that is disclosed in section 1E and illustrated in FIG. 1E. The iPC2.sub.4b also receives the E and F2 sign signals, eS.sub.4b and fS2.sub.4b and generates a multi-quadrant product current signal that represents E.sub.4bF2.sub.4b/G.sub.4b.
(130) In the third channel, a F3 digital input signal that is m-bits wide (F3.sub.4b) is inputted to a F3 digital signal conditioner (dSCF3.sub.4b). The dSCF3.sub.4b can also utilize a circuit embodiment such as dSC.sub.1b that is disclosed in section 1B and illustrated in FIG. 1B. The dSCF3.sub.4b generate a magnitude digital signal (|F3.sub.4b|), which is m1 bits wide. The dSCF3.sub.4b also generates a sign signal (fS3.sub.4b) that is the MSB of the F3.sub.4b digital signal, which indicates the polarity of the digital input signal F3.sub.4b. Concurrently, the current signal |E.sub.4b| from iDACE.sub.4b 's output is also inputted to a current reference port RefF3.sub.4b of a single-quadrant iDACF3.sub.4b. The magnitude digital signal |F3.sub.4b| is inputted to the digital input port DiF3.sub.4b of the iDACF3.sub.4b, which generates an analog unipolar current signal at iDACF3.sub.4b's current output port (AoF3.sub.4b). This signal at AoF3.sub.4b port represents |E.sub.4b||F3.sub.4b|/G.sub.4b, wherein G.sub.4b is a reference current signal. Next, the unipolar product current signal |E.sub.4b||F3.sub.4b|/G.sub.4b is inputted to a current-mode polarity conditioner (iPC3.sub.4b). The iPC3.sub.4b can also utilize a circuit embodiment such as iPC.sub.1e that is disclosed in section 1E and illustrated in FIG. 1E. The iPC3.sub.4b also receives the E and F3 sign signals, eS.sub.4b and fS3.sub.4b and generates a multi-quadrant product current signal that represents E.sub.4bF3.sub.4b/G.sub.4b.
(131) The disclosed SqiMULT.sub.4b of FIG. 4B operates in current mode and as such it possesses the relevant benefits listed earlier in the DETAILED DESCRIPTION section. Also, as compared to a more complicated, bigger, and slower multi-quadrant current mode multiplier, the disclosed method utilizes a simpler, smaller, and faster single-quadrant multiplier (combined with front-end signal conditioning and back-end polarity conditioning) to preform multi-quadrant multiplication. Moreover, matching between the plurality of channel outputs is improved since identical arrangements for iPC1.sub.4b-iPC2.sub.4b-iPC3.sub.4b, and identical arrangements for iDACE.sub.4b-iDACF1.sub.4b-iDACF2.sub.4b-iDACF3.sub.4b can be utilized in SqiMULT.sub.4a.
Section 4CDescription of FIG. 4C
(132) FIG. 4C illustrates another multiple-channel multi-quadrant analog current-input to current-output scalar multiplier (SqiMULT.sub.4c).
(133) As stated earlier, SqiMULT.sub.4c of FIG. 4C utilizes plurality of qiMULT.sub.3c illustrated earlier in FIG. 3D and disclosed in section 3D. Also refer to section 3F and FIG. 3F which is a circuit simulation describing and illustrating the input-output waveforms of the qiMULT.sub.3d of FIG. 3D that is utilized here in FIG. 4C.
(134) In the disclosed SqiMULT.sub.4c of FIG. 4C, a bipolar E analog current-input signal (E.sub.4c) is inputted to an E analog signal conditioner (iSCE.sub.4c). Note that E.sub.4c is the scalar signal that can be multiplied with plurality of signals (e.g., F1.sub.4c, F2.sub.4c, F3.sub.4c, and so on), which will be discussed shortly. The iSCE.sub.4c can utilize a circuit embodiment such as iSC.sub.1a that is disclosed in section 1A and illustrated in FIG. 1A. The iSCE.sub.4C generates a unipolar analog current signal (|E.sub.4c|). The iSCE.sub.4, also generates an E digital sign signal (eS.sub.4c), which indicates the polarity of the E.sub.4c. An E single-quadrant iADCE.sub.4b receives a reference current signal G.sub.4c at its' current reference port RefE.sub.4c. The iADCE.sub.4C receives the E unipolar analog current signal |E.sub.4b| at its analog input port AiE.sub.4c, and generates an E digital signal |E.sub.4c| that is m1 bits wide at its digital output port (DoE.sub.4c). The iADCE.sub.4c's digital output signal |E.sub.4| can be inputted to a plurality channels (e.g., p=3) to be multiplied with plurality of signals (e.g., |F1.sub.4c|, |F2.sub.4c|, and |F3.sub.4c|), which will be described next.
(135) Note that number of channels can be a sea of channels (plurality>2) depending on the end-application requirements, but for clarity of description, 3-channels are illustrated and describe here.
(136) In the first channel, a F1 bipolar analog current-input signal (F1.sub.4c) is inputted to a F1 analog signal conditioner (iSCH.sub.4c). The iSCH.sub.4c can utilize a circuit embodiment such as iSC.sub.1a that is disclosed in section 1A and illustrated in FIG. 1A. The iSCH.sub.4c generate a unipolar analog current signal (|F1.sub.4c|). The iSCH.sub.4c also generates a sign signal (fS1.sub.4c), which indicates the polarity of F1.sub.4c. The iADCE.sub.4c's digital output signal |E.sub.4c| is inputted to the digital input port DiF1.sub.4c of a single-quadrant iDACF1.sub.4c. Concurrently, the unipolar analog current signal |F1.sub.4c| is inputted to the iDACF1.sub.4c's current reference port RefF1.sub.4c. Accordingly, the iDACF1.sub.4c generates (at its current output port AoF1.sub.4c) a unipolar analog current signal that represents |E.sub.4c||F1.sub.4c|/G.sub.4c, wherein G.sub.4c is a reference current signal. Next, the unipolar product current signal |Ez.sub.4c||F1.sub.4c|/G.sub.4c is inputted to a current-mode polarity conditioner (iPC1.sub.4c). The iPC1.sub.4c can utilize a circuit embodiment such as iPC.sub.1e that is disclosed in section 1E and illustrated in FIG. 1E. The iPC1.sub.4c also receives the E and F1 sign signals, eS.sub.4c and fS1.sub.4c, and it generates a multi-quadrant product current signal that represents E.sub.4cF1.sub.4c/G.sub.4c.
(137) In the second channel, a F2 bipolar analog current-input signal (F2.sub.4c) is inputted to a F2 analog signal conditioner (iSCF2.sub.4c). The iSCF2.sub.4c can also utilize a circuit embodiment such as iSC.sub.1a that is disclosed in section 1A and illustrated in FIG. 1A. The iSCF2.sub.4c generate a unipolar analog current signal (|F2.sub.4c|). The iSCF2.sub.4c also generates a sign signal (fS2.sub.4c), which indicates the polarity of F2.sub.4c. The iADCE.sub.4c's digital output signal |E.sub.4c| is also inputted to the digital input port DiF2.sub.4c of a single-quadrant iDACF2.sub.4C. Concurrently, the unipolar analog current signal |F2.sub.4c| is inputted to the iDACF2.sub.4c's current reference port RefF2.sub.4c. Accordingly, the iDACF2.sub.4c generates (at its current output port AoF2.sub.4c) a unipolar analog current signal that represents |E.sub.4c||F2.sub.4c|/G.sub.4c, wherein G.sub.4c is a reference current signal. Next, the unipolar product current signal |E.sub.4c||F2.sub.4c|/G.sub.4c is inputted to a current-mode polarity conditioner (iPC2.sub.4c). The iPC2.sub.4c can also utilize a circuit embodiment such as iPC.sub.1e that is disclosed in section 1E and illustrated in FIG. 1E. The iPC2.sub.4c also receives the E and F2 sign signals, eS.sub.4c and fS2.sub.4c, and it generates a multi-quadrant product current signal that represents E.sub.4cF2.sub.4c/G.sub.4c.
(138) In the third channel, a F3 bipolar analog current-input signal (F3.sub.4c) is inputted to a F3 analog signal conditioner (iSCF3.sub.4C). The iSCF3.sub.4C can also utilize a circuit embodiment such as iSC.sub.1a that is disclosed in section 1A and illustrated in FIG. 1A. The iSCF3.sub.4C generate a unipolar analog current signal (|F3.sub.4c|). The iSCF3.sub.4c also generates a sign signal (fS3.sub.4c), which indicates the polarity of F3.sub.4c. The iADCE.sub.4c's digital output signal |EL.sub.4c| is also inputted to the digital input port DiF3.sub.4c of a single-quadrant iDACF3.sub.4C. Concurrently, the unipolar analog current signal |F3.sub.4c| is inputted to the iDACF3.sub.4c's current reference port RefF3.sub.4c. Accordingly, the iDACF3.sub.4C generates (at its current output port AoF3.sub.4c) a unipolar analog current signal that represents |E.sub.4c||F3.sub.4c|/G.sub.4c, wherein G.sub.4c is a reference current signal. Next, the unipolar product current signal |E.sub.4C||F3.sub.4c|/G.sub.4c is inputted to a current-mode polarity conditioner (iPC3.sub.4c). The iPC3.sub.4c can also utilize a circuit embodiment such as iPC.sub.1e that is disclosed in section 1E and illustrated in FIG. 1E. The iPC3.sub.4c also receives the E and F3 sign signals, eS.sub.4c and fS3.sub.4c, and it generates a multi-quadrant product current signal that represents E.sub.4cF3.sub.4c/G.sub.4c.
(139) The disclosed SqiMULT.sub.4c of FIG. 4C operates in current mode and as such it possesses the relevant benefits listed earlier in the DETAILED DESCRIPTION section. Also, as compared to a more complicated, bigger, and slower multi-quadrant current mode multiplier, the disclosed method utilizes a simpler, smaller, and faster single-quadrant multiplier (combined with front-end signal conditioning and back-end polarity conditioning) to preform multi-quadrant multiplication. Furthermore, matching between the plurality of channel outputs is improved since identical arrangements for iPC1.sub.4-iPC2.sub.4-iPC3.sub.4c, and identical arrangements for DACF1.sub.4c-iDACF2.sub.4c-iDACF3.sub.4c, and identical arrangements for iSCE.sub.4c-iSCH.sub.4c-iSCF2.sub.4c-iSCF3.sub.4c can be utilized in SqiMULT.sub.4c.
Section 4DDescription of FIG. 4D
(140) FIG. 4D is a simplified block diagram illustrating a multi-quadrant digital input to analog current output multiply-accumulate (qiMAC.sub.4d) utilizing qiMULT.sub.3c disclosed in section 3C.
(141) Note that qiMAC.sub.4d utilizes plurality of qiMULT.sub.3c illustrated earlier in FIG. 3C and disclosed in section 3C. Also refer to section 3E and FIG. 3E which is a circuit simulation describing and illustrating the input-output waveforms of the qiMULT.sub.3c of FIG. 3C that is utilized here in FIG. 4D.
(142) In the disclosed qiMAC.sub.4d of FIG. 4D, an E1 digital input signal (E1.sub.4d), which is m bits wide, is inputted to an E1 digital signal conditioner (dSCE1.sub.4d), which operates in sign-magnitude method. As stated earlier, besides the sign-magnitude method, it would be obvious to one skilled in the art to utilize other digital binary formatting methods, including but not limited to, 2's complement, 1's complement, and offset-binary, amongst others. The dSCE1.sub.4d can utilize a circuit embodiment such as dSC.sub.1b that is disclosed in section 1B and illustrated in FIG. 1B. The dSCE1.sub.4d generates a magnitude E1 digital signal (|E1.sub.4d|), which is m1 bits wide. The dSCE1.sub.4d also generates an E1 digital sign signal (eS1.sub.4d), which indicates the polarity of the E1.sub.4d, which is the MSB of the E1.sub.4d digital signal.
(143) Similarly, a F1 digital input signal that is m-bits wide (F1.sub.4d) is inputted to a F1 digital signal conditioner (dSCF1.sub.4d). Also, the dSCF1.sub.4d can utilize a circuit embodiment such as dSC.sub.1b that is disclosed in section 1B and illustrated in FIG. 1B. The dSCF1.sub.4d generate a magnitude F1 digital signal (|F1.sub.4d|), which is m1 bits wide. The dSCF1.sub.4d also generates a F1 sign signal (fS1.sub.4d), which indicates the polarity of the F1.sub.4d, which is the MSB of the F1.sub.4d digital signal.
(144) Then, the |E|.sub.4d| and |F1.sub.4d| magnitude digital signals are inputted to a pair of single-quadrant iDACs configured in multiplying DAC mode, as follows: An E1 single-quadrant iDACE1.sub.4d receives a reference current signal G.sub.4d at its' current reference port RefE1.sub.4d. The iDACE1.sub.4d receives the E1 magnitude digital signals |E|.sub.4d| at its digital input port DiE1.sub.4d, and generates an E1 analog unipolar current signal |E| .sub.4d| at its current output port (AoE1.sub.4d). Concurrently, a F1 single-quadrant iDACF1.sub.4d receives, as its reference current signal, the |E1.sub.4d| from iDACE1.sub.4d at iDACF1.sub.4d's current reference port RefF1.sub.4d. The iDACF1.sub.4d receives the F1 magnitude digital signals |F1.sub.4d| at its digital input port DiF1.sub.4d, and generates a F1 analog unipolar current signal at its current output port (AoF1.sub.4d). This signal at the AoF1.sub.4d is an analog single-quadrant (unipolar) product current signal representing |E1.sub.4d||F1.sub.4d|/G.sub.4d, wherein G.sub.4d is a reference current signal.
(145) The single-quadrant product current signal |E1.sub.4d||F.sub.4d|/G.sub.4d is inputted to a current-mode polarity conditioning accumulator (iPCA.sub.4d), which will be discussed shortly.
(146) Additionally, in the disclosed qiMAC.sub.4d of FIG. 4D, an E2 digital input signal (E2.sub.4d), which is m bits wide, is inputted to an E2 digital signal conditioner (dSCE2.sub.4d), which operates in sign-magnitude method. The dSCE2.sub.4d can utilize a circuit embodiment such as dSC.sub.1b that is disclosed in section 1B and illustrated in FIG. 1B. The dSCE2.sub.4d generates a magnitude E2 digital signal (|E2.sub.4d|), which is m1 bits wide. The dSCE2.sub.4d also generates an E2 digital sign signal (eS2.sub.4d), which indicates the polarity of the E2.sub.4d, which is the MSB of the E2.sub.4d digital signal.
(147) Similarly, a F2 digital input signal that is m-bits wide (F2.sub.4d) is inputted to a F2 digital signal conditioner (dSCF2.sub.4d). Also, the dSCF2.sub.4d can utilize a circuit embodiment such as dSC.sub.1b that is disclosed in section 1B and illustrated in FIG. 1B. The dSCF2.sub.4d generate a magnitude F2 digital signal (|F2.sub.4d|), which is m1 bits wide. The dSCF2.sub.4d also generates a F2 sign signal (fS2.sub.4d), which indicates the polarity of the F2.sub.4d, which is the MSB of the F2.sub.4d digital signal.
(148) Likewise, the |E2.sub.4d| and |F2.sub.4d| magnitude digital signals are inputted to a pair of single-quadrant iDACs configured in multiplying DAC mode, as follows: An E2 single-quadrant iDACE2.sub.4d also receives a reference current signal G.sub.4d at its' current reference port RefE2.sub.4d. The iDACE2.sub.4d receives the E2 magnitude digital signals E2.sub.4d| at its digital input port DiE2.sub.4d, and generates an E2 analog unipolar current signal |E2.sub.4d| at its current output port (AoE2.sub.4d). Concurrently, a F2 single-quadrant iDACF2.sub.4d receives, as its reference current signal, the |E2.sub.4d| from iDACE2.sub.4d at iDACF2.sub.4d's current reference port RefF2.sub.4d. The iDACF2.sub.4d receives the F2 magnitude digital signals |F2.sub.4d| at its digital input port DiF2.sub.4d, and generates a F2 analog unipolar current signal at its current output port (AoF2.sub.4d). This signal at the AoF2.sub.4d is an analog single-quadrant (unipolar) product current signal representing |E2.sub.4d||F2.sub.4d|/G.sub.4d, wherein similarly G.sub.4d is a reference current signal.
(149) The single-quadrant product current signal |E2.sub.4d||F2.sub.4d|/G.sub.4d is inputted to the current-mode polarity conditioning accumulator (iPCA.sub.4d), which is described next: The iPCA.sub.4d performs the equivalent function of a pair of modified iPC.sub.1es disclosed in section 1E and illustrated in FIG. 1E, wherein M3.sub.1e and M4.sub.1e are eliminated from iPC.sub.1e. In the iPCA.sub.4d of FIG. 4d, sign signals eS1.sub.4d and fS1.sub.4d are inputted to XNOR1.sub.4d. The analog single-quadrant (unipolar) product current signal representing Io1.sub.4d=E1.sub.4d||F1.sub.4d|/G.sub.4d is inputted to the source terminals of M1.sub.4d and M1.sub.4d. Here, the Io1.sub.4d is steered either through M1.sub.4d to sink current from Io.sub.4d port (which is the current output port of the qiMAC.sub.4d) or flow through M1.sub.4d to the current mirror M3.sub.4d and M3.sub.4d to source current through the Io.sub.4d port. Similarly, in the iPCA.sub.4d of FIG. 4d, sign signals eS2.sub.4d and fS2.sub.4d are inputted to XNOR2.sub.4d. The analog single-quadrant (unipolar) product current signal representing Io2.sub.4d=|E2.sub.4d||F2.sub.4d|/G.sub.4d is inputted to the source terminals of M2.sub.4d and M2.sub.4d. Here, the Io2.sub.4d is steered either through M2.sub.4d to sink current from Io.sub.4d port, which is the current output port of the qiMAC.sub.4d, or flow through M2.sub.4d to the same current mirror M3.sub.4d and M3.sub.4d to source current through the Io.sub.4d port. Accordingly, the output of qiMAC.sub.4d generates a Io.sub.4d=(E1.sub.4dF1.sub.4dE2.sub.4dF2.sub.4d)/G.sub.4d
(150) Note that for clarity of description, the qiMAC.sub.4d is illustrated with 2 channels, but there can be (plurality) sea of channels, depending on end-application requirements.
(151) Moreover, by sharing the same current mirror M3.sub.4d M3.sub.4d amongst plurality of channels (besides smaller area and lower cost), the matching between each of the plurality of channel's current output is improved. Additionally, for enhanced multi-quadrant matching and faster dynamic performance, just one high-performance current mirror instead of plurality of current mirrors can be utilized (e.g., improved current mirror M3.sub.4d-M3.sub.4d such as cascading the mirror for higher output impedance and multi-quadrant matching, adding constant injection currents to input-output of the current mirror to improve its dynamic performance during zero-current crossing, etc.)
(152) The disclosed qiMAC.sub.4d of FIG. 4D operates in current mode and as such it possesses the relevant benefits listed earlier in the DETAILED DESCRIPTION section. Furthermore, as compared to a more complicated, bigger, and slower multi-quadrant current mode multiplier, the disclosed method utilizes a simpler, smaller, and faster single-quadrant multiplier (combined with front-end signal conditioning and back-end polarity conditioning) to preform multi-quadrant multiplication. Moreover, matching between the plurality of channel outputs is improved since identical arrangements for DACE1.sub.4d-iDACF1.sub.4d and DACE2.sub.4d-iDACF2.sub.4d can be utilized in qiMAC.sub.4d.
Section 5ADescription of FIG. 5A
(153) FIG. 5A illustrates another multiple-channel multi-quadrant analog current-input to current-output scalar multiplier (SqiMULT.sub.5a)
(154) First, the (unipolar) single-quadrant current-input to current-output multiplier section of SqiMULT.sub.5a is briefly described. By utilizing MOSFETs in subthreshold, a scalar current signal I.sub.ME.sub.5a and a reference current signal Ir.sub.5a=I.sub.ME.sub.5a establish a
(155)
By the operation of (Kirchhoff Voltage Law) KVL for the loop (comprising of Vgs.sub.ME.sub.5a, Vgs.sub.ME.sub.5a, Vgs.sub.MF1.sub.5a, and Vgs.sub.MF1.sub.5a) the difference voltage signal Vgs.sub.ME.sub.5aVgs.sub.ME.sub.5a is equalized with the difference voltage signal Vgs.sub.MF1.sub.5a-Vgs.sub.MF1.sub.5a. As such,
(156)
is substantially equalized with
(157)
Hence, I.sub.MF1.sub.5aI.sub.ME.sub.5aI.sub.MF1.sub.5a/I.sub.ME.sub.5a, which formulates the (unipolar) single-quadrant scalar multiplication of the first channel. Similar analysis can be applied to the second and third channels: Vgs.sub.ME.sub.5aVgS.sub.ME.sub.5aVgS.sub.MF2.sub.5aVgS.sub.MF2.sub.5a, and Vgs.sub.ME.sub.5aVgs.sub.ME.sub.5aVgs.sub.MF3.sub.5aVgs.sub.MF3.sub.5a. Therefore, I.sub.MF2.sub.5aI.sub.ME.sub.5aI.sub.MF2.sub.5a/I.sub.ME.sub.5a, and I.sub.MF3.sub.5aI.sub.ME.sub.5aI.sub.MF3.sub.5a/I.sub.ME.sub.5a.
(158) In FIG. 5A, an E bipolar current input signal (E.sub.5a) is inputted to a E current signal conditioner (iSCE.sub.5a). The iSCE.sub.5a can utilize a circuit embodiment such as iSC.sub.1a that is disclosed in section 1A and illustrated in FIG. 1A. The iSCE.sub.5a generate a E unipolar current signal (|E.sub.5a|=I.sub.ME.sub.5a). The iSCE.sub.5a also generates a E sign signal (eS.sub.5a), which indicates the polarity of the E.sub.5a.
(159) Substituting for I.sub.ME.sub.5a=G.sub.5a, and I.sub.ME.sub.5a=|E.sub.5a|, hence I.sub.MF1.sub.5a|E.sub.5a|I.sub.MF1.sub.5a/G.sub.5a, I.sub.MF2.sub.5a|E.sub.5a|I.sub.MF2.sub.5a/G.sub.5a, and I.sub.MF3.sub.5a|E.sub.5a|I.sub.MF3.sub.5a/G.sub.5a.
(160) Note also that number of channels can be a sea of channels (plurality>2) depending on the end-application, but for clarity of description, 3-channels are illustrated and describe here.
(161) In FIG. 5A's first channel, a F1 bipolar current input signal (F1.sub.5a) is inputted to a F1 current signal conditioner (iSCH.sub.5a). Moreover, the iSCH.sub.5a can utilize a circuit embodiment such as iSC.sub.1a that is disclosed in section 1A and illustrated in FIG. 1A. The iSCH.sub.5a generate a F1 unipolar current signal (|F1.sub.5a|=I.sub.MF1.sub.5a) The iSCH.sub.5a also generates a F1 sign signal (fS1.sub.5a), which indicates the polarity of the F1.sub.4a. Substituting for |F1.sub.5a|=I.sub.MF1.sub.5a in the multiplier equation derived above: I.sub.MF1.sub.5a|E.sub.5a|I.sub.MF1.sub.5a/G.sub.5a|E.sub.5a||F1.sub.5a|/G.sub.5a. Next, the single-quadrant product current signal |E.sub.5a||F1.sub.5a|/G.sub.5a is inputted to a current-mode polarity conditioner (iPC1.sub.5a). The iPC1.sub.5a can likewise utilize a circuit embodiment such as iPC.sub.1e that is disclosed in section 1E and illustrated in FIG. 1E. The iPC1.sub.5a is also inputted with the E and F1 sign signals, eS.sub.5a and fS1.sub.5a, and it generates a multi-quadrant product current signal that represents E.sub.5aF1.sub.5a/G.sub.5a.
(162) In FIG. 5A's second channel, a F2 bipolar current input signal (F2.sub.5a) is inputted to a F2 current signal conditioner (iSCF2.sub.5a). Additionally, the iSCF2.sub.5a can utilize a circuit embodiment such as iSC.sub.1a that is disclosed in section 1A and illustrated in FIG. 1A. The iSCF2.sub.5a generate a F2 unipolar current signal (|F2.sub.5a|=I.sub.MF2.sub.5a) The iSCF2.sub.5a also generate a F2 sign signal (fS2.sub.5a), which indicates the polarity of the F2.sub.4a. Substituting for |F2.sub.5a|=I.sub.MF2.sub.5a in the multiplier equation derived above: I.sub.MF2.sub.5a|E.sub.5a|I.sub.MF2.sub.5a/G.sub.5a|E.sub.5a||F2.sub.5a|/G.sub.5a. Next, the single-quadrant product current signal |E.sub.5a||F2.sub.5a|/G.sub.5a is inputted to a current-mode polarity conditioner (iPC2.sub.5a). The iPC2.sub.5a can also utilize a circuit embodiment such as iPC.sub.1e that is disclosed in section 1E and illustrated in FIG. 1E. The iPC2.sub.5a is also inputted with the E and F2 sign signals, eS.sub.5a and fS2.sub.5a, and it generates a multi-quadrant product current signal that represents E.sub.5aF2.sub.5a/G.sub.5a.
(163) In FIG. 5A's third channel, a F3 bipolar current input signal (F3.sub.5a) is inputted to a F3 current signal conditioner (iSCF3.sub.5a). Additionally, the iSCF3.sub.5a can utilize a circuit embodiment such as iSC.sub.1a that is disclosed in section 1A and illustrated in FIG. 1A. The iSCF3.sub.5a generate a F3 unipolar current signal (|F3.sub.5a|=I.sub.MF3.sub.5a). The iSCF3.sub.5a also generates a F3 sign signal (fS3.sub.5a), which indicates the polarity of the F3.sub.4a. Substituting for |F3.sub.5a|=I.sub.MF3.sub.5a in the multiplier equation derived above: I.sub.MF3.sub.5a|E.sub.5a|I.sub.MF3.sub.5a/G.sub.5a|E.sub.5a||F3.sub.5al/G.sub.5a. Next, the single-quadrant product current signal |E.sub.5a||F3.sub.5a|/G.sub.5a is inputted to a current-mode polarity conditioner (iPC3.sub.5a). The iPC3.sub.5a can also utilize a circuit embodiment such as iPC.sub.1e that is disclosed in section 1E and illustrated in FIG. 1E. The iPC3.sub.5a is likewise inputted with the E and F3 sign signals, eS.sub.5a and fS3.sub.5a, and it generates a multi-quadrant product current signal that represents E.sub.5aF3.sub.5a/G.sub.5a.
(164) The disclosed SqiMULT.sub.5a of FIG. 5A operates in current mode and as such it possesses the relevant benefits listed earlier in the DETAILED DESCRIPTION section. Additionally, as compared to a more complicated, bigger, and slower multi-quadrant current mode multiplier, the disclosed method utilizes a simpler, smaller, and faster single-quadrant multiplier (combined with front-end signal conditioning and back-end polarity conditioning) to preform multi-quadrant multiplication. Furthermore, matching between the plurality of channel outputs is improved since identical arrangements for iSCE.sub.5aiSCF1.sub.5aiSCF2.sub.5aiSCF3.sub.5a and identical arrangements for iPC1.sub.5aiPC2.sub.5aiPC3.sub.5a can be utilized in SqiMULT.sub.4d. Area savings and matching improvements are also attained in light of the multiplier FETs ME.sub.5a and ME.sub.5a being shared amongst plurality of channels.
Section 5BDescription of FIG. 5B
(165) FIG. 5B illustrates another multiple-channel multi-quadrant digital-input to current-output scalar multiplier (SqiMULT.sub.5b)
(166) First, the (unipolar) single-quadrant current-input to current-output multiplier section of SqiMULT.sub.5b is briefly described. Utilizing MOSFETs in subthreshold, a scalar current signal I.sub.ME.sub.5b and a reference current signal Ir.sub.5b=I.sub.ME.sub.5b establish a
(167)
By the operation of (Kirchhoff Voltage Law) KVL for the loop (comprising of Vgs.sub.ME.sub.5b, VgS.sub.ME.sub.5b, VgS.sub.MF1.sub.5b, and Vgs.sub.MF1.sub.5b) the difference voltage signal Vgs.sub.ME.sub.5bVgs.sub.ME.sub.5b is equalized with the difference voltage signal Vgs.sub.MF1.sub.5bVgs.sub.MF1.sub.5b. As such,
(168)
is substantially equalized with
(169) 0
Hence, I.sub.MF1.sub.5bI.sub.ME.sub.5bI.sub.MF1.sub.5b/I.sub.ME.sub.5b, which formulates the (unipolar) single-quadrant scalar multiplication of the first channel. Similar analysis can be applied to the second and third channels: Vgs.sub.ME.sub.5bVgs.sub.ME.sub.5bVgs.sub.MF2.sub.5bVgs.sub.MF2.sub.5b, and Vgs.sub.ME.sub.5bVgs.sub.ME.sub.5bVgs.sub.MF3.sub.5bVgs.sub.MF3.sub.5b. Therefore, I.sub.MF2.sub.5bI.sub.ME.sub.5bI.sub.MF2.sub.5b/I.sub.ME.sub.5b, and I.sub.MF3.sub.5bI.sub.ME.sub.5bI.sub.MF3.sub.5b/I.sub.ME.sub.5b.
(170) In the disclosed SqiMULT.sub.5b of FIG. 5B, an E digital-input signal (E.sub.5b), which is m bits wide, is inputted to an E digital signal conditioner (dSCE.sub.5b), which operates in sign-magnitude method. As stated earlier, besides the sign-magnitude method, it would be obvious to one skilled in the art to utilize other digital binary formatting methods, including but not limited to, 2's complement, 1 's complement, and offset-binary, amongst others. The dSCE.sub.5b can utilize a circuit embodiment such as dSC.sub.1b that is disclosed in section 1B and illustrated in FIG. 1B. The dSCE.sub.5b generates a magnitude E digital signal (|E.sub.5b|), which is m1 bits wide. The dSCE.sub.5b also generates an E digital sign signal (eS.sub.5b), which indicates the polarity of the E.sub.5b, which is the MSB of the E.sub.5b digital signal. An E single-quadrant iDACE.sub.5b receives a reference current signal G.sub.5b at its' current reference port RefE.sub.5b. The iDACE.sub.5b receives the E magnitude digital signals |E.sub.5b| at its digital input port DiE.sub.5b, and generates an E analog unipolar current signal |E.sub.5b| at its current output port (AoE.sub.5b).
(171) Substituting for I.sub.ME.sub.5b=G.sub.5b, and I.sub.ME.sub.5b=|E.sub.5b|, hence I.sub.MF1.sub.5b|E.sub.5b|I.sub.MF1.sub.5b/G.sub.5b, I.sub.MF2.sub.5b|E.sub.5b|I.sub.MF2.sub.5b/G.sub.5b, and I.sub.MF3.sub.5b|E.sub.5b|I.sub.MF3.sub.5b/G.sub.5b.
(172) Note that number of channels can be a sea of channels (plurality>3) depending on the end-application, but for clarity's sake 3-channels are illustrated and describe here.
(173) In FIG. 5B, for the disclosed SqiMULT.sub.5b first channel, a F1 digital-input signal (F1.sub.5b) that is m bits wide is inputted to an F1 digital signal conditioner (dSCF1.sub.5b), which operates in sign-magnitude method. As stated earlier, besides the sign-magnitude method, it would be obvious to one skilled in the art to utilize other digital binary formatting methods, including but not limited to, 2's complement, 1's complement, and offset-binary, amongst others. The dSCF1.sub.5b can also utilize a circuit embodiment such as dSC.sub.1b that is disclosed in section 1B and illustrated in FIG. 1B. The dSCF1.sub.5b generates a magnitude F1 digital signal (|F1.sub.5b|), which is m1 bits wide. The dSCF1.sub.5b also generates an F1 digital sign signal (fS1.sub.5b), which indicates the polarity of the F1.sub.5b, which is the MSB of the F1.sub.5b digital signal. An F1 single-quadrant iDACF1.sub.5b receives a reference current signal G.sub.5b at its' current reference port RefF1.sub.5b. The iDACF1.sub.5b receives the F1 magnitude digital signals |F1.sub.5b| at its digital input port DiF1.sub.5b, and generates an F1 analog unipolar current signal |F1.sub.5b| at its current output port (AoF1.sub.5b). Substituting for |F1.sub.5b|=I.sub.MF1.sub.5b in the multiplier equation derived above: I.sub.MF1.sub.5b|E.sub.5b|I.sub.MF1.sub.5b/G.sub.5b|E.sub.5b||F1.sub.5b|/G.sub.5b. Next, the single-quadrant product current signal |E.sub.5b||F1.sub.5b|/G.sub.5b is inputted to a current-mode polarity conditioner (iPC1.sub.5b). The iPC1.sub.5b can likewise utilize a circuit embodiment such as iPC.sub.1e that is disclosed in section 1E and illustrated in FIG. 1E. The iPC1.sub.5b is also inputted with the E and F1 sign signals, eS.sub.5b and fS1.sub.5b, and it generates a multi-quadrant product current signal that represents E.sub.5bF1.sub.5b/G.sub.5b.
(174) In FIG. 5B, the disclosed SqiMULT.sub.5b's second channel, a F2 digital-input signal (F2.sub.5b) that is m bits wide is inputted to an F2 digital signal conditioner (dSCF2.sub.5b), which operates in sign-magnitude method. The dSCF2.sub.5b can also utilize a circuit embodiment such as dSC.sub.1b that is disclosed in section 1B and illustrated in FIG. 1B. The dSCF2.sub.5b generates a magnitude F2 digital signal (|F2.sub.5b|), which is m1 bits wide. The dSCF2.sub.5b also generates an F2 digital sign signal (fS2.sub.5b), which indicates the polarity of the F2.sub.5b, which is the MSB of the F2.sub.5b digital signal. An F2 single-quadrant iDACF2.sub.5b receives a reference current signal G.sub.5b at its' current reference port RefF2.sub.5b. The iDACF2.sub.5b receives the F2 magnitude digital signals |F2.sub.5b| at its digital input port DiF2.sub.5b, and it generates an F2 analog unipolar current signal |F2.sub.5b| at its current output port (AoF2.sub.5b). Substituting for |F2.sub.5b|=I.sub.MF2.sub.5b in the multiplier equation derived above: I.sub.MF2.sub.5bE.sub.5b|I.sub.MF2.sub.5b/G.sub.5b|E.sub.5b||F2.sub.5b|/G.sub.5b. Next, the single-quadrant product current signal |E.sub.5b||F2.sub.5b|/G.sub.5b is inputted to a current-mode polarity conditioner (iPC2.sub.5b). The iPC2.sub.5b can likewise utilize a circuit embodiment such as iPC.sub.1e that is disclosed in section 1E and illustrated in FIG. 1E. The iPC2.sub.5b is also inputted with the E and F2 sign signals, eS.sub.5b and fS2.sub.5b, and it generates a multi-quadrant product current signal that represents E.sub.5bF2.sub.5b/G.sub.5b.
(175) In the disclosed SqiMULT.sub.5b's third channel, a F3 digital-input signal (F3.sub.5b) that is m bits wide is inputted to an F3 digital signal conditioner (dSCF3.sub.5b), which operates in sign-magnitude method. The dSCF3.sub.5b can also utilize a circuit embodiment such as dSC.sub.1b that is disclosed in section 1B and illustrated in FIG. 1B. The dSCF3.sub.5b generates a magnitude F3 digital signal (|F3.sub.5b|), which is m1 bits wide. The dSCF3.sub.5b also generates an F3 digital sign signal (fS3.sub.5b), which indicates the polarity of the F3.sub.5b, which is the MSB of the F3.sub.5b digital signal. A F3 single-quadrant iDACF3.sub.5b receives a reference current signal G.sub.5b at its' current reference port RefF3.sub.5b. The iDACF3.sub.5b receives the F3 magnitude digital signals |F3.sub.5b| at its digital input port DiF3.sub.5b, and generates an F3 analog unipolar current signal |F3.sub.5b| at its current output port (AoF3.sub.5b). Substituting for |F3.sub.5b|=I.sub.MF3.sub.5b in the multiplier equation derived above: I.sub.MF2.sub.5b|E.sub.5b|I.sub.MF3.sub.5b/G.sub.5b|E.sub.5b||F3.sub.5b|/G.sub.5b. Next, the single-quadrant product current signal |E.sub.5b||F3.sub.5b|/G.sub.5b is inputted to a current-mode polarity conditioner (iPC3.sub.5b). The iPC3.sub.5b can likewise utilize a circuit embodiment such as iPC.sub.1e that is disclosed in section 1E and illustrated in FIG. 1E. The iPC3.sub.5b is also inputted with the E and F3 sign signals, eS.sub.5b and fS3.sub.5b, and it generates a multi-quadrant product current signal that represents E.sub.5bF3.sub.5b/G.sub.5b.
(176) The disclosed SqiMULT.sub.5b of FIG. 5B operates in current mode and as such it possesses the relevant benefits listed earlier in the DETAILED DESCRIPTION section. Furthermore, as compared to a more complicated, bigger, and slower multi-quadrant current mode multiplier, the disclosed method utilizes a simpler, smaller, and faster single-quadrant multiplier (combined with front-end signal conditioning and back-end polarity conditioning) to preform multi-quadrant multiplication. Additionally, matching between the plurality of channel outputs is improved since identical arrangements for iSCE.sub.5biSCH.sub.5biSCF2.sub.5biSCF3.sub.5b, and identical arrangements for iDACE.sub.5biDACF1.sub.5biDACF2.sub.5biDACF3.sub.5b, and identical arrangements for iPC1.sub.5biPC2.sub.5biPC3.sub.5b can be utilized in SqiMULT.sub.5b. Area savings and matching improvements are also attained in light of the multiplier FETs ME.sub.5b and ME.sub.5b being shared amongst plurality of channels.
