Clock generator

Abstract

A clock generator including a phase frequency detector configured to compare a phase and a frequency of a reference clock signal with a phase and a frequency of a first output clock signal and generate a detection signal based on a difference in the phases and frequencies of the clock signals; a loop filter configured to generate a first control voltage signal based on the detection signal; a first voltage controlled oscillator configured to generate and output a first output clock signal based on the first control voltage signal, a modulation filter configured to generate a modulation voltage signal based on the reference clock signal and generate a second control voltage signal by combining the modulation voltage signal and the first control voltage signal, and a second voltage controlled oscillator configured to generate and output a second output clock signal based on the second control voltage signal is provided.

Claims

1. A clock generator, comprising: a phase frequency detector configured to compare a phase and a frequency of a reference clock signal with a phase and a frequency of a first output clock signal and generate a detection signal based on a difference in the phases and frequencies of the clock signals; a loop filter configured to generate a first control voltage signal based on the detection signal; a first voltage controlled oscillator configured to generate and output a first output clock signal based on the first control voltage signal; a modulation filter configured to generate a modulation voltage signal based on the reference clock signal and generate a second control voltage signal by combining the modulation voltage signal and the first control voltage signal; and a second voltage controlled oscillator configured to generate and output a second output clock signal based on the second control voltage signal, wherein the modulation filter is a high-pass filter (HPF) consisting of a resistor and a capacitor, and wherein the modulation filter removes a direct current (DC) component and a lower-frequency harmonic component from the reference clock signal, and wherein the first control voltage signal is input to the resistor and the modulation voltage signal is input to the capacitor.

2. The clock generator of claim 1, wherein the first output clock signal is a non-spread spectrum clock signal, and the second output clock signal is a spread spectrum clock signal.

3. The clock generator of claim 1, further comprising a first charge pump configured to generate a first charge pumping current corresponding to the detection signal.

4. The clock generator of claim 1, wherein the loop filter generates a first control voltage signal corresponding to a first charge pumping current.

5. The clock generator of claim 1, further comprising a second charge pump configured to generate a second charge pumping current based on the reference clock signal.

6. The clock generator of claim 5, further comprising a clock divider configured to divide the reference clock signal by a predetermined division ratio and output the divided clock signal to the second charge pump.

7. The clock generator of claim 1, wherein the modulation filter generates the modulation voltage signal by integrating a second charge pumping current.

8. The clock generator of claim 1, wherein the modulation filter comprises high-pass filter features.

9. The clock generator of claim 1, wherein the modulation filter comprises a buffer configured to transmit the first control voltage signal to the modulation filter to combine the modulation voltage signal and the first control voltage signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a block diagram illustrating a conventional spread spectrum clock generator.

(2) FIG. 2 is a schematic block diagram illustrating a clock generator according to an embodiment of the present disclosure.

(3) FIG. 3 is a detailed block diagram illustrating the clock generator according to an embodiment of the present disclosure.

(4) FIG. 4 is a drawing illustrating a linear model of the clock generator according to an embodiment of the present disclosure.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

(5) Exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The same or similar elements are denoted by the same reference numerals regardless of the reference numerals, and redundant description thereof will be omitted.

(6) In addition, in the following description, well-known functions or constructions are not described in detail since they would obscure the disclosure in unnecessary detail. It is to be noted that the accompanying drawings are only for the purpose of facilitating understanding of the present disclosure and should not be construed as limiting the scope of the present disclosure with reference to the accompanying drawings.

(7) FIG. 2 is a schematic block diagram illustrating a clock generator according to an embodiment of the present disclosure, and FIG. 3 is a detailed block diagram illustrating the clock generator according to an embodiment of the present disclosure.

(8) As illustrated in FIG. 2, a clock generator according to an embodiment of the present disclosure includes a first clock generator 100 for generating and outputting a first output clock signal CLK.sub.out1 and a second clock generator 200 for generating and outputting a second output clock signal CLK.sub.out2.

(9) The first output clock signal CLK.sub.out1 is a non-spread spectrum clock signal without spread spectrum modulation, and the second output clock signal (CLK.sub.out2) is a spread spectrum clock signal subjected to spread spectrum modulation.

(10) The second clock generator 200 receives a first voltage control signal V.sub.c1 generated by the first clock generator 100 and generates a second output clock signal CLK.sub.out2 based on the first voltage control signal V.sub.c1. The first voltage control signal (V.sub.c1) is generated by the second clock generator 200, based on the first output clock signal CLK.sub.out1 fed back thereto.

(11) The first clock generator 100 has a closed loop structure and the second clock generator 200 has an open loop structure. Specifically, the first clock generator 100 has a closed loop structure because the first clock generator 100 outputs a clock signal having a fixed phase by receiving the first output clock signal CLK.sub.out1 fed back thereto. The second clock generator 200 has an open loop structure because the second clock generator 200 outputs a clock signal subjected to spread spectrum modulation by receiving the first control voltage signal V.sub.c1 generated by the first clock generator 100 as an input.

(12) As illustrated in FIG. 3, the clock generator according to an embodiment of the present disclosure may include a phase frequency detector (PFD) 110, a first charge pump (CP.sub.1) 120, a loop filter 130, a voltage controlled oscillator (VCO.sub.1) 140, a second charge pump (CP.sub.2) 220, a modulation filter 230, and a second voltage controlled oscillator (VCO.sub.2) 240.

(13) The phase frequency detector 110, the first charge pump 120, the loop filter 130, and the voltage controlled oscillator 140 may be included in the above-mentioned first clock generator 100, and the second charge pump 220, the modulation filter 230 and the second voltage controlled oscillator 240 may be included in the above-mentioned second clock generator 200.

(14) The phase frequency detector 110 receives the first output clock signal CLK.sub.out1 output from the first voltage controlled oscillator (VCO.sub.1) as an input, i.e. a feedback signal, and receives a reference clock signal CLK.sub.ref from an external source. The phase frequency detector 110 compares the phase and frequency of the reference clock signal CLK.sub.ref with those of the first output clock signal CLK.sub.out1 to generate a detection signal D corresponding to the difference.

(15) In particular, the phase frequency detector 110 generates an up-detection signal D.sub.up or a down-detection signal D.sub.dn corresponding to the phase-frequency difference between the reference clock signal CLK.sub.ref and the first output clock signal CLK.sub.out1. The up-detection signal D.sub.up and the down-detection signal D.sub.dn are pulse signals activated in accordance with the phase frequency relationship between the reference clock signal CLK.sub.ref and the first output clock signal CLK.sub.out1.

(16) The first charge pump 120 generates a first charge pumping current I.sub.cp1 corresponding to the detection signal D generated in the phase frequency detector 110. The first charge pump 120 may have a self-bias structure.

(17) In particular, the first charge pump 120 generates a first charge pumping current I.sub.cp1 having positive polarity (+) by performing a positive charge pumping operation in response to the up-detection signal D.sub.up while generating a first charge pumping current I.sub.cp1 having negative polarity () by performing a negative charge pumping operation in response to the down-detection signal D.sub.dn.

(18) The first charge pump 120 supplies charges to the loop filter 130 in response to the up-detection signal D.sub.up and subtracts the charges from the loop filter 130 in response to the down-detection signal D.sub.dn.

(19) The loop filter 130 generates the first control voltage signal V.sub.c1 based on the detection signal D generated by the phase frequency detector 110. The loop filter 130 generates the first control voltage signal V.sub.c1 corresponding to the first charge pumping current I.sub.cp1 generated by the first charge pump 120.

(20) In particular, the loop filter 130 may include a first capacitor (C.sub.1), a second capacitor (C.sub.2), and a first resistor (R.sub.1). Here, the first capacitor (C.sub.1) and the first resistor (R.sub.1) are connected in series and may be connected between a first node (N.sub.1) and a ground terminal. The second capacitor (C.sub.2) may be connected between the first node (N.sub.1) and the ground terminal.

(21) The loop filter 130 charges the second capacitor (C.sub.2) with charges supplied by the positive charge pumping operation of the first charge pump 120 and generates the first control voltage signal V.sub.c1 corresponding to the charges. The loop filter 130 discharges the second capacitor (C.sub.2) by the amount of charges discharged by the negative charge pumping operation generates the first control voltage signal V.sub.c1 corresponding to the charges.

(22) In other words, the voltage level of the first control voltage signal V.sub.c1 is increased by a charging operation of the first charge pump 120 and the voltage level is decreased by a discharging operation of the first charge pump 120.

(23) The detection signal (D) generated by the phase frequency detector 110 may include a direct current (DC) component and a harmonic component. Since the components necessary for fixing the phase of the clock signal are a DC component and a lower-frequency harmonic component, higher-frequency harmonic components of the detection signal D need to be removed.

(24) As described above, the loop filter 130 has a low pass filter (LPF) feature to remove a harmonic component from the detection signal (D). Here, the first capacitor (C.sub.1) and the first resistor (R.sub.1) connected in series may perform a low pass filter function.

(25) The first voltage controlled oscillator 140 generates the first output clock signal CLK.sub.out1 based on the first control voltage signal V.sub.c1 generated by the loop filter 130, and outputs the generated first output clock signal CLK.sub.out1. Then the first voltage controlled oscillator 140 outputs the generated first output clock signal CLK.sub.out1 to the phase frequency detector 110 to fix the phase of a next output clock signal.

(26) Here, the first voltage controlled oscillator 140 generates a first output clock signal CLK.sub.out1 having a frequency corresponding to the voltage level of the first control voltage signal V.sub.c1.

(27) The first clock generator 100 may further include a first clock divider D.sub.1 150. The first clock divider 150 divides the first output clock signal CLK.sub.out1 generated by the first voltage controlled oscillator 140 at a predetermined division ratio and outputs the result to the phase frequency detector 110.

(28) Here, the frequency division ratio of the first clock divider 150 is an important factor for determining the frequency of the first output clock signal CLK.sub.out1.

(29) For example, when the frequency of the reference clock signal CLK.sub.ref is 25 MHz and the division ratio is 60, the frequency of the first output clock signal CLK.sub.out1 is 1.5 GHz.

(30) Since detailed circuit configurations of the phase frequency detector 110, the first charge pump 120, the first voltage controlled oscillator 140, and the first clock divider 150 are well known in the art, detailed descriptions thereof will be omitted.

(31) The first control voltage signal V.sub.c1 is transmitted to the second clock generator 200, which will be described later.

(32) In this regard, the clock generator according to an embodiment of the present disclosure may further include a buffer 160 for transmitting a first control voltage signal V.sub.c1 generated by the loop filter 130 to the modulation filter 230.

(33) The first voltage controlled oscillator 140, for example, generates a first output clock signal CLK.sub.out1 having a low frequency corresponding to a first control voltage signal V.sub.c1 having a high voltage level and generates a first output clock signal CLK.sub.out1 having a high frequency corresponding to a first control voltage signal V.sub.c1 having a low voltage level.

(34) A frequency relationship between a voltage level of a first control voltage signal V.sub.c1 and a first output clock signal CLK.sub.out1 may vary depending on the design. It is possible to generate a first output clock signal CLK.sub.out1 having a low frequency corresponding to a first control voltage signal V.sub.c1 having a low voltage level and to generate a first output clock signal CLK.sub.out1 having a high frequency corresponding to a first control voltage signal V.sub.c1 having a high voltage level.

(35) The first clock divider 150 divides the first output clock signal CLK.sub.out1 at a predetermined division ratio and outputs the result to the phase frequency detector 110, and the phase frequency detector 110 re-detects the phase frequency difference between the reference clock signal CLK.sub.ref and the frequency-changed first output clock signal CLK.sub.out1.

(36) The first clock generator 100 generates and outputs a first output clock signal CLK.sub.out1 synchronized with the reference clock signal CLK.sub.ref while repeatedly performing the above-described operation.

(37) The second charge pump 220 generates a second charge pumping current I.sub.cp2 based on the reference clock signal CLK.sub.ref. The second charge pump 220 may have a non-self-bias structure, unlike the first charge pump 120.

(38) The modulation filter 230 may include a third capacitor (C.sub.3), a fourth capacitor (C.sub.4), and a second resistor (R.sub.2). Here, the third capacitor (C.sub.3) may be connected between a second node (N.sub.2) and the ground terminal, the second resistor (R.sub.2) may be connected between a third node N.sub.3 and the buffer 160, and the fourth capacitor (C.sub.4) may be connected between the second node N.sub.2 and the third node N.sub.3.

(39) The modulation filter 230 generates a modulation voltage signal V.sub.m based on the reference clock signal CLK.sub.ref. The third capacitor (C.sub.3) of the modulation filter 230 generates the modulation voltage signal V.sub.m by integrating a second charge pumping current I.sub.cp2 generated by the second charge pump 220.

(40) The modulation filter 230 generates a second control voltage signal V.sub.c2 by combining the generated modulation voltage signal V.sub.m with the first control voltage signal V.sub.c1 received from the buffer 160.

(41) The second clock generator 200 may further include a second clock divider (D.sub.2) 250.

(42) The second clock divider 250 divides a reference clock signal CLK.sub.ref received from an external source at a predetermined division ratio and outputs the divided clock signal CLK.sub.ref to the second charge pump 220. Then, the second charge pump 220 generates a second charge pumping current I.sub.cp2 corresponding to the divided reference clock signal CLK.sub.ref.

(43) The reference clock signal CLK.sub.ref divided by the second clock divider 250 may include a DC component and a harmonic component. Since the components necessary for the spread spectrum of the clock signal are higher-frequency harmonic components, the DC component and the lower-frequency harmonic component, among the divided reference clock signal CLK.sub.ref, need to be removed.

(44) As described above, the modulation filter 230 has a high-pass filter (HPF) feature to remove a DC component and a lower-frequency harmonic component from the divided reference clock signal CLK.sub.ref. Here, the fourth capacitor (C.sub.4) and the second resistor (R.sub.2) may perform a high-pass filter function.

(45) The second voltage controlled oscillator 240 generates and outputs a second output clock signal CLK.sub.out2 based on the second control voltage signal V.sub.c2 generated by the modulation filter 230. Specifically, the second voltage controlled oscillator 240 generates the second output clock signal CLK.sub.out2 having a frequency corresponding to the voltage level of the second control voltage signal V.sub.c2.

(46) Since the detailed circuit configurations of the second charge pump 220, the second voltage controlled oscillator 240, and the second clock divider 250 are well known in the art, detailed descriptions thereof will be omitted.

(47) Hereinafter, the operation of the second clock generator 200 will be described.

(48) The second clock divider 250 divides a reference clock signal CLK.sub.ref and outputs the divided reference clock signal CLK.sub.ref to the second charge pump 220.

(49) The second charge pump 220 generates a second charge pumping current I.sub.cp2 based on the divided reference clock signal CLK.sub.ref.

(50) Here, the divided reference clock signal CLK.sub.ref may have a square waveform in which the high level and the low level are repeated. In this case, the second charge pumping current I.sub.cp2 generated by the second charge pump 220 also has a square waveform.

(51) The modulation filter 230 generates a modulation voltage signal V.sub.mp in the form of a triangular wave by integrating the square wave formed current supplied from the second charge pump 220. Here, the modulation voltage signal V.sub.mp is filtered by the modulation filter 230 to generate V.sub.m, so that only high-frequency harmonic components remain.

(52) In addition, the modulation filter 230 receives a first control voltage signal V.sub.c1 through the buffer 160, and generates a second control voltage signal V.sub.c2 by combining the received first control voltage signal V.sub.c1 with the modulation voltage signal V.sub.m.

(53) The second voltage controlled oscillator 240 generates and outputs a second output clock signal CLK.sub.out2 corresponding to the voltage level of the second control voltage signal V.sub.c2. Here, the second output clock signal CLK.sub.out2 is converted into a clock signal subjected to spread spectrum modulation.

(54) As described above, the clock generator according to an embodiment of the present disclosure can reduce an electromagnetic interference (EMI) by reducing the power density of a clock signal using the spread spectrum of the clock signal frequency.

(55) In addition, when the clock generator according to an embodiment of the present disclosure is mounted on a wearable device, such as a healthcare product, used in close contact with a human body, the influence of electromagnetic waves on the human body can be minimized.

(56) In addition, the clock generator according to an embodiment of the present disclosure is advantageous in that a single clock generator can generate and output different types of clock signals, such as a non-spread spectrum clock signal and a spread spectrum clock signal, so that the clock signals can be used selectively or simultaneously as required.

(57) FIG. 4 is a drawing illustrating a linear model of the clock generator according to an embodiment of the present disclosure.

(58) Hereinafter, the circuit features of the clock generator according to the embodiment of the present disclosure will be described with reference to FIG. 4.

(59) Formula 1 below represents a transfer function of the frequency shift value (s) of a second output clock signal CLK.sub.out2 with respect to a modulation voltage signal V.sub.m(s).

(60) $\begin{array}{cc}\frac{\left(s\right)}{V_m\left(s\right)}=2K_{}& \mathrm{Formula}1\end{array}$

(61) Referring to Formula 1 above, the frequency shift value (s) of the second output clock signal CLK.sub.out2 with respect to the modulation voltage signal V.sub.m(s) has no bandwidth limitation, due to all-pass filter features thereof, where K.sub.v is the VCO gain.

(62) Formula 2 below represents a transfer function of a modulation voltage signal V.sub.m(s) for a second charge pumping current I.sub.cp2(s), which corresponds to the modulation currents I.sub.m(s).

(63) $\begin{array}{cc}\frac{V_m\left(s\right)}{I_m\left(s\right)}=\frac{\frac{1}{C_3}}{s+\frac{1}{R_2}\left(\frac{1}{C_3}+\frac{1}{C_4}\right)},{}_c=\frac{1}{R_2}\left(\frac{1}{C_3}+\frac{1}{C_4}\right)& \mathrm{Formula}2\end{array}$

(64) Referring to formula 2 above, the modulation voltage signal V.sub.m(s) for the second charge pumping current I.sub.cp2(s) has a low pass filter feature.

(65) The cutoff frequency .sub.c must be much smaller than the frequency .sub.m of the modulation voltage signal V.sub.m so that the second charge pumping current I.sub.cp2 is integrated to form the modulation voltage signal V.sub.m in the form of a triangular wave.

(66) Here, a resistance value of the second resistor (R.sub.2) must be increased or the capacitance of the third capacitor (C.sub.3) or the fourth capacitor (C.sub.4) must be increased to make the cutoff frequency .sub.c lower than the frequency of the modulation voltage signal V.sub.m.

(67) When the capacitance of the third capacitor (C.sub.3) or the fourth capacitor (C.sub.4) is made larger than the resistance value of the second resistor (R.sub.2), the chip area is further increased.

(68) According to embodiments of the present disclosure the third capacitor (C.sub.3) and fourth capacitor (C.sub.4) can have relatively small values of capacitance by increasing the resistance value of the second resistor (R.sub.2), it is possible to realize a clock generator having a small chip area. Therefore, the clock generator can be integrated as an on-chip type.

(69) In this case, since the second clock generator 200 has an open loop structure and is located outside of the first clock generator 100, the ripple noise of the first clock generator 100 is not formed even in the case in which the resistance value of the second resistor R.sub.2 is increased as described above.

(70) The embodiments described in the present specification and the accompanying drawings are merely illustrative of some of the technical spirit of the present disclosure. Therefore, it is obvious that the embodiments disclosed in the present specification are intended to be illustrative rather than limiting the technical spirit of the present disclosure, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. Modifications and specific examples that can be readily devised by a person having ordinary skills in the art within the scope of the technical idea suggested in the specification and drawings of the present disclosure are to be construed as being embraced within the scope of the present disclosure.