Load control device having a wide output range

Abstract

A load control device (e.g., an LED driver) for controlling the intensity of a lighting load (e.g., an LED light source) may provide a wide output range and flicker-free adjustment of the intensity of the lighting load. The load control device may comprise a load regulation circuit, a control circuit, and a filter circuit (e.g., a boxcar filter circuit) that operates in a different manner in dependence upon a target current. When the intensity of the lighting load is near a low-end intensity, the control circuit may adjust an operating frequency of the load regulation circuit in response to the target current, and may control the filter circuit to filter a current feedback signal during a filter window that repeats on periodic basis. When the intensity of the lighting load is near a high-end intensity, the control circuit may control the filter circuit to constantly filter the current feedback signal.

Claims

1. A method of controlling an intensity of a lighting load, the method comprising: controlling, by a load regulation circuit, a magnitude of a load current conducted through the lighting load to adjust the intensity of the lighting load between a low-end intensity and a high-end intensity; filtering a current feedback signal received from the load regulation circuit to generate a filtered feedback signal; adjusting the magnitude of the load current towards a target current in response to the filtered feedback signal; and adjusting an operating frequency of the load regulation circuit in response to the target current when the intensity of the lighting load is near the low-end intensity; wherein filtering the current feedback signal comprises filtering the current feedback signal during a filter window that repeats on a periodic basis when the intensity of the lighting load is near the low-end intensity, and constantly filtering the current feedback signal when the intensity of the lighting load is near the high-end intensity.

2. The method of claim 1, wherein adjusting the operating frequency of the load regulation circuit in response to the target current when the intensity of the lighting load is near the low-end intensity comprises adjusting the operating frequency of the load regulation circuit in response to the target current when the magnitude of the target current is less than a transition current.

3. The method of claim 2, wherein filtering the current feedback signal comprises filtering the current feedback signal during the filter window when the magnitude of the target current is less than the transition current, and constantly filtering the current feedback signal when the magnitude of the target current is greater than the transition current.

4. The method of claim 3, further comprising: rendering a semiconductor switch of the load regulation circuit conductive for an on-time during each operating cycle of the load regulation circuit.

5. The method of claim 4, further comprising, when the magnitude of the target current is greater than the transition current, maintaining the operating frequency of the load regulation circuit constant and adjusting the on-time of the semiconductor switch of the load regulation circuit in response to the target current.

6. The method of claim 5, further comprising: when the magnitude of the target current is greater than the transition current, adjusting a magnitude of a target-current control signal to adjust the on-time of the semiconductor switch of the load regulation circuit; and when the magnitude of the target current is less than the transition current, maintaining the magnitude of the target-current control signal constant and adjusting the operating frequency of the load regulation circuit in response to the target current.

7. The method of claim 5, further comprising: generating a target-current control signal; controlling, by an analog control loop circuit, the semiconductor switch of the load regulation circuit to control the magnitude of the load current in response to the target-current control signal; and when the magnitude of the target current is less than the transition current, maintaining the magnitude of the target-current control signal constant and adjusting the operating frequency of the load regulation circuit in response to the target current.

8. The method of claim 3, wherein filtering the current feedback signal comprises filtering the current feedback signal with a filter circuit.

9. The method of claim 8, further comprising: controlling the filter circuit with a periodic signal when the magnitude of the target current is less than the transition current; and controlling the filter circuit with a constant signal when the magnitude of the target current is greater than the transition current.

10. The method of claim 9, wherein the periodic signal has a maximum duty cycle when the magnitude of the target current is greater than the transition current.

11. The method of claim 10, wherein the maximum duty cycle is 100%.

12. The method of claim 10, wherein the maximum duty cycle is greater than approximately 90%.

13. The method of claim 9, further comprising generating a frequency control signal for controlling the operating frequency of the load regulation circuit, wherein the periodic signal for controlling the filter circuit has a constant on-time and is synchronized with the frequency control signal.

14. The method of claim 13, wherein the on-time of the periodic signal for controlling the filter circuit is equal to a minimum period of the frequency control signal.

15. A method of controlling an intensity of a lighting load, the method comprising: controlling, by a load regulation circuit, a magnitude of a load current conducted through the lighting load to adjust the intensity of the lighting load; filtering a current feedback signal received from the load regulation circuit to generate a filtered feedback signal; adjusting the magnitude of the load current towards a target current in response to the filtered feedback signal; and adjusting an operating frequency of the load regulation circuit in response to the target current when the magnitude of the target current of the lighting load is less than a transition current; wherein filtering the current feedback signal comprises filtering the current feedback signal during a filter window that repeats on a periodic basis when the magnitude of the target current of the lighting load is less than the transition current, and constantly filtering the current feedback signal when the magnitude of the target current of the lighting load is greater than the transition current.

16. The method of claim 15, further comprising: rendering a semiconductor switch of the load regulation circuit conductive for an on-time during each operating cycle of the load regulation circuit; and when the magnitude of the target current is greater than the transition current, maintaining the operating frequency of the load regulation circuit constant.

17. The method of claim 16, further comprising: when the magnitude of the target current is greater than the transition current, adjusting the on-time of the semiconductor switch of the load regulation circuit in response to the target current; and when the magnitude of the target current is less than the transition current, adjusting the operating frequency of the load regulation circuit in response to the target current.

18. The method of claim 16, further comprising: generating a target-current control signal; controlling, by an analog control loop circuit, the semiconductor switch of the load regulation circuit to control the magnitude of the load current in response to the target-current control signal; and when the magnitude of the target current is less than the transition current, maintaining the magnitude of the target-current control signal constant and adjusting the operating frequency of the load regulation circuit in response to the target current.

19. The method of claim 15, wherein filtering the current feedback signal comprises filtering the current feedback signal with a filter circuit, and the method further comprises controlling the filter circuit with a periodic signal when the magnitude of the target current is less than the transition current, and controlling the filter circuit with a constant signal when the magnitude of the target current is greater than the transition current.

20. The method of claim 19, further comprising generating a frequency control signal for controlling the operating frequency of the load regulation circuit, wherein the periodic signal for controlling the filter circuit has a constant on-time and is synchronized with the frequency control signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a simplified block diagram of an example light-emitting diode (LED) driver for controlling the intensity of an LED light source.

(2) FIG. 2 is a simplified schematic diagram of an example LED driver.

(3) FIG. 3A is an example plot of a relationship between an operating frequency and a target current of the LED driver of FIG. 2.

(4) FIG. 3B is an example plot of a relationship between a magnitude of a target-current control signal and the target current of the LED driver of FIG. 2.

(5) FIGS. 4A and 4B show example waveforms illustrating the operation of the LED driver of FIG. 2.

(6) FIG. 5A shows example waveforms illustrating the operation of the LED driver of FIG. 2 when the LED driver is learning a load voltage.

(7) FIG. 5B shows example waveforms illustrating the operation of the LED driver of FIG. 2 when the LED driver is turning on an LED light source using the learned load voltage.

(8) FIG. 6 is a simplified flowchart of an example control procedure for controlling an LED driver to control a magnitude of a load current conducted through a lighting load.

DETAILED DESCRIPTION OF THE INVENTION

(9) FIG. 1 is a simplified block diagram of a load control device, such as a light-emitting diode (LED) driver 100 for controlling the intensity of an LED light source 102 (e.g., an LED light engine). The LED light source 102 is shown in FIG. 1 as a plurality of LEDs connected in series but may comprise a single LED or a plurality of LEDs connected in parallel or a suitable combination thereof, depending on the particular lighting system. In addition, the LED light source 102 may alternatively comprise one or more organic light-emitting diodes (OLEDs). The LED driver 100 may be adapted to work with a plurality of different LED light sources, which may be rated at different magnitudes of load current and voltage.

(10) The LED driver 100 may comprise a hot terminal H and a neutral terminal N for receiving an alternating-current (AC) voltage V.sub.AC from an AC power source (not shown). The LED driver 100 may comprise a radio-frequency (RFI) filter and rectifier circuit 110, which may receive the AC voltage V.sub.AC. The RFI filter and rectifier circuit 110 may operate to minimize the noise provided on the AC power source and to generate a rectified voltage V.sub.RECT. The LED driver 100 may comprise a power converter circuit 120, which may receive the rectified voltage V.sub.RECT and generate a variable direct-current (DC) bus voltage V.sub.BUS across a bus capacitor C.sub.BUS. The power converter circuit 120 may comprise any suitable power converter circuit for generating an appropriate bus voltage, such as, for example, a boost converter, a buck converter, a buck-boost converter, a flyback converter, a single-ended primary-inductance converter (SEPIC), a uk converter, or other suitable power converter circuit. The power converter circuit 120 may also provide electrical isolation between the AC power source and the LED light source 102, and operate as a power factor correction (PFC) circuit to adjust the power factor of the LED driver 100 towards a power factor of one.

(11) The LED driver 100 may comprise a load regulation circuit, e.g., an LED drive circuit 130, which may receive the bus voltage V.sub.BUS and control the amount of power delivered to the LED light source 102 so as to control the intensity of the LED light source. For example, the LED drive circuit 130 may comprise a buck converter, as will be described in greater detail below. To control the amount of power delivered to the LED light source 102, the LED drive circuit 130 may be configured to control an average magnitude of a load current I.sub.LOAD conducted through the LED light source 102.

(12) The LED driver 100 may include a control circuit 140 for controlling the operation of the power converter circuit 120 and the LED drive circuit 130. The control circuit 140 may comprise, for example, a controller or any other suitable processing device, such as, for example, a microcontroller, a programmable logic device (PLD), a microprocessor, an application specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). The control circuit 140 may be configured to control the LED drive circuit 130 to control the average magnitude of the load current I.sub.LOAD conducted through the LED light source to control the amount of power delivered to the LED light source. The control circuit 140 may be configured to control the LED drive circuit 130 to turn the LED light source 102 on and off and to adjust (e.g., dim) a present intensity L.sub.PRES of the LED light source 102 towards a target intensity L.sub.TRGT, which may range across a dimming range of the LED light source, e.g., between a low-end intensity L.sub.LE (e.g., approximately 0.1%-1.0%) and a high-end intensity L.sub.HE (e.g., approximately 100%).

(13) The control circuit may be configured to fade (e.g., gradually adjust over a period of time) the target intensity L.sub.TRGT (and thus the present intensity L.sub.PRES) of the LED light source 102. The control circuit 140 may be configured to fade the LED light source 102 from off to on by slowly increasing the present intensity L.sub.PRES of the LED light source from a minimum fading intensity L.sub.FADE-MIN, which may be less than the low-end intensity L.sub.LE (e.g., such as approximately 0.02%), to the target intensity L.sub.TRGT. The control circuit 140 may be configured to fade the LED light source 102 from on to off by slowly decreasing the present intensity L.sub.PRES of the LED light source from an initial intensity greater than or equal to the low-end intensity L.sub.LE to the minimum fading intensity L.sub.FADE-MIN at which point the control circuit 140 may turn off the LED light source.

(14) The control circuit 140 may be coupled to a memory 112 configured to store operational characteristics of the LED driver 100 (e.g., the target intensity L.sub.TRGT, the low-end intensity L.sub.LE, the high-end intensity L.sub.HE, etc.). The memory 112 may be implemented as an external integrated circuit (IC) or as an internal circuit of the control circuit 140. The LED driver 100 may also comprise a communication circuit 114, which may be coupled to, for example, a wired communication link or a wireless communication link, such as a radio-frequency (RF) communication link or an infrared (IR) communication link. The control circuit 140 may be configured to determine the target intensity L.sub.TRGT of the LED light source 102 or the operational characteristics stored in the memory 112 in response to digital messages received via the communication circuit 114. In response to receiving a command to turn on the LED light source 102, the control circuit 140 may be configured to execute the turn-on routine. The LED driver 100 may further comprise a power supply 116, which may receive the rectified voltage V.sub.RECT and generate a direct-current (DC) supply voltage V.sub.CC (e.g., approximately 5 volts) for powering the low-voltage circuitry of the LED driver. In addition, the power supply 116 may generate one or more additional supply voltages, for example, for powering control circuitry of the power converter circuit 120 and/or the LED drive circuit 130.

(15) The control circuit 140 may comprise a digital control circuit, such as a processor 142, which may be, for example, a microprocessor, a programmable logic device (PLD), a microcontroller, an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other suitable processing device or controller. The control circuit 140 may also comprise an analog control loop circuit 150. The processor 142 and the analog control loop circuit 150 may operate together to control the LED driver circuit 130 to adjust the average magnitude of the load current I.sub.LOAD towards a target current I.sub.TRGT. The target current I.sub.TRGT may be dependent upon the target intensity L.sub.TRGT (e.g., a function of the target intensity L.sub.TRGT). The processor 142 may generate a target-current control signal V.sub.I-TRGT, which may have a DC magnitude or a duty cycle that may indicate the target current I.sub.TRGT. The processor 142 may control the DC magnitude or the duty cycle of the target-current control signal V.sub.I-TRGT based on the target intensity L.sub.TRGT of the LED light source 102.

(16) The control circuit 140 may also comprise a latch circuit 160 that may generate a drive signal V.sub.DR for controlling the operation of the LED drive circuit 130 (e.g., for rendering a switching transistor of the LED drive circuit 130 conductive and non-conductive to regulate the average magnitude of the load current I.sub.LOAD towards the target current I.sub.TRGT). The processor 142 may generate a frequency control signal V.sub.FREQ that may set an operating frequency for of the LED drive circuit 130. In response to the frequency control signal V.sub.FREQ, the latch circuit 160 may control the drive signal V.sub.DR to render the switching transistor of the LED drive circuit 130 conductive to start a cycle of the LED drive circuit, at which time the LED drive circuit may begin to conduct an inductor current I.sub.L conducted through an inductor (not shown) of the LED drive circuit 130. The analog control loop circuit 150 may generate a peak current threshold V.sub.TH-PK, which may be used by the latch circuit 160 to render the switching transistor of the LED drive circuit 130 non-conductive in response to the magnitude of the inductor current I.sub.L.

(17) The LED driver 100 may comprise an amplifier circuit 170, which may receive a current feedback signal V.sub.I-FB from the LED drive circuit 130. The amplifier circuit 170 may amplify the current feedback signal V.sub.I-FB to generate an instantaneous current feedback signal V.sub.I-INST, which may indicate an instantaneous magnitude of the inductor current k flowing through the inductor of the LED drive circuit 130.

(18) The LED driver 100 may further comprise a filter circuit 180, such as a boxcar filter circuit. The filter circuit 180 may receive the instantaneous current feedback signal V.sub.I-INST and generate a filtered feedback signal, e.g., an average current feedback signal V.sub.I-AVE, which may indicate an average magnitude of the inductor current I.sub.L flowing through the inductor of the LED drive circuit 130 (e.g., over a specific time window). The processor 142 may generate a filter control signal V.sub.FILTER (e.g., a filter control signal) for controlling the operation of the filter circuit 180, e.g., to control when the filter circuit 180 filters the instantaneous current feedback signal V.sub.I-INST. For example, the processor 142 may control the filter control signal V.sub.FILTER to allow the filter circuit 180 to filter the instantaneous current feedback signal V.sub.I-INST over a filter window period T.sub.FILTER during each cycle of the LED drive circuit 130. The processor 142 may control the filter control signal V.sub.FILTER in a manner that is synchronous with the frequency control signal V.sub.FREQ, e.g., to start a cycle of the LED drive circuit 130 at the beginning of the filter window period T.sub.FILTER. For example, the filter window period T.sub.FILTER may have the same length during each cycle of the LED drive circuit 130 independent of the frequency of the frequency control signal V.sub.FREQ. The magnitude of the average current feedback signal V.sub.I-AVE may indicate the average magnitude of the inductor current k during the filter window period T.sub.FILTER (e.g., while the filter circuit 180 is filtering the instantaneous current feedback signal V.sub.I-INST).

(19) The analog control loop circuit 150 of the control circuit 140 may receive the average current feedback signal V.sub.I-AVE and the latch circuit 160 may receive the instantaneous current feedback signal V.sub.I-INST. The analog control loop circuit 150 may adjust the magnitude of the peak current threshold V.sub.TH-PK in response to the target-current control signal V.sub.I-TRGT and the average current feedback signal V.sub.I-AVE. The latch circuit 160 may control the drive signal V.sub.DR to render the switching transistor of the LED drive circuit 130 conductive in response to the frequency control signal V.sub.FREQ (e.g., at the beginning of a cycle of the LED drive circuit 130). The latch circuit 160 may control the drive signal V.sub.DR to render the switching transistor non-conductive in response to the peak current threshold V.sub.TH-PK and the instantaneous current feedback signal V.sub.I-INST. After rendering the switching transistor of the LED drive circuit 130 non-conductive, the latch circuit 160 may remain in a latched state and maintain the switching transistor non-conductive until the beginning of the next cycle of the LED drive circuit 130.

(20) The control circuit 140 may be configured to determine or learn (e.g., measure or receive an indication of) one or more operational characteristics of the LED light source 102 (e.g., learned load characteristics). For example, the control circuit 140 may be configured to determine a voltage representative of the magnitude of the load voltage V.sub.LOAD. The magnitude of the load voltage V.sub.LOAD generated across the LED light source 102 may be dependent upon the magnitude of the load current I.sub.LOAD (e.g., the target load current I.sub.TRGT to which the control circuit 140 is regulating the load current I.sub.LOAD) as well as the internal circuitry of the LED light source. The control circuit 140 may be configured to determine (e.g., measure) the magnitude of the load voltage V.sub.LOAD and/or store the measurement in the memory 112 as a learned load voltage V.sub.LEARNED. The control circuit 140 may be configured to determine (e.g., measure) the magnitude of the load voltage V.sub.LOAD using a load voltage feedback signal V.sub.V-LOAD received from the LED drive circuit 130. For example, the LED drive circuit 130 may comprise a resistive divider circuit (not shown) coupled across the LED light source 102 for generating the load voltage feedback signal V.sub.V-LAD as a scaled load voltage. The load voltage feedback signal V.sub.V-LOAD may be received by an analog-to-digital converter (ADC) of the processor 142 for learning the magnitude of the load voltage V.sub.LOAD.

(21) The control circuit 140 may be configured to determine (e.g., measure) the magnitude of the load voltage V.sub.LOAD when the target intensity L.sub.TRGT is at or near the low-end intensity L.sub.LE. For example, the control circuit 140 may be configured to determine (e.g., measure) the magnitude of the load voltage V.sub.LOAD while the control circuit 140 is fading the LED light source 102 from on to off, for example, while the average magnitude of the load current I.sub.LOAD is within a measurement window that may range from a maximum learning threshold I.sub.LEARN-MAX to a minimum learning threshold I.sub.LEARN-MIN. The maximum learning threshold I.sub.LEARN-MAX and the minimum learning threshold I.sub.LEARN-MIN may be functions of a rated (or maximum) current I.sub.RATED of the LED light source 102, for example, 0.0020.Math.I.sub.RATED and 0.0002.Math.I.sub.RATED, respectively.

(22) The control circuit 140 may be configured to control the LED drive circuit 130 using the learned load voltage V.sub.LEARNED. For example, the control circuit 140 may be configured to control the LED drive circuit 130 in response to the learned load voltage V.sub.LEARNED when turning on the LED light source 102. The control circuit 140 may be configured to charge (e.g., pre-charge) an output capacitor (not shown) of the LED drive circuit 130 prior to attempting to turn on the LED light source 102. In response to receiving a command to turn on the LED light source 102 and/or in response to power being applied to the LED driver 100 to turn on the LED light source, the control circuit 140 may pre-charge the output capacitor until the magnitude of the load voltage V.sub.LOAD reaches or exceeds a pre-charge voltage threshold V.sub.TH-PC, which may be, for example, a function of the learned load voltage V.sub.LEARNED (e.g., as will be described in greater detail below). The pre-charging of the output capacitor may allow the LED driver 100 to turn-on the LED light source 102 quickly and consistently, e.g., when fading on to the low-end intensity L.sub.LE.

(23) The control circuit 140 may be configured to determine an operating parameter (e.g., a pre-load parameter) as a function of the learned load voltage V.sub.LEARNED and use the operating parameter to control the LED drive circuit 130 to pre-charge the output capacitor of the LED drive circuit 130 prior to turning the LED light source 102 on (e.g., as will be described in greater detail below). For example, the control circuit 140 may be configured to determine the DC magnitude or the duty cycle of the target-current control signal V.sub.I-TRGT to use while pre-charging the output capacitor of the LED drive circuit 130 as a function of the learned load voltage V.sub.LEARNED. In addition, the processor 142 may generate a start-up control signal V.sub.START-UP for controlling the analog control loop circuit 150 while pre-charging the output capacitor of the LED drive circuit 130 to maintain the output of the analog control loop circuit 150 at a predetermined voltage.

(24) After the magnitude of the load voltage V.sub.LOAD reaches or exceeds the pre-charge voltage threshold V.sub.TH-PC, the processor 142 may control the start-up control signal V.sub.START-UP to allow the analog control loop circuit 150 to control the LED drive circuit 130 using closed loop control in response to the current feedback signal V.sub.I-FB to regulate the magnitude of the load current I.sub.LOAD towards the target current I.sub.TRGT.

(25) FIG. 2 is a simplified schematic diagram of a load regulation device, e.g., an LED driver 200 (such as the LED driver 100 of FIG. 1) for controlling the intensity of an LED light source 202. The LED driver 200 may comprise a bus capacitor C.sub.BUS for storing a bus voltage V.sub.BUS, which may be generated by a power converter circuit (e.g., the power converter circuit 120 of the LED driver 100). The LED driver 200 may comprise an LED drive circuit 230, which may be configured to control the magnitude of a load current I.sub.LOAD conducted through the LED light source 202. The LED driver 200 may further comprise a control circuit 240, which may be a hybrid analog-digital control circuit (e.g., the control circuit 140 of the LED driver 100). The control circuit 240 may comprise a processor 242, a low-pass filter circuit 244, an analog control loop circuit (e.g., which may include an integrator circuit 250), and a latch circuit 260. The latch circuit 260 may generate a drive signal V.sub.DR, which may be provided to the LED driver circuit 230. The LED driver 200 may further comprise an amplifier circuit 270 and a filter circuit 280 (e.g., a boxcar filter circuit) for generating an instantaneous current feedback signal V.sub.I-INST and an average current feedback signal V.sub.I-AVE, respectively.

(26) As shown in FIG. 2, the LED drive circuit 230 may comprise a buck converter. The LED drive circuit 230 may comprise a switching transistor, e.g., a field-effect transistor (FET) Q232, which may be controlled in response to the drive signal V.sub.DR to control the average magnitude of the load current I.sub.LOAD. The LED drive circuit 230 may also comprise an inductor L234, a switching diode D235, an output capacitor C236, and a feedback resistor R238. The drive signal V.sub.DR may be coupled to a gate of the FET Q232 through a gate drive circuit 239. When the FET Q232 is conductive, the inductor L234 may conduct an inductor current I.sub.L from the bus capacitor C.sub.BUS through the parallel combination of the output capacitor C236 and the LED light source 202. When the FET Q232 is non-conductive, the inductor L234 may conduct the inductor current I.sub.L through the switching diode D235 and the parallel combination of the output capacitor C236, and the LED light source 202. The LED light source 202 may conduct the average component of the inductor current I.sub.L and the output capacitor C236 may conduct the transient component of the inductor current I.sub.L. The average magnitude of the load current I.sub.LOAD may be approximately equal to the average magnitude of the inductor current I.sub.L.

(27) The current feedback signal V.sub.I-FB may be generated across the feedback resistor R238 of the LED drive circuit 230 and may be proportional to the magnitude of the inductor current I.sub.L. The current feedback signal V.sub.I-FB may be received by the amplifier circuit 270. The amplifier circuit 270 may comprise an operational amplifier U272 and may be configured as a non-inverting amplifier circuit. The operational amplifier U272 may have a non-inverting input that may receive the current feedback signal V.sub.I-FB. The amplifier circuit 270 may also comprise a resistor R274 coupled between an inverting input of the operational amplifier U272 and circuit common, and a resistor R276 coupled between the inverting input and an output of the operational amplifier U272. The amplifier circuit 270 may be configured to generate the instantaneous current feedback signal V.sub.I-INST, which may be an amplified version of the current feedback signal V.sub.I-FB and may indicate the instantaneous magnitude of the inductor current k.

(28) The filter circuit 280 may filter the instantaneous current feedback signal V.sub.I-INST to generate the average load current signal V.sub.I-AVE, which may indicate the average magnitude of the inductor current k. The filter circuit 280 may comprise a controllable switching circuit 282 and a low-pass filter circuit (e.g., a third-order low-pass filter circuit) that includes resistors R284, R286, R288 and capacitors C285, C287, C289. The processor 242 may generate a filter control signal V.sub.FILTER for rendering the controllable switching circuit 282 conductive and non-conductive. When the controllable switching circuit 282 is conductive, the filter circuit 280 may be configured to filter the instantaneous current feedback signal V.sub.I-INST to generate the average current feedback signal V.sub.I-AVE. When the controllable switching circuit 282 is non-conductive, the capacitors C285, C287, C289 of the filter circuit 280 may maintain the magnitude of the average current feedback signal V.sub.I-AVE at a value that indicates the average magnitude of the inductor current I.sub.L during the period of time when the controllable switching circuit 282 was previously conductive.

(29) The processor 242 may generate a pulse-width modulated (PWM) signal V.sub.PWM, which may be received by the low-pass filter circuit 244 of the control circuit 240. The low-pass filter circuit 244 may be configured to generate a target-current control signal V.sub.I-TRGT, which may have a DC magnitude that indicates the target current I.sub.TRGT. For example, the low-pass filter circuit 244 may comprise a resistor-capacitor (RC) circuit having a resistor R246 and a capacitor C248. The processor 242 may be configured to control the duty cycle of the pulse-width modulated signal V.sub.PWM to adjust the magnitude of the target-current control signal V.sub.I-TRGT.

(30) The average current feedback signal V.sub.I-AVE generated by the filter circuit 280 and the target-current control signal V.sub.I-TRGT generated by the low-pass filter circuit 244 may be received by the integrator circuit 250. The integrator circuit 250 may comprise an operational amplifier U252 having a non-inverting input coupled to the target-current control signal V.sub.I-TRGT and an inverting input coupled to the average current feedback signal V.sub.I-AVE via a resistor R254. The integrator circuit 250 may comprise a capacitor C256 coupled between the inverting input and an output of the operational amplifier U252, such that the integrator circuit 250 may be configured to integrate the error between the average current feedback signal V.sub.I-AVE and the target-current control signal V.sub.I-TRGT. The integrator circuit 250 may generate a peak current threshold V.sub.TH-PK having a DC magnitude that may increase or decrease by amounts dependent upon the error between the magnitude of the target-current control signal V.sub.I-TRGT and the average current feedback signal V.sub.I-AVE. The integrator circuit 250 may comprise a controllable switching circuit 258 coupled in parallel with the capacitor C256. The controllable switching circuit 258 may be rendered conductive and non-conductive in response to a startup control signal V.sub.START-UP received from the processor 242 during a startup routine (e.g., as will be described in greater detail below).

(31) The latch circuit 260 may receive the peak current threshold V.sub.TH-PK generated by the integrator circuit 250 and the instantaneous current feedback signal V-INST generated by the amplifier circuit 270. The latch circuit 260 may comprise a comparator U262 configured to compare the magnitude of the instantaneous current feedback signal V-INST to the magnitude of the peak current threshold V.sub.TH. The comparator U262 may generate a latch control signal V.sub.LATCH at an output. When the magnitude of the instantaneous current feedback signal V-INST is less than the magnitude of the peak current threshold VT, the comparator U262 may drive the latch control signal V.sub.LATCH at the output high (e.g., towards the supply voltage V.sub.CC). When the magnitude of the instantaneous current feedback signal V.sub.I-INST exceeds the magnitude of the peak current threshold V.sub.TH-PK, the comparator U262 may drive the latch control signal V.sub.LATCH at the output low (e.g., towards circuit common).

(32) The processor 242 may generate a frequency control signal V.sub.FREQ that may set an operating frequency f.sub.OP of the LED drive circuit 230. The latch circuit 260 may comprise a PWM control circuit 266, which may receive the latch control signal V.sub.LATCH from the comparator U262 and the frequency control signal V.sub.FREQ from the processor 242. The PWM control circuit 266 may generate the drive signal V.sub.DR, which may be received by the gate drive circuit 239 of the LED drive circuit 230. When the frequency control signal V.sub.FREQ is driven high at the beginning of a cycle of the LED driver circuit 230, the PWM control circuit 266 may drive the magnitude of the drive signal V.sub.DR high, which may render the FET Q232 of the LED drive circuit 230 conductive. When the magnitude of the instantaneous current feedback signal V.sub.I-INST exceeds the magnitude of the peak current threshold signal VT, the comparator U262 may drive the latch control signal V.sub.LATCH low, which may cause the PWM control circuit 266 to drive the magnitude of the drive signal V.sub.DR low. The PWM control circuit 266 may maintain the magnitude of the drive signal V.sub.DR low until the processor 242 drives the magnitude of the frequency control signal V.sub.FREQ high once again at the end of the present cycle and the beginning of the next cycle of the LED drive circuit 230.

(33) The processor 242 may control the frequency of the frequency control signal V.sub.FREQ and the duty cycle of the pulse-width modulated control signal V.sub.PWM (and thus the magnitude of the target-current control signal V.sub.I-TRGT) in dependence upon the target current I.sub.TRGT of the LED light source 202 using open loop control. FIG. 3A is an example plot of the relationship 300 between the frequency of the frequency control signal V.sub.FREQ (e.g., the operating frequency f.sub.OP of the LED drive circuit 230) and the target current I.sub.TRGT. FIG. 3B is an example plot of the relationship 310 between the magnitude of the target-current control signal V.sub.I-TRGT and the target current I.sub.TRGT. For example, the target current I.sub.TRGT may range between a high-end current I.sub.HE (e.g., approximately 150 mA) at the high-end intensity L.sub.HE and a low-end current ILE (e.g., approximately 150 IA) at the low-end intensity L.sub.LE.

(34) The processor 242 may operate in first and second modes of operation depending upon whether the target current I.sub.TRGT is less than or greater than approximately a transition current IRAN (e.g., approximately 16.8 mA). Near the low-end intensity L.sub.LE (e.g., when the target current I.sub.TRGT is less than approximately the transition current I.sub.TRAN), the processor 242 may operate in the first operating mode during which the processor 242 may adjust the frequency of the frequency control signal V.sub.FREQ between a minimum operating frequency f.sub.MIN and a maximum operating frequency f.sub.MAX (e.g., linearly) with respect to the target current I.sub.TRGT while holding the magnitude of the target-current control signal V.sub.I-RGT constant (e.g., at a minimum voltage V.sub.MIN). Near the high-end intensity L.sub.HE (e.g., when the target current I.sub.TRGT is greater than or equal to approximately the transition current I.sub.TRAN), the processor 242 may operate in the second operating mode during which the processor 242 may adjust the magnitude of the target-current control signal V.sub.I-TRGT between the minimum voltage V.sub.MIN and a maximum voltage V.sub.MAX (e.g., linearly) with respect to the target current I.sub.TRGT while holding the frequency control signal V.sub.FREQ constant (e.g., at the maximum operating frequency f.sub.MAX). For example, the maximum operating frequency f.sub.MAX may be approximately 140 kHz and the minimum operating frequency f.sub.MIN may be approximately 1250 Hz. For example, the maximum voltage V.sub.MAX may be approximately 3.3 V and the minimum voltage V.sub.MIN may be approximately 44 mV.

(35) FIGS. 4A and 4B show example waveforms illustrating the operation of the LED driver 200 shown in FIG. 2. FIG. 4A shows example waveforms illustrating the operation of the LED driver 200 when the target current I.sub.TRGT is less than the transition current I.sub.TRAN. The processor 242 may generate the frequency control signal V.sub.FREQ to set the operating frequency f.sub.OP of the LED drive circuit 230. For example, an operating period T.sub.OP of the LED drive circuit 230 may be equal to the period of the frequency control signal V.sub.FREQ. The processor 242 may set the operating frequency f.sub.OP (and thus the operating period T.sub.OP) in dependence upon the target current I.sub.TRGT (e.g., as shown in FIG. 3A). The processor 242 may generate the frequency control signal V.sub.FREQ to have a predetermined on-time T.sub.FREQ-ON, which may have the same length each cycle of the LED drive circuit 130 (e.g., independent of the frequency of the frequency control signal V.sub.FREQ or the target current I.sub.TRGT).

(36) The processor 242 may generate the filter control signal V.sub.FILTER in a synchronous manner with respect to the frequency control signal V.sub.FREQ. For example, the processor 242 may drive both the filter control signal V.sub.FILTER and the frequency control signal V.sub.FREQ high at the same time to start a cycle of the LED drive circuit 230 (e.g., at time t.sub.1 in FIG. 4A). At time t.sub.1, the PWM control circuit 266 of the latch circuit 260 may drive the magnitude of the drive signal V.sub.DR high (e.g., towards the supply voltage V.sub.CC) causing the FET Q232 of the LED drive circuit 230 to be rendered conductive. At this time, the inductor L234 of the LED drive circuit 230 may begin to conduct the inductor current I.sub.L. When the instantaneous current feedback signal V.sub.I-INST (which may be proportional to the magnitude of the inductor current I.sub.L) exceeds the magnitude of the peak current threshold signal V.sub.TH, the PWM control circuit 266 may drive the magnitude of the drive voltage V.sub.DR low (e.g., towards circuit common) as shown at time t.sub.2 of FIG. 4A, which may cause the FET Q232 of the LED drive circuit 230 to be rendered non-conductive. The drive signal V.sub.DR may be characterized by an on-time T.sub.ON and a period that may be equal to the operating period T.sub.OP as shown in FIG. 4A. The PWM control circuit 266 may render the FET Q232 conductive for the length of the on-time T.sub.ON of the drive signal V.sub.DR during each operating cycle of the LED drive circuit 230. The inductor current I.sub.L may have a peak magnitude I.sub.PK as shown in FIG. 4A. The magnitude of the inductor current k may begin to decrease at time t.sub.2 until the magnitude of the inductor current k drops to zero amps at time t.sub.3.

(37) The processor 242 may drive the frequency control signal V.sub.FREQ low at the end of the predetermined on-time T.sub.FREQ-ON (e.g., at time t.sub.4 in FIG. 4A). The processor 242 may drive the filter control signal V.sub.FILTER low at the end of a filter window period T.sub.FILTER (e.g., at time t.sub.5 in FIG. 4A). The processor 242 may drive both the filter control signal V.sub.FILTER and the frequency control signal V.sub.FREQ high to start another cycle of the LED drive circuit 230 at the end of the operating period T.sub.OP (e.g., at time t.sub.6 in FIG. 4A).

(38) When the target current I.sub.TRGT is less than the transition current I.sub.TRAN, the processor 242 may hold the magnitude of the target-current control signal V.sub.I-TRGT constant at the minimum voltage V.sub.MIN, and linearly adjust the frequency of the frequency control signal V.sub.FREQ between the minimum frequency f.sub.MIN and the maximum frequency f.sub.MAX as a function of the target current I.sub.TRGT (e.g., as shown in FIGS. 3A and 3B). The filter circuit 280 may be configured to filter the instantaneous current feedback signal V.sub.I-INST during the filter window period T.sub.FILTER each cycle of the LED drive circuit 230. When the target current I.sub.TRGT is less than the transition current I.sub.TRAN, the filter control signal V.sub.FILTER may be a periodic signal characterized by the operating frequency f.sub.OP. The processor 242 may maintain the length of the filter window period T.sub.FILTER of the filter control signal V.sub.FILTER constant from one cycle of the LED driver circuit 230 to the next cycle independent of the frequency of the frequency control signal V.sub.FREQ. A duty cycle of the filter control signal V.sub.FILTER may vary as the frequency of the frequency control signal V.sub.FREQ is adjusted.

(39) Since the target-current control signal V.sub.I-TRGT and the filter window period T.sub.FILTER are held constant, the on-time T.sub.ON of the drive signal V.sub.DR may be approximately the same each cycle of the LED drive circuit 230 even though the frequency of the drive signal V.sub.DR (e.g., the operating period T.sub.OP) may vary in dependence upon the target current I.sub.TRGT. As a result, the peak and average magnitudes of the inductor current I.sub.L during the filter window period T.sub.FILTER may be approximately the same from one cycle to the next of the LED drive circuit 230 independent of the target current I.sub.TRGT when the target current I.sub.TRGT is less than the transition current I.sub.TRAN. The length of the filter window period T.sub.FILTER may be sized to ensure that the inductor current I.sub.L drops to zero amps before the end of the filter window period T.sub.FILTER when the target current I.sub.TRGT is less than the transition current I.sub.TRAN. When the target current is less than the transition current I.sub.TRAN, the LED drive circuit 230 may be configured to operate in a discontinuous mode of operation.

(40) FIG. 4B shows example waveforms illustrating the operation of the LED driver 200 when the target current I.sub.TRGT is greater than the transition current I.sub.TRAN. When the target current I.sub.TRGT is greater than the transition current I.sub.TRAN, the processor 242 may linearly adjust the magnitude of the target-current control signal V.sub.I-TRGT between the minimum voltage V.sub.MIN and the maximum voltage V.sub.MAX as a function of the target current I.sub.TRGT (e.g., as shown in FIGS. 3A and 3B). In addition, the processor 242 may hold the frequency of the frequency control signal V.sub.FREQ constant at the maximum operating frequency f.sub.MAX (e.g., causing the operating period T.sub.OP to be held constant at a minimum operating period T.sub.MIN). When the target current I.sub.TRGT is greater than the transition current I.sub.TRAN, the processor 242 may control the duty cycle of the filter control signal V.sub.FILTER to a maximum filter duty cycle (e.g., 100%). For example, the operating period T.sub.OP may be equal to the length of the filter window period T.sub.FILTER when the target current I.sub.TRGT is greater than the transition current I.sub.TRAN. As a result, the processor 242 may drive the filter control signal V.sub.FILTER high at all times (e.g., the filter control signal V.sub.FILTER is a constant signal) while the target current I.sub.TRGT is greater than the transition current I.sub.TRAN as shown in FIG. 4B. The average current feedback signal V.sub.I-AVE may indicate the average magnitude of the inductor current I.sub.L when the target current I.sub.TRGT is greater than the transition current I.sub.TRAN. Additionally or alternatively, the processor 242 may drive the filter control signal V.sub.FILTER high approximately all of the time (e.g., almost all of the time), for example at substantially large duty cycle (e.g., approximately 90% or greater).

(41) Because the processor 242 varies the magnitude of the target-current control signal V.sub.I-TRGT as a function of the target current I.sub.TRGT, the length of the on-time T.sub.ON of the drive signal V.sub.DR may vary as a function of the target current I.sub.TRGT even though the frequency of the drive signal V.sub.DR (e.g., the operating period T.sub.OP) is held constant. As the target current I.sub.TRGT increases, the peak current I.sub.PK of the inductor current may increase to a point at which the LED drive circuit 230 may begin to operate in a continuous mode of operation. Since the minimum operating period T.sub.MIN (e.g., the operating period T.sub.OP when the target current I.sub.TRGT is greater than the transition current I.sub.TRAN) may be equal to the length of the filter window time period T.sub.FILTER, the processor 242 may be configured to smoothly transition the LED driver 200 between the first operating mode when the target current I.sub.TRGT is less than the transition current I.sub.TRAN and the second operating mode when the target current I.sub.TRGT is greater than the transition current I.sub.TRAN.

(42) The length of the predetermined on-time T.sub.FREQ-ON of the frequency control signal T.sub.FREQ is less than the length of the operating period T.sub.OP when the target current I.sub.TRGT is greater than the transition current I.sub.TRAN. The processor 242 may drive the frequency control signal T.sub.FREQ low (e.g., at time t.sub.7 in FIG. 4B) and then high (e.g., at time t.sub.8) at the end of each cycle of the LED drive circuit 230. This causes the PWM control circuit 266 of the latch circuit 260 to stop maintaining the magnitude of the drive signal V.sub.DR low, and to drive the magnitude of the drive signal V.sub.DR high again when the frequency control signal T.sub.FREQ is driven high to begin the next cycle of the LED drive circuit 230 (e.g., at time t.sub.8).

(43) The processor 242 of the control circuit 240 may be configured to determine or learn (e.g., measure or receive an indication of) the magnitude of the load voltage V.sub.LOAD and/or store the measurement in memory (e.g., the memory 112) as a learned load voltage V.sub.LEARNED. The magnitude of the load voltage V.sub.LOAD generated across the LED light source 202 may be dependent upon the magnitude of the load current I.sub.LOAD (e.g., the target load current I.sub.TRGT to which the control circuit 240 is regulating the load current I.sub.LOAD) as well as the internal circuitry of the LED light source. The processor 242 may be configured to receive a load voltage feedback signal from the LED drive circuit 230 (e.g., the load voltage feedback signal V.sub.V-LOAD of the LED driver 100), which may be a scaled version of the load voltage V.sub.LOAD generated by a resistive divider circuit (not shown) of the LED drive circuit 230. The processor 242 may sample the load voltage feedback signal using an analog-to-digital converter (ADC) to measure the magnitude of the load voltage V.sub.LOAD.

(44) FIG. 5A shows example waveforms illustrating the operation of the LED driver 200 when the processor 242 is learning the load voltage V.sub.LOAD. The processor 242 may be configured to determine (e.g., measure) the magnitude of the load voltage V.sub.LOAD while the processor 242 is fading the LED light source 202 from on to off. As shown in FIG. 5A, when fading the LED light source 202 from on to off, the processor 242 may begin to decrease the average magnitude of the load current I.sub.LOAD from an initial current I.sub.INIT at time t.sub.0, at which time the magnitude of the load voltage V.sub.LOAD may also begin to decrease, e.g., from an initial voltage V.sub.INIT. The processor 242 may be configured to determine (e.g., measure) the magnitude of the load voltage V.sub.LOAD while the average magnitude of the load current I.sub.LOAD is within a measurement window that may range from a maximum learning threshold I.sub.LEARN-MAX and a minimum learning threshold I.sub.LEARN-MIN (e.g., between times t.sub.WIN-START and t.sub.WIN-END as shown in FIG. 5A). The maximum learning threshold I.sub.LEARN-MAX and the minimum learning threshold I.sub.LEARN-MIN may be functions of a rated (or maximum) current I.sub.RATED of the LED light source 202, for example, 0.0020.Math.I.sub.RATED and 0.0002.Math.I.sub.RATED, respectively. The processor 242 may be configured to periodically sample the load voltage feedback signal during the measurement window, and to process the plurality of samples to determine the learned load voltage V.sub.LEARNED. For example, the processor 242 may be configured to process the plurality of samples of the load voltage feedback signal by calculating an average or median value of the plurality of samples or filtering the samples using a digital low-pass filter.

(45) The processor 242 may be configured to measure the load voltage V.sub.LOAD and determine the learned load voltage V.sub.LEARNED when (e.g., each time that) the processor 242 turns the LED light source 202 off (e.g., fades the LED light source off). The processor 242 may be configured to overwrite the learned load voltage V.sub.LEARNED stored in the memory with the learned load voltage V.sub.LEARNED determined the last time that the processor 242 turned off the LED light source 202. In addition, the processor 242 may be configured to process the learned load voltages V.sub.LEARNED from multiple turn-off events (e.g., calculate the average or median value of the multiple learned load voltages) before overwriting the learned load voltage V.sub.LEARNED stored in the memory.

(46) The processor 242 may be configured to control the LED drive circuit 230 using the learned load voltage V.sub.LEARNED, for example, when turning on the LED light source 202. FIG. 5B shows example waveforms illustrating the operation of the LED driver 200 when the processor 242 is fading on the LED light source 202 (e.g., fading on to a target intensity L.sub.TRGT that corresponds to a target current I.sub.TRGT). In response to receiving a command to turn on the LED light source 202 and/or in response to power being applied to the LED driver 200 to turn on the LED light source, the processor 242 may be configured to pre-charge the output capacitor C236 of the LED drive circuit 230 during a pre-charge period T.sub.PRE-CHARGE prior to attempting to turn on the LED light source 202. During the pre-charge period T.sub.PRE-CHARGE, the processor 242 may be configured to control the duty cycle of the pulse-width modulated signal V.sub.PWM (and thus the DC magnitude of the target-current control signal V.sub.I-TRGT) as a function of the learned load voltage V.sub.LEARNED to cause the output capacitor C236 to charge faster than normal (e.g., faster than if the processor 242 controlled the DC magnitude of the target-current control signal V.sub.I-TRGT in response to the target current I.sub.TRGT as shown in FIG. 3B). The faster rate at which the output capacitor C236 charges during the pre-charge period T.sub.PRE-CHARGE may allow the processor 242 to turn-on the LED light source 202 quickly and consistently, e.g., when fading the LED light source on to the low-end intensity L.sub.LE.

(47) The control circuit 240 may be configured to pre-charge the output capacitor C236 of the LED drive circuit 230 until the magnitude of the load voltage V.sub.LOAD reaches or exceeds a pre-charge voltage threshold V.sub.TH-PC. The pre-charge voltage threshold V.sub.TH-PC may be determined, for example, as a function of the learned load voltage V.sub.LEARNED (e.g., V.sub.TH-PC=.Math.V.sub.LEARNED, where a is a constant that may be, for example, approximately 0.90). Since the magnitude of the load voltage V.sub.LOAD may be greater when the LED light source 202 is cold than when the LED light source 202 is warm, the constant may be sized to be less than one to ensure that the LED drive circuit 230 does not overshoot the learned load voltage V.sub.LEARNED when pre-charging the output capacitor C236. Additionally or alternatively, the pre-charge voltage threshold V.sub.TH-PC may be determined, for example, using a different function of the learned load voltage V.sub.LEARNED (e.g., V.sub.TH-PC=V.sub.LEARNED, where is a constant that may be, for example, approximately one volt). Additionally or alternatively, the pre-charge voltage threshold V.sub.TH-PC may be a fixed threshold (e.g., a predetermined threshold). The processor 242 may be configured to cease pre-charging the output capacitor C236 if the magnitude of the load voltage V.sub.LOAD does not exceed the pre-charge voltage threshold V.sub.TH-PC within a timeout period. The processor 242 may be configured to select the value of the duty cycle of the pulse-width modulated signal V.sub.PWM based on the learned load voltage V.sub.LEARNED such that pre-charge period T.sub.PRE-CHARGE for the LED driver 200 may be approximately the same for different LED light sources that have different resulting load voltages.

(48) The processor 242 may control the start-up control signal V.sub.START-UP to render the controllable switching circuit 258 of the integrator circuit 250 conductive during the pre-charge period T.sub.PRE-CHARGE. After the magnitude of the load voltage V.sub.LOAD reaches or exceeds the pre-charge voltage threshold V.sub.TH-PC, the processor 242 may control the start-up control signal V.sub.START-UP to render the controllable switching circuit 258 of the integrator circuit 250 non-conductive. This may allow the integrator circuit 250 and the latch circuit 260 to control the LED drive circuit 230 using closed loop control in response to the current feedback signal V.sub.I-FB to regulate the magnitude of the load current I.sub.LOAD towards the target current I.sub.TRGT.

(49) FIG. 6 is a simplified flowchart of an example control procedure 600 for controlling a load control device (e.g., the LED driver 200) to control a magnitude of a load current conducted through a lighting load (e.g., the LED light source 202). The control procedure 600 may be executed by a control circuit of the load control device (e.g., the control circuit 240 of the LED driver 200) at step 610, for example, periodically and/or in response to a change in the target current I.sub.TRGT for the lighting load. If the target current I.sub.TRGT is less than the transition current I.sub.TRAN at 612 (e.g., when the target intensity L.sub.TRGT in near the low-end intensity L.sub.LE), the control circuit may maintain the magnitude of the target-current control signal V.sub.I-TRGT constant (e.g., at the minimum voltage V.sub.MIN) at 614, and may adjust the frequency of the frequency control signal V.sub.FREQ in response to the target current I.sub.TRGT (e.g., as shown in FIG. 3A) at 616. The control circuit may then control a filter circuit (e.g., the filter circuit 280) at 618 by controlling the filter control signal V.sub.FILTER to be periodic (e.g., having the same frequency of the frequency control signal V.sub.FREQ) and synchronized to the frequency control signal V.sub.FREQ (e.g., as shown in FIG. 4A). The control procedure 600 may then exit.

(50) If the target current I.sub.TRGT is greater than the transition current I.sub.TRAN (e.g., greater than or equal to the transition current I.sub.TRAN) at 612 (e.g., when the target intensity L.sub.TRGT in near the high-end intensity L.sub.HE), the control circuit may maintain the frequency of the frequency control signal V.sub.FREQ constant (e.g., at the maximum operating frequency f.sub.MAX) at 620, and may adjust the magnitude of the target-current control signal V.sub.I-TRGT in response to the target current I.sub.TRGT (e.g., as shown in FIG. 3B) at 622. The control circuit may then control the filter control signal V.sub.FILTER to be substantially constant at 624, before the control procedure 600 exits. For example, the control circuit may drive the control signal V.sub.FILTER using a maximum duty cycle, such as 100% (e.g., by constantly driving the filter control signal V.sub.FILTER high as shown in FIG. 4B), or a substantially high duty cycle (e.g., 90% or greater) at 624.