Method and device for measuring the frequency of a signal

Abstract

A method includes a) counting whole periods of a signal during a first period of a reference signal, b) repeating step a) for each period of the reference signal until a first duration is equal to a first quantity of periods of the reference signal, and c) determining a first average of the whole periods. The method also includes repeating at least one of steps a) to c) and at each repetition shifting a start of the counting of step a) by at least one period of the reference signal, and in steps b) and c) accounting for whole periods of the signal already counted during the at least one preceding group of steps a) and b). The method includes determining a second average of the first averages, and determining the frequency of the signal from the second average and the frequency of the reference signal.

Claims

1. A method for determining a frequency of a signal using a frequency measurement circuit, the method comprising, using the frequency measurement circuit: a) counting a number of whole periods of the signal during a first period of a periodic reference signal; b) repeating step a) for each period of the periodic reference signal until a first duration is equal to a first quantity of periods of the periodic reference signal; c) determining a first average of the numbers of whole periods; d) repeating at least one of steps a), b) and c) and at each repetition shifting a start of the counting of step a) by at least one period of the periodic reference signal; e) determining a second average of the first averages; and f) determining the frequency of the signal from the second average and the frequency of the periodic reference signal by multiplying the second average times the frequency of the periodic reference signal.

2. The method of claim 1, wherein repeating at least one of steps a), b) and c) comprises repeating steps a), b) and c) in parallel.

3. The method of claim 1, wherein steps a) to e) are implemented by applying the following formula: $M2=\frac{1}{R}*\left(\underset{k=1}{\overset{R}{.Math.}}\frac{1}{S}\underset{i=k}{\overset{k+S-1}{.Math.}}{C}_i\right)$ wherein M2 designates the second average, S corresponds to the first quantity of periods, R corresponds to a number of repetitions of steps during step d), and C.sub.i corresponds to the number of whole periods of the signal counted during a current period of the periodic reference signal.

4. The method of claim 1, wherein the repetitions of steps a), b) and c) is equal to a second quantity of periods of the periodic reference signal reduced by the first quantity of periods.

5. The method of claim 4, wherein the first quantity and the second quantity of periods are powers of two.

6. The method of claim 5, wherein the first quantity of periods is equal to half the second quantity of periods.

7. The method of claim 6, wherein steps a) to e) are implemented by applying the following formula: $M2=\frac{1}{P-S}*\frac{1}{S}*\left(\underset{i=1}{\overset{S}{.Math.}}i*C_i+\underset{i=S+1}{\overset{P-1}{.Math.}}\left(P-i\right)*C_i\right)$ wherein M2 designates the second average, S corresponds to the first quantity of periods, P corresponds to the second quantity of periods and C.sub.i corresponds to the number of whole periods of the signal counted during a current period of the periodic reference signal.

8. The method of claim 5, wherein the first quantity of periods is less than half the second quantity of periods.

9. The method of claim 8, wherein steps a) to e) are implemented by applying the following formula: $M2=\frac{1}{P-S}*\frac{1}{S}*\left(\underset{i=1}{\overset{S}{.Math.}}i*C_i+\underset{i=S+1}{\overset{P-S}{.Math.}}S*C_i+\underset{i=P-S+1}{\overset{P-1}{.Math.}}\left(P-i\right)*C_i\right)$ wherein M2 designates the second average, S corresponds to the first quantity of periods, P corresponds to the second quantity of periods and C.sub.i corresponds to the number of whole periods of the signal counted during a current period of the periodic reference signal.

10. The method of claim 1, wherein in steps b) and c) accounting for the numbers of whole periods of the signal already counted during the at least one preceding group of steps a) and b).

11. The method of claim 1, wherein determining the second average comprises performing a bit shift on an accumulator value.

12. The method of claim 1, wherein counting the number of whole periods comprises using a counter, the method further comprising, during step b), resetting the counter after each period of the periodic reference signal.

13. A method for determining a frequency of a signal using a frequency measurement circuit, the method comprising: receiving the signal with a first input; receiving a periodic reference signal with a second input; counting, with a counter of the frequency measurement circuit, a number of whole periods of the signal to generate a period count during each period of the periodic reference signal for P 1 periods, wherein P is a positive integer; resetting the counter after each period of the periodic reference signal; incrementing by 1 a setpoint counter of the frequency measurement circuit after each period of the periodic reference signal until the setpoint counter reaches S, wherein S is a positive integer lower than P; multiplying each period count with an output of the setpoint counter to generate respective counter values; accumulating, with an accumulator of the frequency measurement circuit, the respective counter values; and generating an average value by dividing the accumulated counter value by (P-S)*S, wherein the frequency of the signal is based on the average value.

14. The method of claim 13, further comprising decrementing by 1 the setpoint counter a period after the setpoint counter reaches S.

15. The method of claim 13, further comprising keeping the output of the setpoint counter at S for more than 1 period of the periodic reference signal.

16. The method of claim 13, wherein S and P are powers of 2.

17. The method of claim 13, wherein S is half of P.

18. The method of claim 13, further comprising dividing the accumulated counter value by (P-S)*S by performing a shift operation on a register of the accumulator.

19. The method of claim 13, wherein the first input is coupled to an output of a voltage controlled oscillator (VCO) of a phased-locked loop (PLL) and the second input is coupled to a reference input of the PLL.

20. The method of claim 1, further comprising: receiving the signal from a voltage controlled oscillator (VCO) of a phased-locked loop (PLL); and receiving the periodic reference signal from the PLL.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantages and features of the invention will appear on examination of the detailed description of implementations and embodiments of the invention, in no way restrictive, and the attached drawings in which:

(2) FIG. 1 is a graph of a frequency of a signal SIG and a periodic reference signal REF in accordance with the invention;

(3) FIG. 2 is a schematic diagram of a device to determine the frequency of the signal of FIG. 1 from a periodic reference signal;

(4) FIG. 3 is a graph of a setpoint counter of FIG. 2 being incremented and decremented in accordance with the invention;

(5) FIG. 4 is a graph of the frequency of the signal SIG and the periodic reference signal REF in accordance with an embodiment of the invention;

(6) FIG. 5 is a schematic diagram of a device to determine the frequency of the signal of FIG. 4 from a periodic reference signal in accordance with an embodiment of the invention; and

(7) FIG. 6 illustrates a graph of the setpoint counter of FIG. 5 being incremented and decremented in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(8) FIG. 1 illustrates an example of a method for determining a frequency of a periodic signal SIG, from a periodic reference signal REF.

(9) The reference signal REF may be, for example, but not restrictively a reference signal of a phase-locked loop, and the signal SIG may be, for example, but not restrictively the signal delivered by a voltage-controlled oscillator forming part of this same phase-locked loop.

(10) In the rest of the description, the index i will be used to represent the various elements associated with a period Pi of the reference signal. Thus, an index 1 is associated with the period P1, an index 2 with the period P2, etc.

(11) In a first step a) of the method a count is performed of a number Ci of whole periods of the first signal SIG during a first reference period P1 of the reference signal REF.

(12) The count a) is repeated (step b)) for each other successive period Pi of the reference signal REF, during a first quantity S of reference periods Pi.

(13) In this example S=4. Thus successive counts are performed of the numbers C1, C2, C3 and C4 of whole periods of the first signal SIG taking place during the successive periods P1, P2, P3 and P4.

(14) Then (step c)) a first average M11 is determined of the different numbers Ci counted during the four repetitions of the first step a). In this example, the first average M11 will be equal to the sum of the numbers C1, C2, C3 and C4, divided by the first quantity S=4.

(15) Steps a) to c) are repeated a quantity of times equal to the difference between a second quantity P of reference periods and the first quantity S=4, by shifting the start of the counting of a reference period Pi at each repetition.

(16) In this example P=8. Thus PS=4 first averages M11, M12, M13 and M14 are determined in parallel each relating to 4 successive numbers Ci.

(17) M11 is thus the average of the numbers C1 to C4, M12 the average of the numbers C2 to C5, M13 the average of the numbers C3 to C6, and M14 the average of the numbers C4 to C7.

(18) Finally, a second average M2 is determined on the values of the first averages M11, M12, M13, and M14.

(19) Here, the value of the second average M2 is thus equal to the sum of the first averages M11, M12, M13 and M14, divided by PS=4.

(20) In order to obtain the frequency of the first signal, the frequency of the reference signal is then multiplied by the value of the second average M2.

(21) The method thus implemented is equivalent to applying the following first formula F1:

(22) $\begin{array}{cc}M2=\frac{1}{P-S}*\left(\underset{k=1}{\overset{P-S}{.Math.}}\frac{1}{S}\underset{i=k}{\overset{k+S-1}{.Math.}}{C}_i\right)& \left(\mathrm{F1}\right)\end{array}$
This formula could be implemented in a software form e.g. within a microcontroller.

(23) However, the inventors have observed that by selecting the first quantity S and the second quantity P as powers of two and particularly by selecting

(24) $S=\frac{P}{2},$
the method is equivalent to applying the following second formula F2:

(25) 0$\begin{array}{cc}M2=\frac{1}{P-S}*\frac{1}{S}*\left(\underset{i=1}{\overset{S}{.Math.}}i*C_i+\underset{i=S+1}{\overset{P-1}{.Math.}}\left(P-i\right)*C_i\right)& \left(\mathrm{F2}\right)\end{array}$

(26) This formula is particularly advantageous since it can be used to apply the formula not only with software means, but also with simple hardware means such as those of the device DIS1 illustrated in FIG. 2.

(27) It is then also possible not to repeat the counting of certain numbers Ci at each repetition and to keep these numbers Ci for subsequently weighting them.

(28) The device DIS1 in FIG. 2 here includes a counting means 1, receiving as input the reference signal REF and the first signal SIG. The counting means 1 is configured for counting each number Ci of whole periods of the first signal SIG taking place during each reference period Pi.

(29) In this example, the counting means 1 includes a counter 11 clocked by the signal REF associated with a decoder 12.

(30) The counter 11 is configured for being incremented at each period of the signal SIG, and the decoder 12 is configured for resetting the counter 11 to zero at each reference period Pi.

(31) The device DIS1 also includes a setpoint counter 2a configured for delivering a counter value Vi at each reference period Pi of the reference signal.

(32) As illustrated in FIG. 3, the counter 2a is in this example configured, during the P1=7 reference periods P1 to P7, for being incremented by one at each new reference period Pi up to the first quantity S=4 then being decremented by one at each new reference period Pi.

(33) Thus, the value Vi of the setpoint counter will be successively equal to 1, 2, 3, 4, 3, 2, 1 respectively during the reference periods P1, P2, P3, P4, P5, P6, P7.

(34) The outputs of the counting means 1 and the setpoint counter 2a are both connected to a multiplier 3 (FIG. 2). Thus, each successive number Ci is multiplied by the associated counter value Vi.

(35) An accumulator 4 comprises an asynchronous adder 40 and a register 41 for synchronizing the sums to be performed. A first input of the adder is connected at the output of the multiplier 3 so as to receive each number Ci multiplied by its associated counter value Vi. The output of the register 41 is looped back onto a second input of the adder. Initially, the accumulator 4 contains a zero value.

(36) At each reference period Pi, the accumulator stores the output value of the multiplier and adds it together with the previously stored value. The sum of the stored values is returned on the second input of the adder 40 and synchronized by the register 41.

(37) The sum finally stored is therefore equal to
C.sub.1+2*C.sub.2+3*C.sub.1+4*C.sub.4+3*C.sub.5+2*C.sub.6+C.sub.7

(38) The device further includes a shifting means 6, e.g. a software module, configured for performing a bit shift on the binary value of the stored sum and delivering the second average M2.

(39) In this example, the bit shift corresponds to a division by the product (PS)*S=16, i.e. a 4-bit right shift.

(40) It should be noted that the division thus performed by a bit shift is possible thanks to the selection of powers of 2 for the first quantity S and the second quantity P.

(41) Thus it is possible, for a 16 MHZ reference signal, to obtain an accuracy of 62.5 kHz in a number of periods of the reference signal equal to 32, while 256 periods of the reference signal would have been required with a conventional counter.

(42) According to another implementation illustrated in FIGS. 4 to 6, S is selected less than

(43) $\frac{P}{2},$
e.g. S=2 and P=8.

(44) Thus successive counts are performed of the numbers Ci of whole periods of the signal SIG taking place during two successive periods Pi.

(45) Then the average M11 is determined of the two numbers C1 and C2 counted during the two reference periods P1 and P2.

(46) This step of the method is repeated a quantity of times equal to PS=6, by shifting the start of the counting of a reference period Pi at each repetition.

(47) Thus 6 averages M11, M12, M13, M14, M15 and M16 are determined in parallel, each relating to 2 successive numbers Ci.

(48) Finally, a second average M2 is determined on the values of the first averages M11, M12, M13, M14, M15 and M16.

(49) The inventors have noticed that by selecting

(50) $S<\frac{P}{2},$
with P and S as powers of two, the above formula F1 is equivalent to the following formula F3:

(51) $\begin{array}{cc}M2=\frac{1}{P-S}*\frac{1}{S}*\left(\underset{i=1}{\overset{S}{.Math.}}i*C_i+\underset{i=S+1}{\overset{P-S}{.Math.}}S*C_i+\underset{i=P-S+1}{\overset{P-1}{.Math.}}\left(P-i\right)*C_i\right)& \left(\mathrm{F3}\right)\end{array}$

(52) This formula can be used to apply this method with software means, but also again with simple hardware means such as the device DIS2 illustrated in FIG. 5 while avoiding repetitive counts of certain numbers Ci.

(53) This device DIS2 is similar to the device DIS1 illustrated in FIG. 2 and described previously, but differs in that it includes a setpoint counter 2b configured differently.

(54) FIG. 6 illustrates a possible operation of the setpoint counter 2b in the case where P=8 and S=2.

(55) Here the counter is configured for being incremented at the second reference period P2, then during five reference periods P2 to P6 for being kept at a value equal to two, and then for being decremented once during the reference period P7.

(56) Thus, the sum finally stored by the accumulator is therefore
C.sub.1+2*C.sub.2+2*C.sub.1+2*C.sub.4+2*C.sub.5+2*C.sub.6+C.sub.7

(57) In this embodiment also, the division again comprises a bit shift on the accumulator value, and this is possible thanks to the selection of powers of two for the first quantity S and the second quantity P.

(58) Although implementations and embodiments of the invention have been described here in which the second quantity P is 8 and the first quantity S is 2 or 4, the invention is compatible with any other first quantity and any other second quantity, whether or not these two quantities are powers of two, so long as S is less than P. The fact that S and P are powers of two enables a particularly compact integrated embodiment to be obtained and the division by S (PS) to be performed by a simple bit shift.