Switching regulator using protection circuit for avoiding voltage stress and associated power management integrated circuit

Abstract

A switching regulator includes a first switch circuit, a second switch circuit, and a protection circuit. The first switch circuit has a first connection node coupled to a first reference voltage, and a second connection node coupled to one end of an inductor. The second switch circuit has a first connection node coupled to a second reference voltage, and a second connection node coupled to the one end of the inductor. The protection circuit senses a voltage level at the first connection node of the first switch circuit, and selectively enables an auxiliary current path in response to the voltage level at the first connection node of the first switch circuit, wherein the auxiliary current path and at least the first switch circuit are arranged in a parallel connection fashion.

Claims

1. A switching regulator comprising: a first switch circuit, having a first connection node coupled to a first reference voltage, and a second connection node coupled to one end of an inductor; a second switch circuit, having a first connection node coupled to a second reference voltage that is different from the first reference voltage, and a second connection node coupled to said one end of the inductor; and a protection circuit, arranged to sense a voltage level at the first connection node of the first switch circuit, and selectively enable an auxiliary current path in response to the voltage level at the first connection node of the first switch circuit, wherein the auxiliary current path and at least the first switch circuit are arranged in a parallel connection fashion; wherein the protection circuit disables the auxiliary current path in response to a difference between an auxiliary reference voltage and the voltage level at the first connection node of the first switch circuit, during a period in which the first switch circuit is switched on.

2. The switching regulator of claim 1, wherein the first reference voltage is a supply voltage, and the second reference voltage is a ground voltage.

3. The switching regulator of claim 1, wherein the first reference voltage is a ground voltage, and the second reference voltage is a supply voltage.

4. The switching regulator of claim 1, wherein the protection circuit is further arranged to receive the auxiliary reference voltage, and automatically enables the auxiliary current path according to the difference between the auxiliary reference voltage and the voltage level at the first connection node of the first switch circuit.

5. The switching regulator of claim 4, wherein the switching regulator is implemented in a chip, the protection circuit receives the auxiliary reference voltage via one pin of the chip, and the first switch circuit receives the first reference voltage via another pin of the chip.

6. The switching regulator of claim 5, wherein a noise level of the auxiliary reference voltage is lower than a noise level of the first reference voltage.

7. The switching regulator of claim 4, wherein the protection circuit comprises: an auxiliary transistor, having a control node arranged to receive the auxiliary reference voltage, a first connection node coupled to the first connection node of the first switch circuit, and a second connection node coupled to said one end of the inductor.

8. The switching regulator of claim 7, wherein a voltage level at the control node of the auxiliary transistor is constant.

9. The switching regulator of claim 7, wherein the protection circuit further comprises: a resistor—capacitor (RC) circuit, having a resistor and a capacitor, wherein a first end of the resistor is coupled to the auxiliary reference voltage, a second end of the resistor is coupled to the control node of the auxiliary transistor, a first end of the capacitor is coupled to the control node of the auxiliary transistor, and a second end of the capacitor is coupled to said one end of the inductor.

10. The switching regulator of claim 4, wherein the protection circuit comprises: an auxiliary transistor, having a control node arranged to receive the auxiliary reference voltage, a first connection node coupled to the first connection node of the first switch circuit, and a second connection node coupled to the second reference voltage.

11. A power management integrated circuit (PMIC) comprising: a first pin, arranged to receive a first reference voltage; a second pin, arranged to receive a second reference voltage that is different from the first reference voltage; a third pin, arranged to output a pulsed voltage; and a switching regulator, arranged to generate the pulsed voltage, wherein the switching regulator comprises: a first switch circuit, having a first connection node coupled to the first pin, and a second connection node coupled to the third pin; a second switch circuit, having a first connection node coupled to the second pin, and a second connection node coupled to the third pin; and a protection circuit, arranged to sense a voltage level at the first connection node of the first switch circuit, and selectively enable an auxiliary current path in response to the voltage level at the first connection node of the first switch circuit, wherein the auxiliary current path and at least the first switch circuit are arranged in a parallel connection fashion; wherein the protection circuit disables the auxiliary current path in response to a difference between an auxiliary reference voltage and the voltage level at the first connection node of the first switch circuit, during a period in which the first switch circuit is switched on.

12. The PMIC of claim 11, wherein the first reference voltage is a supply voltage, and the second reference voltage is a ground voltage.

13. The PMIC of claim 11, wherein the first reference voltage is a ground voltage, and the second reference voltage is a supply voltage.

14. The PMIC of claim 11, further comprising: a fourth pin, arranged to receive the auxiliary reference voltage; wherein the protection circuit is further coupled to the fourth pin, and automatically enables the auxiliary current path according to the difference between the auxiliary reference voltage and the voltage level at the first connection node of the first switch circuit.

15. The PMIC of claim 14, wherein a noise level of the auxiliary reference voltage is lower than a noise level of the first reference voltage.

16. The PMIC of claim 14, wherein the protection circuit comprises: an auxiliary transistor, having a control node coupled to the fourth pin, a first connection node coupled to the first connection node of the first switch circuit, and a second connection node coupled to the third pin.

17. The PMIC of claim 16, wherein a voltage level at the control node of the auxiliary transistor is constant.

18. The PMIC of claim 16, wherein the protection circuit further comprises: a resistor—capacitor (RC) circuit, having a resistor and a capacitor, wherein a first end of the resistor is coupled to the fourth pin, a second end of the resistor is coupled to the control node of the auxiliary transistor, a first end of the capacitor is coupled to the control node of the auxiliary transistor, and a second end of the capacitor is coupled to the third pin.

19. The PMIC of claim 14, wherein the protection circuit comprises: an auxiliary transistor, having a control node coupled to the fourth pin, a first connection node coupled to the first connection node of the first switch circuit, and a second connection node coupled to the third pin.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a diagram illustrating a power management integrated circuit (PMIC) according to an embodiment of the present invention.

(2) FIG. 2 is a circuit diagram illustrating a first switching regulator with high-side safe operating area (SOA) protection according to an embodiment of the present invention.

(3) FIG. 3 is a diagram illustrating waveforms of various voltages and an auxiliary current in the switching regulator shown in FIG. 2 according to an embodiment of the present invention.

(4) FIG. 4 is a diagram illustrating the switching regulator in FIG. 2 that operates during a first period within a voltage regulation cycle.

(5) FIG. 5 is a diagram illustrating the switching regulator in FIG. 2 that operates during a second period within the voltage regulation cycle.

(6) FIG. 6 is a diagram illustrating a second switching regulator with high-side SOA protection according to an embodiment of the present invention.

(7) FIG. 7 is a diagram illustrating a third switching regulator with high-side SOA protection according to an embodiment of the present invention.

(8) FIG. 8 is a diagram illustrating waveforms of various voltages and an auxiliary current in the switching regulator shown in FIG. 7 according to an embodiment of the present invention.

(9) FIG. 9 is a diagram illustrating a fourth switching regulator with high-side SOA protection according to an embodiment of the present invention.

(10) FIG. 10 is a circuit diagram illustrating a first switching regulator with low-side SOA protection according to an embodiment of the present invention.

(11) FIG. 11 is a diagram illustrating the switching regulator in FIG. 10 that operates during a first period within a voltage regulation cycle.

(12) FIG. 12 is a diagram illustrating the switching regulator in FIG. 10 that operates during a second period within the voltage regulation cycle.

(13) FIG. 13 is a diagram illustrating a second switching regulator with low-side SOA protection according to an embodiment of the present invention.

(14) FIG. 14 is a diagram illustrating a third switching regulator with low-side SOA protection according to an embodiment of the present invention.

(15) FIG. 15 is a diagram illustrating a fourth switching regulator with low-side SOA protection according to an embodiment of the present invention.

DETAILED DESCRIPTION

(16) Certain terms are used throughout the following description and claims, which refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

(17) FIG. 1 is a diagram illustrating a power management integrated circuit (PMIC) according to an embodiment of the present invention. The PMIC 100 is a chip that may be used by an electronic device for providing regulated voltages to other components in the same electronic device. In this embodiment, the PMIC 100 is employed by a mobile device such as a cellular phone, a tablet, or a wearable device. Hence, the mobile device is powered by a battery 10. As shown in FIG. 1, the PMIC 100 includes a switching regulator 102, where the switching regulator 102 includes a controller 104 and a power stage 106. The controller 104 is a control circuit that may employ a pulse width modulation (PWM) scheme or other control scheme to control conductance states (i.e., on/off states) of switching elements (e.g., transistors) in the power stage 106. In addition to switching elements (e.g., transistors), the power stage 106 includes the proposed protection circuit 108 to ensure that the switching elements (e.g., transistors) can meet the SOA requirement.

(18) The supply voltage of the controller 104 and the supply voltage of the power stage 106 may be provided separately. Similarly, the ground voltage of the controller 104 and the ground voltage of the power stage 106 may be provided separately. The PMIC 100 has a plurality of pins 112, 114, 116, 118 for receiving a plurality of reference voltages V.sub.AVDD, V.sub.AGND, V.sub.PVDD, V.sub.PGND, respectively. Specifically, the pin 112 is a power pin arranged to receive a supply voltage (e.g., V.sub.AVDD) needed by the controller 104, the pin 114 is a ground pin arranged to receive a ground voltage (e.g., V.sub.AGND) needed by the controller 104, the pin 116 is another power pin arranged to receive a supply voltage (e.g., V.sub.PVDD) needed by the power stage 106, and the pin 118 is another ground pin arranged to receive a ground voltage (e.g., V.sub.PGND) needed by the power stage 106. The supply voltage V.sub.AVDD is provided via circuit components on a first printed circuit board (denoted by “PCB1”) 12, the supply voltage V.sub.PVDD is provided via circuit components on a second printed circuit board (denoted by “PCB2”) 14, the ground voltage V.sub.AGND is provided via circuit components on a third printed circuit board (denoted by “PCB3”) 16, and the ground voltage V.sub.PVDD is provided via circuit components on a fourth printed circuit board (denoted by “PCB4”) 18. The PMIC 100 further includes a pin 120 that is a voltage output pin used to output a pulsed voltage V.sub.LX generated from the power stage 106 to a load circuit. For example, the load circuit may be connected to the pin 120 via an inductor.

(19) The supply voltages V.sub.AVDD and V.sub.PVDD may be designed to have the same steady-state voltage value, and the ground voltages V.sub.AGND and V.sub.PGND may be designed to have the same steady-state voltage value. However, due to inherent characteristics of the controller 104 and the power stage 106, the noise level of the supply voltage V.sub.AVDD is lower than the noise level of the supply voltage V.sub.PVDD/and the noise level of the ground voltage V.sub.AGND is lower than the noise level of the ground voltage V.sub.PGND. In other words, the supply voltage V.sub.AVDD is much cleaner than the supply voltage V.sub.AVDD, and the ground voltage V.sub.AGND is much cleaner than the ground voltage V.sub.PGND. In one exemplary SOA protection design, the protection circuit 108 may use the supply voltage V.sub.AVDD as a reference to monitor the voltage bouncing on the supply voltage at the pin 116. In another exemplary SOA protection design, the protection circuit 108 may use the ground supply voltage V.sub.AGND as a reference to monitor the voltage bouncing on the ground voltage at the pin 118. However, these are for illustrative purposes only, and are not meant to be limitations of the present invention. In practice, any switching regulator design using the proposed SOA protection design falls within the scope of the present invention. For example, the protection circuit 108 may use a higher steady-state reference voltage level to monitor the voltage bouncing on the supply voltage at the pin 116. For another example, the protection circuit 108 may use a lower steady-state reference voltage level to monitor the voltage bouncing on the ground voltage at the pin 118. Further details of the proposed SOA protection design are described with reference to the accompanying drawings.

(20) FIG. 2 is a circuit diagram illustrating a first switching regulator with high-side SOA protection according to an embodiment of the present invention. The switching regulator 102 shown in FIG. 1 may be implemented using the switching regulator 200. For clarity and simplicity, only the circuit components pertinent to the present invention are illustrated in FIG. 2. In practice, the switching regulator 200 may include other circuit components. As shown in FIG. 2, the switching regulator 200 includes a plurality of switch circuits 202, 204 and a protection circuit 206. The switch circuits 202 and 204 act as switching elements of the power stage 106, and the protection circuit 108 of the power stage 106 may be implemented by the protection circuit 206. The switch circuit 202 is a high-side (HS) switch having a first connection node coupled to a first reference voltage (e.g., supply voltage V.sub.PVDD) and a second connection node coupled to one end of an off-chip inductor L, where the supply voltage V.sub.PVDD is received by the switch circuit 202 via the pin 116, and the off-chip inductor L is coupled to the switch circuit 202 via the pin 120. In addition, a conductance state (i.e., on/off state) of the switch circuit 202 is controlled by one switching control signal S1. For example, the switching control signal S1 is generated from the controller 104 shown in FIG. 1.

(21) The switch circuit 204 is a low-side (LS) switch having a first connection node coupled to a second reference voltage (e.g., ground voltage V.sub.PGND) that is different from the first reference voltage (e.g., supply voltage V.sub.PVDD), and a second connection node coupled to one end of the off-chip inductor L, where the ground voltage V.sub.PGND is received by the switch circuit 204 via the pin 118. In addition, a conductance state (i.e., on/off state) of the switch circuit 204 is controlled by another switching control signal S2. For example, the switching control signal S2 is generated from the controller 104 shown in FIG.

(22) The protection circuit 206 is arranged to sense a voltage level V.sub.PVDD,IN at the first connection node of the switch circuit 202, and selectively enable an auxiliary current path 208 in response to the voltage level V.sub.PVDD,IN at the first connection node of the switch circuit 202, wherein the auxiliary current path 208 and the switch circuit 202 are arranged in a parallel connection fashion.

(23) In this embodiment, the switch circuit 202 is implemented by a P-channel metal-oxide-semiconductor (PMOS) transistor M.sub.HS with a source node coupled to the pin 116, a drain node coupled to the pin 120, and a gate node coupled to a controller (e.g., controller 104 shown in FIG. 1); the switch circuit 204 is implemented by an N-channel metal-oxide-semiconductor (NMOS) transistor M.sub.LS with a source node coupled to the pin 118, a drain node coupled to the pin 120, and a gate node coupled to a controller (e.g., controller 104 shown in FIG. 1); and the protection circuit 206 is implemented by an auxiliary transistor that is a PMOS transistor M.sub.AUX with a source node coupled to the pin 116, a drain node coupled to the pin 120, and a gate node coupled to the pin 112.

(24) The parasitic inductors resulting from PCB and semiconductor package are represented by L.sub.HS,par and L.sub.LS,par, and the parasitic capacitors resulting from PCB, semiconductor package and switch circuits 202 and 204 are represented by C.sub.HS,par and C.sub.LS,par.

(25) Please refer to FIG. 2 in conjunction with FIGS. 3-4. FIG. 3 is a diagram illustrating waveforms of various voltages and an auxiliary current in the switching regulator 200 shown in FIG. 2 according to an embodiment of the present invention. FIG. 4 is a diagram illustrating the switching regulator 200 in FIG. 2 that operates during a first period t1-t2 within a voltage regulation cycle. An absolute value of a gate-source voltage of the PMOS transistor M.sub.AUX is denoted by |V.sub.GS,AUX|. An absolute value of a gate-source voltage of the PMOS transistor M.sub.HS is denoted by |V.sub.GS,P|. An absolute value of a gate-source voltage of the NMOS transistor M.sub.LS is denoted by V.sub.GS, N|. An absolute value of a drain-source voltage of the PMOS transistor M.sub.HS denoted by |V.sub.DS,P|.

(26) During the first period t1-t2, the switch circuit 202 (particularly, PMOS transistor M.sub.HS) is switched on, and the switch circuit 204 (particularly, NMOS transistor M.sub.LS) is switched off. Hence, the switching regulator 200 generates one current I.sub.L passing through the parasitic inductor L.sub.HS,par, the switch circuit 202 (particularly, PMOS transistor M.sub.HS), and the inductor L. In this way, the pulsed voltage V.sub.LX has a high voltage level. Since the voltage level V.sub.PVDD,IN at the first connection node of the switch circuit 202 is approximately equal to the supply voltage V.sub.AVDD received by the protection circuit 206, the protection circuit 206 (particularly, PMOS transistor M.sub.AUX) is switched off, meaning that the auxiliary current path 208 is not enabled between the first connection node and the second connection node of the switch circuit 202.

(27) Please refer to FIG. 2 in conjunction with FIG. 3 and FIG. 5. FIG. 5 is a diagram illustrating the switching regulator 200 in FIG. 2 that operates during a second period t2-t3 within the voltage regulation cycle. During the second period t2-t3 immediately following the first period t1-t2, the switching control signal S1 is set for switching off the switch circuit 202 (particularly, PMOS transistor M.sub.HS), and the switching control signal S2 is set for switching on the switch circuit 204 (particularly, NMOS transistor M.sub.LS). Hence, the switching regulator 200 generates the current I.sub.L passing through the parasitic inductor L.sub.LS,par, the switch circuit 204 (particularly, NMOS transistor M.sub.LS), and the inductor L. In this way, the pulsed voltage V.sub.LX has a transition from a high voltage level to a low voltage level. Since the switch circuit 202 (particularly, PMOS transistor M.sub.HS) is controlled to be switched off and the current passing through the parasitic inductor L.sub.HS,par should be continuous, the parasitic inductor L.sub.HS,par still has the current I.sub.HS, par passing there through, thus increasing the voltage level V.sub.PVDD,IN at the first connection node of the switch circuit 202. In a case where the proposed protection circuit 206 is omitted, the voltage level V.sub.PVDD,IN at the first connection node of the switch circuit 202 is boosted significantly, as indicated by the dotted line 302. As illustrated by the dotted line 304, the absolute value of the drain-source voltage of the PMOS transistor M.sub.HS (which is denoted by |V.sub.DS,P|) will exceed the SOA voltage V.sub.SOA, thus resulting in damage of the PMOS transistor M.sub.HS.

(28) To address this issue, the proposed protection circuit 206 is implemented to provide SOA protection. When the current I.sub.HS,par passing through the parasitic inductor L.sub.HS,par, the voltage level V.sub.PVDD,IN at the first connection node of the switch circuit 202 is increased to be higher than the supply voltage V.sub.AVDD acting a gate voltage of the PMOS transistor M.sub.AUX, and the absolute value of the gate-source voltage of the PMOS transistor M.sub.AUX (which is denoted by |V.sub.GS, AUX|) is increased accordingly. Once the absolute value of the gate-source voltage of the PMOS transistor M.sub.AUX (which is denoted by |V.sub.GS,AUX|) exceeds an absolute value of a threshold voltage |V.sub.TH| of the PMOS transistor M.sub.AUX the protection circuit 206 (particularly, PMOS transistor M.sub.AUX) is automatically switched on, thereby enabling the auxiliary current path 208 between the first connection node and the second connection node of the switch circuit 202. In other words, the protection circuit 206 provides another current path for I.sub.HS, par Since a part of the current I.sub.HS, par (which is denoted by I.sub.AUX) passes through the auxiliary current path 208, the voltage bouncing at the first connection node of the switch circuit 202 is mitigated, as illustrated by the solid line 306. In this way, the absolute value of the drain-source voltage of the PMOS transistor M.sub.HS (which is denoted by |V.sub.DS,P) will not exceed the SOA voltage V.sub.SOA, as illustrated by the dotted line 308.

(29) In above embodiment shown in FIG. 2, the protection circuit 206 is implemented by PMOS transistor M.sub.AUX. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. Alternatively, the protection circuit 206 may be implemented by a PNP bipolar transistor or other transistor that can be selectively turned on according to difference between the auxiliary reference voltage (e.g., V.sub.AVDD) and the voltage level V.sub.PVDD,IN at the first connection node of the switch circuit 202.

(30) The proposed protection circuit 206 has a simple design that can automatically enable the auxiliary current path 208 according to a difference between the auxiliary reference voltage (e.g., V.sub.AVDD) and the voltage level V.sub.PVDD,IN at the first connection node of the switch circuit 202. In addition, there is no need to decrease the slew rate of the PMOS transistor M.sub.HS for SOA protection, such that the power efficiency of the switching regulator 200 can be maintained under a condition that the PMOS transistor M.sub.HS meets the SOA requirement.

(31) The maximum value of the current I.sub.HS,par depends on the maximum value of the current I.sub.L required by a load circuit, and also depends on parasitic inductors, capacitors, and resistors resulting from PCB and semiconductor package. Since the proposed protection circuit 206 can ensure that the PMOS transistor M.sub.HS meets the SOA requirement, there is no need to limit the maximum current capability for SOA protection and/or to apply limitations to design rules of PCB and semiconductor package for SOA protection.

(32) With regard to the embodiment shown in FIG. 2, the protection circuit 206 is arranged to selectively enable the auxiliary current path 208 coupled between the first connection node of the switch circuit 202 and one end of the inductor L. Since the pulsed voltage V.sub.LX is an output of the switching regulator 200 and provided to the inductor L via the pin 120, the power on the parasitic inductor L.sub.HS,par can be recycled to the output of the switching regulator 200 through the auxiliary current path 208. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. The same objective of providing SOA protection for the switch circuit 202 (particularly, PMOS transistor M.sub.HS) can be achieved by enabling the auxiliary current path 208 coupled between the first connection node of the switch circuit 202 (particularly, PMOS transistor M.sub.HS) and one reference voltage (e.g., ground voltage V.sub.PGND).

(33) FIG. 6 is a diagram illustrating a second switching regulator with high-side SOA protection according to an embodiment of the present invention. The major difference between the switching regulators 200 and 600 is that the switching regulator 600 has a protection circuit 606 implemented by an auxiliary transistor that is a PMOS transistor M′.sub.AUX with a source node coupled to the pin 116, a drain node coupled to the pin 118, and a gate node coupled to the pin 112. Hence, when an auxiliary current path 608 is enabled, the power on the parasitic inductor L.sub.HS,par is not recycled to the output of the switching regulator 600. Alternatively, the protection circuit 606 may be implemented by a PNP bipolar transistor or other transistor that can be selectively turned on according to difference between the auxiliary reference voltage (e.g., V.sub.AVDD) and the voltage level V.sub.PVDD,IN at the first connection node of the switch circuit 202.

(34) FIG. 7 is a diagram illustrating a third switching regulator with high-side SOA protection according to an embodiment of the present invention. The major difference between the switching regulators 200 and 700 is that the switching regulator 700 has a protection circuit 706 including a resistor-capacitor (RC) circuit 707 and the aforementioned auxiliary transistor (e.g., PMOS transistor M.sub.AUX). The RC circuit 707 includes a resistor R and a capacitor C. A first end of the resistor R is coupled to the auxiliary reference voltage (e.g., supply voltage V.sub.AVDD), and a second end of the resistor R is coupled to the control node of the auxiliary transistor (e.g., PMOS transistor M.sub.AUX). A first end of the capacitor C is coupled to the control node of the auxiliary transistor (e.g., PMOS transistor M.sub.AUX), and a second end of the capacitor C is coupled to one end of the inductor L. As shown in FIG. 3 and FIG. 5, the switching control signal S1 is set for switching off the switch circuit 202 (particularly, PMOS transistor M.sub.HS) and the switching control signal S2 is set for switching on the switch circuit 204 (particularly, NMOS transistor M.sub.LS) during the second period t2-t3. Hence, the pulsed voltage V.sub.LX has a transition from a high voltage level to a low voltage level. Since the pulsed voltage V.sub.Lx is coupled to the control node of the auxiliary transistor (e.g., PMOS transistor M.sub.AUX) through the RC circuit 707, the voltage level V.sub.AVDD,RC at the control node of the auxiliary transistor (e.g., PMOS transistor M.sub.AUX) is temporarily pulled low due to the pulsed voltage V.sub.LX. After the voltage level V.sub.AVDD,RC is temporarily pulled low by the pulsed voltage V.sub.LX, it will be pulled high by the auxiliary reference voltage (e.g., supply voltage V.sub.AVDD).

(35) Alternatively, the auxiliary transistor (e.g., PMOS transistor M.sub.AUX) in the protection circuit 706 may be implemented by a PNP bipolar transistor or other transistor that can be selectively turned on according to difference between the voltage level V.sub.AVDD,RC at the control node of the auxiliary transistor and the voltage level V.sub.PVDD,IN at the first connection node of the switch circuit 202.

(36) Please refer to FIG. 7 in conjunction with FIG. 8. FIG. 8 is a diagram illustrating waveforms of various voltages and an auxiliary current in the switching regulator 700 shown in FIG. 7 according to an embodiment of the present invention. When the voltage level V.sub.AVDD, RC is temporarily pulled low by the pulsed voltage V.sub.Lx, the gate-source voltage of the PMOS transistor M.sub.AUX is increased, thus allowing higher current density on the auxiliary current path 208. Hence, the current I.sub.AUX passing through the auxiliary current path 208 is increased, thus resulting in a lower voltage increment of the voltage level V.sub.PVDD,IN at the first connection node of the switch circuit 202, as indicated by a dotted line 806. In this way, the voltage bouncing at the first connection node of the switch circuit 202 is mitigated due to a smaller absolute value of the drain-source voltage of the PMOS transistor M.sub.HS, as illustrated by the dotted line 808. Compared to the design of the protection circuit 206, the design of the protection circuit 706 can provide better SOA protection for the switch circuit 202 (particularly, PMOS transistor M.sub.HS).

(37) FIG. 9 is a diagram illustrating a fourth switching regulator with high-side SOA protection according to an embodiment of the present invention. The major difference between the switching regulators 600 and 900 is that the switching regulator 900 has a protection circuit 906 including a resistor-capacitor (RC) circuit 907 and the aforementioned auxiliary transistor (e.g., PMOS transistor M′.sub.AUX) The RC circuit 907 includes a resistor R′ and a capacitor C′. A first end of the resistor R′ is coupled to the auxiliary reference voltage (e.g., supply voltage V.sub.AVDD), and a second end of the resistor R′ is coupled to the control node of the auxiliary transistor (e.g., PMOS transistor M′.sub.AUX). A first end of the capacitor C′ is coupled to the control node of the auxiliary transistor (e.g., PMOS transistor, M′.sub.AUX) and a second end of the capacitor C′ is coupled to one reference voltage (e.g., ground voltage V.sub.PGND). As a skilled person in the art can readily understand the principle of the protection circuit 906 after reading above paragraphs directed to the protection circuit 706, further description is omitted here for brevity.

(38) Alternatively, the auxiliary transistor (e.g., PMOS transistor M′.sub.AUX) in the protection circuit 906 may be implemented by a PNP bipolar transistor or other transistor that can be selectively turned on according to difference between the voltage level V.sub.AVDD, RC at the control node of the auxiliary transistor and the voltage level V.sub.PVDD, IN at the first connection node of the switch circuit 202.

(39) With regard to the embodiments shown in FIG. 2, FIG. 6, FIG. 7, and FIG. 9, each of the proposed protection circuits 206, 606, 706, and 906 is designed to apply SOA protection to the high-side switch circuit 202. However, these are for illustrative purposes only, and are not meant to be limitations of the present invention. The same SOA protection design can be employed for applying SOA protection to the low-side switch circuit 204.

(40) FIG. 10 is a circuit diagram illustrating a first switching regulator with low-side SOA protection according to an embodiment of the present invention. The switching regulator 102 shown in FIG. 1 may be implemented using the switching regulator 1000. The major difference between the switching regulators 200 and 1000 is that the switching regulator 1000 includes a protection circuit 1006 arranged to sense a voltage level V.sub.PGND,IN at the first connection node of the switch circuit 204 and selectively enable an auxiliary current path 1008 in response to the voltage level V.sub.PGND,IN at the first connection node of the switch circuit 204, wherein the auxiliary current path 1008 and the switch circuit 204 are arranged in a parallel connection fashion. In this embodiment, the protection circuit 1006 is implemented by an auxiliary transistor that is an NMOS transistor MN.sub.AUX with a source node coupled to the pin 118, a drain node coupled to the pin 120, and a gate node coupled to the pin 114.

(41) Please refer to FIG. 10 in conjunction with FIG. 11. FIG. 11 is a diagram illustrating the switching regulator 1000 in FIG. 10 that operates during a first period within a voltage regulation cycle. During the first period within the voltage regulation cycle, the switch circuit 204 (particularly, NMOS transistor M.sub.LS) is switched on, and the switch circuit 202 (particularly, PMOS transistor M.sub.HS) is switched off. Hence, the switching regulator 1000 generates one current I.sub.L passing through the inductor L, the switch circuit 204 (particularly, NMOS transistor M.sub.LS), and the parasitic inductor L.sub.LS,par. In this way, the pulsed voltage V.sub.LX has a low voltage level. Since the voltage level V.sub.PGND,IN at the first connection node of the switch circuit 204 is approximately equal to the ground voltage V.sub.AGND received by the protection circuit 1006, the protection circuit 1006 (particularly, NMOS transistor MN.sub.AUX) is switched off, meaning that the auxiliary current path 1008 is not enabled between the first connection node and the second connection node of the switch circuit 204.

(42) Please refer to FIG. 10 in conjunction with FIG. 12. FIG. 12 is a diagram illustrating the switching regulator 1000 in FIG. 10 that operates during a second period within the voltage regulation cycle. During the second period immediately following the first period, the switching control signal S2 is set for switching off the switch circuit 204 (particularly, NMOS transistor M.sub.LS), and the switching control signal S1 is set for switching on the switch circuit 202 (particularly, PMOS transistor M.sub.HS). Hence, the switching regulator 1000 generates the current I.sub.L passing through the inductor L, the switch circuit 202 (particularly, PMOS transistor M.sub.HS), and the parasitic inductor L.sub.HS, par. In this way, the pulsed voltage V.sub.LX has a transition from a low voltage level to a high voltage level. Since the switch circuit 204 (particularly, NMOS transistor M.sub.LS) is controlled to be switched off and the current passing through the parasitic inductor L.sub.LS,par should be continuous, the parasitic inductor L.sub.LS,par still has the current I.sub.LS, par passing there through, thus decreasing the voltage level V.sub.PGND,IN at the first connection node of the switch circuit 204. Ina case where the proposed protection circuit 1006 is omitted, the voltage level V.sub.PGND,IN at the first connection node of the switch circuit 204 is pulled low significantly. As a result, the absolute value of the drain-source voltage of the NMOS transistor M.sub.LS will exceed the SOA voltage, thus resulting in damage of the NMOS transistor M.sub.LS.

(43) To address this issue, the proposed protection circuit 1006 is implemented to provide SOA protection. When the current I.sub.LS,par passing through the parasitic inductor L.sub.LS,par, the voltage level V.sub.PGND,IN at the first connection node of the switch circuit 204 is decreased to be lower than the ground voltage V.sub.AGND acting a gate voltage of the NMOS transistor MN.sub.AUX, and the absolute value of the gate-source voltage of the NMOS transistor MN.sub.AUX is increased accordingly. Once the absolute value of the gate-source voltage of the NMOS transistor MN.sub.AUX exceeds an absolute value of a threshold voltage |V.sub.TH| of the NMOS transistor MN.sub.AUX, the protection circuit 1006 (particularly, NMOS transistor MN.sub.AUX) is automatically switched on, thereby enabling the auxiliary current path 1008 between the first connection node and the second connection node of the switch circuit 204. In other words, the protection circuit 1006 provides another current path for I.sub.LS,par. Since the auxiliary current I.sub.AUX (which is apart of the current I.sub.LS,par) passes through the auxiliary current path 1008, the voltage bouncing at the first connection node of the switch circuit 204 is mitigated. In this way, the absolute value of the drain-source voltage of the NMOS transistor M.sub.LS will not exceed the SOA voltage.

(44) In above embodiment shown in FIG. 10, the protection circuit 1006 is implemented by NMOS transistor MN.sub.AUX. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. Alternatively, the protection circuit 1006 may be implemented by an NPN bipolar transistor or other transistor that can be selectively turned on according to difference between the auxiliary reference voltage (e.g., V.sub.AGND) and the voltage level V.sub.PGND,IN at the first connection node of the switch circuit 204.

(45) FIG. 13 is a diagram illustrating a second switching regulator with low-side SOA protection according to an embodiment of the present invention. The major difference between the switching regulators 1000 and 1300 is that the switching regulator 1300 has a protection circuit 1306 implemented by an auxiliary transistor that is an NMOS transistor MN′.sub.AUX with a source node coupled to the pin 118, a drain node coupled to the pin 116, and a gate node coupled to the pin 114. Hence, when an auxiliary current path 1308 is enabled, the power on the parasitic inductor L.sub.LS,par is not recycled to the output of the switching regulator 1300. Alternatively, the protection circuit 1306 may be implemented by an NPN bipolar transistor or other transistor that can be selectively turned on according to difference between the auxiliary reference voltage (e.g., V.sub.AGND) and the voltage level V.sub.PGND,IN at the first connection node of the switch circuit 204.

(46) FIG. 14 is a diagram illustrating a third switching regulator with low-side SOA protection according to an embodiment of the present invention. The major difference between the switching regulators 1000 and 1400 is that the switching regulator 1400 has a protection circuit 1406 including a resistor-capacitor (RC) circuit 1407 and the aforementioned auxiliary transistor (e.g., NMOS transistor MN.sub.AUX). The RC circuit 1407 includes a resistor R and a capacitor C. A first end of the resistor R is coupled to the auxiliary reference voltage (e.g., ground voltage V.sub.AGND), and a second end of the resistor R is coupled to the control node of the auxiliary transistor (e.g., NMOS transistor MN.sub.AUX). A first end of the capacitor C is coupled to the control node of the auxiliary transistor (e.g., NMOS transistor MN.sub.AUX), and a second end of the capacitor C is coupled to one end of the inductor L. Alternatively, the auxiliary transistor (e.g., NMOS transistor MN.sub.AUX) in the protection circuit 1406 may be implemented by an NPN bipolar transistor or other transistor that can be selectively turned on according to difference between the voltage level V.sub.AGND,RC at the control node of the auxiliary transistor and the voltage level V.sub.PGND,IN at the first connection node of the switch circuit 204.

(47) During the second period of the voltage regulation cycle, the switching control signal S2 is set for switching off the switch circuit 204 (particularly, NMOS transistor M.sub.LS) and the switching control signal S1 is set for switching on the switch circuit 202 (particularly, PMOS transistor M.sub.HS). Hence, the pulsed voltage V.sub.Lx has a transition from a low voltage level to a high voltage level. Since the pulsed voltage V.sub.Lx is coupled to the control node of the auxiliary transistor (e.g., NMOS transistor Mn.sub.AUX) through the RC circuit 1407, the voltage level V.sub.AGND,RC at the control node of the auxiliary transistor (e.g., NMOS transistor MN.sub.AUX) is temporarily pulled high due to the pulsed voltage V.sub.LX. After the voltage level V.sub.AGND,RC is temporarily pulled high by the pulsed voltage V.sub.Lx, it will be pulled low by the auxiliary reference voltage (e.g., ground voltage V.sub.AGND).

(48) When the voltage level V.sub.AGND,RC is temporarily pulled high by the pulsed voltage V.sub.LX, the gate-source voltage of the NMOS transistor MN.sub.AUX is increased for allowing higher current density on the auxiliary current path 1008. Hence, the current passing through the auxiliary current path 1008 is increased, resulting in a lower voltage decrement of the voltage level V.sub.PGND,IN at the first connection node of the switch circuit 204. In this way, the voltage bouncing at the first connection node of the switch circuit 204 is mitigated due to a smaller absolute value of the drain-source voltage of the NMOS transistor M.sub.LS. Compared to the design of the protection circuit 1006, the design of the protection circuit 1406 can provide better SOA protection for the switch circuit 204 (particularly, NMOS transistor M.sub.LS).

(49) FIG. 15 is a diagram illustrating a fourth switching regulator with low-side SOA protection according to an embodiment of the present invention. The major difference between the switching regulators 1300 and 1500 is that the switching regulator 1500 has a protection circuit 1506 including a resistor-capacitor (RC) circuit 1507 and the aforementioned auxiliary transistor (e.g., NMOS transistor M′.sub.AUX). The RC circuit 1507 includes a resistor R′ and a capacitor C′. A first end of the resistor R′ is coupled to the auxiliary reference voltage (e.g., ground voltage V.sub.AGND), and a second end of the resistor R′ is coupled to the control node of the auxiliary transistor (e.g., NMOS transistor MN′.sub.AUX). A first end of the capacitor C′ is coupled to the control node of the auxiliary transistor (e.g., NMOS transistor MN′.sub.AUX), and a second end of the capacitor C′ is coupled to one reference voltage (e.g., supply voltage P.sub.PVDD) Alternatively, the auxiliary transistor (e.g., NMOS transistor MN′.sub.AUX) in the protection circuit 1506 may be implemented by an NPN bipolar transistor or other transistor that can be selectively turned on according to difference between the voltage level V.sub.AGND,RC at the control node of the auxiliary transistor and the voltage level V.sub.PGND,IN at the first connection node of the switch circuit 204. As a skilled person in the art can readily understand the principle of the protection circuit 1506 after reading above paragraphs directed to the protection circuit 1406, further description is omitted here for brevity.

(50) In above embodiments, switch circuits 202 and 204 may be implemented by MOS transistors. However, these are for illustrative purposes only, and are not meant to be limitations of the present invention. Alternatively, at least one of the switch circuits 202 and 204 may be implemented by a diode or a schottky diode. To put it simply, the present invention has no limitations on the implementation of switch circuits 202 and 204. Hence, each of the switch circuits 202 and 204 may be implemented by any circuit element with a switchable conductance state. These alternative designs all fall within the scope of the present invention.

(51) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.