Multi-layer circuit board and electronic assembly having same
10820408 ยท 2020-10-27
Assignee
Inventors
Cpc classification
H05K5/0082
ELECTRICITY
H05K2201/09609
ELECTRICITY
H05K1/0289
ELECTRICITY
H05K1/0207
ELECTRICITY
H05K1/115
ELECTRICITY
International classification
Abstract
A multi-layer circuit board comprising a carrier plate with an upper surface and a lower surface, and at least one electrically conductive upper inner layer located on the upper surface of the carrier plate and an electrically insulating upper intermediate layer located thereon, and an electrically conductive upper outer layer located thereon, forming the outermost layer of the upper surface. At least one electrically conductive lower inner layer is located on the lower surface of the carrier plate and an electrically insulating lower intermediate layer located thereon, and an electrically conductive lower outer layer located thereon, forming the outermost layer of the lower surface. The upper and/or lower outer layers are populated with components, and conductor paths in one of the inner layers are oriented in different directions from conductor paths in the other inner layer, and the region between the conductor paths is flooded with a voltage.
Claims
1. A multi-layer circuit board comprising: a carrier plate with an upper surface and a lower surface; at least one electrically conductive upper inner layer on the upper surface of the carrier plate; an electrically insulating upper intermediate layer on the at least one electrically conductive upper inner layer; an electrically conductive upper outer layer on the insulating upper intermediate layer and forming an outermost layer of the upper surface of the carrier plate; at least one electrically conductive lower inner layer located on the lower surface of the carrier plate; an electrically insulating lower intermediate layer on the lower surface of the carrier plate; and an electrically conductive lower outer layer on the insulating lower intermediate layer and forming an outermost layer of the lower surface of the carrier plate; wherein at least one of the upper outer layer or the lower outer layer is populated with components, wherein conductor paths in the upper inner layer are connected to conductor paths in the lower inner layer, and wherein the conductor paths in the upper inner layer are oriented in a different direction from the conductor paths in the lower inner layer, and wherein a region between the conductor paths in the upper inner layer and the conductor paths in the lower inner layer is flooded with a voltage; wherein the multi-layer circuit board comprises a first conductor track located on at least the upper outer layer between at least two components located on the upper outer layer and electrically connected to one another, the first conductor track configured to conduct a power supply signal; and a second conductor track in the upper inner layer directly adjacent to the upper outer layer, the second conductor track configured to conduct a current return signal.
2. The multi-layer circuit board according to claim 1, wherein the conductor paths in the upper inner layer are substantially parallel to one another, wherein at least some of the conductor paths in the upper inner layer connect to at last some of the conductor paths in the lower inner layer, and wherein the conductor paths in the upper inner layer that are connected to the conductor paths in the lower inner layer are substantially orthogonal to the conduct paths in the lower inner layer.
3. The multi-layer circuit board according to claim 1, further comprising thermally conductive channels formed in the region between the conductor paths in the upper inner layer and the conductor paths in the lower inner layer that is flooded with the voltage, and formed parallel to at least one conductor path, the thermally conductive channels having at least one thermally conductive through connection.
4. The multi-layer circuit board according to claim 3, wherein a plurality of the conductor paths in the upper inner layer are combined to form a conductor path group.
5. The multi-layer circuit board according to claim 3, wherein a plurality of the thermally conductive through connections are at a predefined spacing to one another.
6. The multi-layer circuit board according to claim 1 further comprising additional conductor tracks in the lower outer layer.
7. The multi-layer circuit board according to claim 1, wherein the first conductor track is also located on the lower outer layer such that it is divided between the upper outer later and the lower outer layer, and wherein a connection between portions of the first conductor track located on the upper outer layer and portions of the first conductor track located on the lower outer later is obtained via at least one of an electrically conductive through connection or an insertion connector located between the upper outer layer and the lower outer layer.
8. The multi-layer circuit board according to claim 1, wherein at least one of the upper intermediate layer or the lower intermediate layer comprises a thickness of less than 100 m.
9. An electronic assembly comprising: a housing; and a multi-layer circuit board according to claim 1.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) Preferred embodiments of the present disclosure shall be explained in greater detail below based on the attached drawings.
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DETAILED DESCRIPTION
(10) In the following description of the drawings, identical elements and functions are given the same reference symbols.
(11) A multi-layer circuit board with at least four electrically conductive layers is provided for the purpose described above, wherein two of them form outer layers, i.e., the outermost layers, which can be populated with components. Furthermore, at least two of the other layers form electrically conductive inner layers. Further inner layers are conceivable, although the following descriptions refer to two inner layers, because the principles used herein can be applied to further inner layers.
(12)
(13) It can be seen in
(14) There is at least one more layer between an outer layer 21 or 31 and the carrier layer 1, referred to in the following as the upper inner layer 22 or lower inner layer 32, depending on their locations. Each of the inner layers 22 and 32 is separated from each adjacent layer by an electrically insulating intermediate layer. There is only one intermediate layer 22 or 32 in
(15) The layers 21-23 and 31-33 are each successively applied to the carrier by means of known methods.
(16) A substantial feature of the construction of the proposed multi-layer circuit board 100 is that the directions of the conductor paths 6 in the individual inner layers 22 and 32 (exclusively) are in a respective preferred direction. The respective preferred directions of the conductor paths 6 in the different inner layers 22 and 32 of the multi-layer circuit board 100 are shown in
(17) Furthermore, all of the regions of the multi-layer circuit board 100 that are not used for the conductor paths 6 are flooded with a voltage, e.g., a ground. This takes place in turn via known methods. The alignment of the conductor paths 6 in a preferred direction for each of the inner layers 22 and 32, and the flooding with a voltage 7, has the advantage that thermally conductive channels are formed parallel to the direction of the conductor paths 6, which are shown as arrows in the drawings. As a result, each conductor path 6 can have a dedicated thermally conductive channel 8. Conductor path groups 6 with m*n conductor paths 6 can also be densely arranged or routed. These groups 6 that bundle, e.g., analog conductors or digital conductors, can each have a single dedicated collective thermally conductive channel 8. As a result, there are thermally conductive channels 8 in the upper and lower inner layers 22 that are orthogonal to one another, when the conductor paths 6 or conductor path groups 6 are orthogonal to one another, as shown in
(18) Furthermore, densely arranged vertical thermal through connections 9 are formed in the thermally conductive channels 8 that thermally connect the individual electrically conductive layers to one another, in this case the inner layers 22 and 32. As a result, a dense network of thermally conductive channels 8 is formed in the inner layers 22 and 32, such that the heat generated by the current and/or the components can be evenly distributed in all of the regions of the multi-layer circuit board 100.
(19) It can also be seen that individual connections are extended, because diagonal routing is not used for the direct connection, such that all of the advantages listed above are clearly obtained.
(20) In a further development, the outer layers 21 and 31 are also used for conductor paths, as long as there is enough space between the components 4 and 41-43 placed on the multi-layer circuit board 100. It should also be noted that adjacent layers 21, 22 and 31, 32, are each oriented at a right angle to one another.
(21) Moreover, the advantages obtained from the routing concept described above, likewise regarding self-destruction and irradiation properties, are also substantial, because the thermally conductive channels 8 act in the same manner as symmetrical return paths for signals in the adjacent routing channel via densely arranged vertical through connections, resulting in a very low impedance grounding structure.
(22) Furthermore, signal groups or conductor path groups 6 that have applicable electrical properties, e.g., analog conductors, can be effectively bundled, and foreign signals, e.g., digital signals, can be effectively shielded via the grounding structure.
(23) Furthermore, the multi-layer circuit board 100 is simplified in that no metalized end surfaces and micro-connections are needed. In addition, the number of necessary copper layers, in particular the inner layers 22 and 32, can be reduced by the routing concept described herein, because dedicated ground layers are not necessary, due to the flooding of the regions of the multi-layer circuit board 100 that are not used for the conductor paths 6 with a voltage.
(24) In another embodiment, a simplified power routing concept is shown that is used for signals with a higher power consumption.
(25) An embodiment of the power supply conductors configured for increased power consumption is shown in
(26) The simplified power routing concept has various advantages obtained by the routing of the power supply signal on one of the outer layers 21 or 31. No electrically conductive through connections are needed for implementing the power supply, resulting in a power path via the power supply path, thus the first conductor track 61, with a nearly constant cross section, which is not reduced in size by the holes for the electrically conductive through connections. Furthermore, thermal impedances and associated losses are avoided in the routing of the power supply.
(27) By routing the current return signal, thus the second conductor track 62 to the first inner layer 22 adjacent to the outer layer 21 directly beneath the current supply signal, thus the first conductor track 61, a current path with a nearly constant cross section can likewise be provided via the current return path, that is not reduced in size by the holes for through connections. Furthermore, thermal impedances and associated losses are also avoided in the routing of the current return path. The electrically conductive through connections 5 necessary for connecting the current return path can be located in regions outside the power supply path 61, or adjacent to the power supply path 61, as shown in
(28) Furthermore, the necessary conductor cross section for the power supply conductor signal can be supplied by widened conductor tracks 61 on the outer layer 21, instead of using numerous layers in parallel. The same applies for providing the necessary conductor cross section for the current return path signals through widened conductor tracks 62 on the inner layer 22 adjacent to the outer layer 21. It is not necessary to use numerous layers in parallel for this either.
(29) This arrangement has the advantage that an enlarged overlapping surface area is obtained between the power supply and the current return paths. The width of the conductor tracks 61 and 62 depends on the necessary power consumption, and is determined by the person skilled in the art, depending on the application.
(30) In addition, a thin insulating medium, also referred to as the first intermediate layer 23 or 33, can be used between the outer layers 21 and 31 and the adjacent inner layers 22 and 33, respectively, e.g., exhibiting a thickness of d<100 m. This results in the advantage that there can be a smaller spacing between the outer layers 21 and 31 and the first inner layers 22 and 33, respectively. In combination with the enlarged overlapping surface area, the thermal transition resistance of the outer layers 21 and 31 serving as a heat source for the first inner layers 22 and 33, which functions as a heat sink in combination with other electrically conductive surfaces in the multi-layer circuit board, can be reduced to a minimum. Furthermore, reducing the spacing d results in an improved anti-parallel alignment of the power supply and the current return paths. This results in an improved current symmetry, and an improved, frequency independent, magnetic field elimination or magnetic field reduction.
(31) A further development of the assembly shown in
(32) An electronic assembly is shown in
REFERENCE SYMBOLS
(33) 100 multi-layer circuit board 1 carrier plate 2 upper surface of the carrier plate 21 upper outer layer 22 first upper inner layer 23 first upper intermediate layer d thickness of the intermediate layers 23 and 33 3 lower surface of the carrier plate 31 lower outer layer 32 first lower inner layer 33 first lower intermediate layer 4 electronic components 41 vehicle connector 42 transmission connector 43 valve connector 5 electrically conductive through connections 6 conductor paths 61 first conductor track 62 second conductor track 7 ground 8 thermally conductive channel 9 thermal through connections 300 electronic assembly 200 housing 201 lid