Digital circuit arrangements for ambient noise-reduction

Abstract

A digital circuit arrangement for an ambient noise-reduction system affording a higher degree of noise reduction than has hitherto been possible. The arrangement converts the analog signals into N-bit digital signals at sample rate f.sub.0, and then subjects the converted signals to digital filtering. The value of N in some embodiments is 1 but, in any event, is no greater than 8, and f.sub.0 may be 64 times the Nyquist sampling rate but, in any event, is substantially greater than the Nyquist sampling rate. This permits digital processing to be used without incurring group delay problems that rule out the use of conventional digital processing in this context. Furthermore, adjustment of the group delay can readily be achieved, in units of a fraction of a micro-second, providing the ability to fine tune the group delay for feed forward applications.

Claims

1. A noise cancellation circuit, comprising: an input for receiving an input analog signal from a microphone; an analog-digital converter, configured for converting the analog signal into a digital signal having an over-sampling rate; a digital filter, connected to receive the digital signal, and to operate at said over-sampling rate; a digital delta-sigma modulator, connected to receive an output of the digital filter, and configured to operate at said over-sampling rate; and a digital-analog converter, connected to receive an output of the digital delta-sigma modulator, and configured for converting the output of the digital delta-sigma modulator into an analog output signal; wherein the noise cancellation circuit does not include decimating or interpolating filters.

2. A noise cancellation circuit according to claim 1, wherein the analog-digital converter comprises an analog delta-sigma modulator.

3. A noise cancellation circuit according to claim 1, wherein the over-sampling rate is at least 16 times an upper noise cancelling frequency in an audio band.

4. A noise cancellation circuit according to claim 3, wherein the over-sampling rate is at least 128 times an upper noise cancelling frequency in an audio band.

5. A noise cancellation circuit according to claim 1, wherein the over-sampling rate is greater than 50 kHz.

6. A noise cancellation circuit according to claim 1, wherein the over-sampling rate is greater than 200 kHz.

7. A noise cancellation circuit according to claim 1, wherein the over-sampling rate is greater than 400 kHz.

8. A noise cancellation circuit according to claim 1, wherein the over-sampling rate is greater than 800 kHz.

9. A noise cancellation circuit according to claim 1, wherein the digital filter is a low-bit filter.

10. A noise cancellation circuit according to claim 9, wherein the digital filter is a 1-bit filter.

11. A noise cancellation circuit, comprising: an input for receiving an input analog audio signal from a sensor; an analog-digital converter, configured for converting the analog audio signal into a digital audio signal having an over-sampling rate; a digital filter, connected to receive the digital audio signal, and to operate at said over-sampling rate; a digital audio processor, connected to receive an output of the digital filter, and configured to operate at said over-sampling rate; a digital-analog converter, connected to receive an output of the digital audio processor, and configured for converting the output of the digital audio processor into an analog output audio signal; wherein the noise cancellation circuit does not include decimating or interpolating filters.

12. A noise cancellation circuit according to claim 11, wherein the digital audio processor is a digital signal processor.

13. A noise cancellation system, comprising: a sensor, for generating an input analog audio signal; and a noise cancellation circuit comprising: an analog-digital converter, configured for converting the analog audio signal into a digital audio signal having an over-sampling rate; a digital filter, connected to receive the digital audio signal, and to operate at said over-sampling rate; a digital audio processor, connected to receive an output of the digital filter, and configured to operate at said over-sampling rate; and a digital-analog converter, connected to receive an output of the digital audio processor, and configured for converting the output of the digital audio processor into an analog output audio signal; wherein the noise cancellation circuit does not include decimating or interpolating filters.

14. A noise cancellation system according to claim 13, further comprising a loudspeaker, connected to receive the analog output audio signal.

15. A noise cancellation system according to claim 14, wherein the loudspeaker is the loudspeaker of a phone handset.

16. A noise cancellation system according to claim 13, wherein the sensor comprises a transducer.

17. A noise cancellation system according to claim 16, wherein the transducer comprises a microphone.

18. A noise cancellation system according to claim 17, wherein the microphone is the microphone of a phone handset.

Description

(1) In order that the invention may be clearly understood and readily carried-into effect, embodiments thereof will now be described; by way of example only, with reference to the accompanying drawings, of which:

(2) FIG. 1a has already been referred to, and is a diagram explanatory of the feedback type of ambient noise reduction system;

(3) FIGS. 1b and 2 also have been referred to already, and comprise diagrams explanatory of the feed-forward type of ambient noise reduction system;

(4) FIG. 3 shows a conventional electronic filter using digital processing;

(5) FIG. 4 shows a conventional digital audio processor;

(6) FIG. 5 shows a conventional delta-sigma analogue-to-digital converter;

(7) FIG. 6 shows a conventional delta-sigma digital-to-analogue converter;

(8) FIG. 7 shows a 1-bit processing system;

(9) FIG. 8 shows, in schematic form, a circuit arrangement in accordance with one embodiment of the invention;

(10) FIG. 9 shows, in schematic form, a circuit arrangement in accordance with another embodiment of the invention;

(11) FIG. 10 shows a typical first-order analogue delta-sigma modulator usable with the invention;

(12) FIG. 11 shows, for comparison with FIG. 10, a typical third-order analogue delta-sigma modulator-usable with the invention;

(13) FIG. 12 shows a typical first-order digital delta-sigma modulator usable with the invention;

(14) FIG. 13 shows, for comparison with FIG. 12, a typical third-order digital delta-sigma modulator usable with the invention;

(15) FIG. 14 shows a conventional second-order IIR filter usable with the invention; and

(16) FIG. 15 shows a developed form of the invention, in which certain processing functions are merged.

(17) Before describing embodiments of the invention in detail, some further background information will be provided in relation to the difficulties facing the designer of a filter circuit for use in the present context.

(18) As mentioned briefly above it is necessary, in designing filters for both the feed-forward and feedback systems, to take into account the acoustic arrangements and all of the other electronic components in the circuit. Two of these elements in particular complicate the design of the filter: The characteristics of the electro-mechanical speaker are complex and it is difficult to design analogue filters to compensate for these characteristics below a few hundred Hz. Common microphone types have a low-frequency response that extends down to a few Hz or below. A high-pass filter may be required to prevent large amplitude very low frequency acoustic signals picked up by the microphone from driving the electronics into saturation. This filter can take the form of a simple RC circuit, but such circuits do not have a sufficiently steep cut-off to avoid adversely affecting the filter response for the lower audible frequencies it is desired to cancel. The phase response is particularly badly affected by such circuit elements.

(19) The electronic filter therefore needs to have a complex amplitude and phase response. In practice, all commercial consumer noise reducing headphones use an analogue electronic filter (if any filter is used at all). However, the filter is often far from perfect, as the design of an analogue filter with the required amplitude and phase characteristics is difficult, as noted above, ad nearly impossible to achieve with a cost-effective number of components. In order to ensure manufacturability, close tolerance components may also have to be used, further increasing costs. To achieve some of the required low-frequency filter response shaping, large capacitors may be required. These are relatively expensive and bulky. For mass-produced products, an application-specific integrated circuit (ASIC) can be used to reduce component costs, but a number of external components are still required, and development cost of the ASIC is difficult to justify. This assertion is borne out by the fact that no currently available commercial consumer noise reduction system for earphones uses a custom ASIC to implement the filter.

(20) Against the foregoing background, it is attractive to consider the use of digital filtering technology, particularly when it is considered that digital filters are well known for their ability to implement almost any required filter response in an accurate, repeatable, stable and cost-effective way. Digital ASICs can be produced at very low-cost and require few, if any, external components. Moreover, if digital technology is used, it also becomes relatively easy to add advanced control features, or to integrate the noise-cancellation circuit with other functions, such as an MP3 player or music enhancement algorithm. A still further advantage of using digital technology is that it can readily be configured for different acoustic arrangements with a read-only data memory, for example. In contrast, analogue circuits require many component changes, or a re-design, to suit different acoustic arrangements. Digital processing therefore has many advantages over analogue for this application.

(21) However, a conventional application of digital processing presents serious difficulties as regards the group delay imposed by the system. This is explained with reference to FIG. 3, which shows schematically an arrangement consisting of an analogue-to-digital converter (ADC) 31, a digital filter 32, and a digital-to-analogue converter-(DAC) 33. The ADC 31 and DAC 33 must be clocked at a minimum of twice the maximum audio frequency to be accommodated (as dictated by the Nyquist criterion), so the minimum clock frequency for a system designed to cancel noise up to 5 kHz, for example, is 10 kHz. The major difficulty with such an arrangement in the present application is that each of the elements in the filter introduces a significant delay, contributing to an overall delay which is known as the group-delay. The importance of avoiding the introduction of additional delay into feedback and feed-forward systems used in this context has been emphasised in the foregoing and, although the use of higher sampling rates can somewhat reduce the delay, they are still excessive, even if a typical audio sampling rate of 48 kHz is employed.

(22) There are various ADC and DAC technologies known, but most audio quality converters are of the so-called delta-sigma type. A typical example of an ADC is the AD1870 from Analog Devices Inc., which exhibits a group delay of 750 micro-seconds at a sampling rate of 48 kHz; this delay being of itself almost twenty times the example target of micro-seconds, referred to above for a feed-forward system. Delta-sigma DAC converters have similar group delays. Faster converter technologies exist, including the flash type of converter, but these are prohibitively expensive. Irrespective of how low the ADC and DAC delays can be made, however, the digital filter 32 has a group delay which alone is too high. A typical digital filter incurs a few audio samples of delay, the delay being larger for more complex filter shapes. Even a simple 5.sup.th order-48 kHz digital filter, with a 5-sample delay, incurs a delay of approximately 100 micro-seconds. The group delay of the whole processing chain is thus typically 750 micro-seconds (attributable to the ADC 31) plus 100 micro-seconds (attributable to the digital filter 32) plus 750 micro-seconds (attributable to ADC 33) amounting to some 1600 micro-seconds, which is around 40 times too large. The only way to reduce the time delay of such a system to acceptable levels would be to use a much higher clock rate. This would not be commercially viable on cost grounds and would increase power consumption; an important consideration for a battery-powered application. Accordingly there is, to the Inventor's knowledge, no current commercial consumer noise-cancelling earphone system using a digital filter for the purpose of performing direct cancellation.

(23) It should be noted that digital processing is used in some noise-cancelling headphone products but this processing does not attempt to provide cancellation by time alignment of the ambient acoustic signal and the cancellation signal, but invariably operates on repetitive audio signals, providing adaptive filtering, for example using least mean square (LMS) techniques. The group delay problem is not a consideration in those applications, and they are not relevant to the present invention as they do not attempt to directly cancel the noise. Those systems make use of the repetitive nature of noise to predict noise ahead of time, thus overcoming the need for a low group delay. Although such systems can effectively cancel repetitive noise, they fail when the noise is not predictable. The present invention relates to noise cancelling systems that do not rely on the repetitive nature of the noise to operate satisfactorily.

(24) Completely independently of the above discussion, further background concerning digital processing needs to be described in order for the invention to become clear.

(25) Conventional digital audio processing utilises a relatively large number of bits in the ADC, in order to represent the audio-signal with sufficient accuracy and to ensure that the quantisation noise is at an adequately low level, allowing the desired signal-to-noise ratio (SNR) to be achieved. 16 or more bits are commonly used for audio to achieve SNR figures in excess of 90 dB. The conventional digital signal processor shown in FIG. 4 consists of a delta-sigma ADC 41, a digital processing circuit (filter) 42, and delta-sigma DAC 43. The digital processing circuit 42 typically operates on 16-bit or 24-bit words and is a very well established technology area.

(26) The internal architectures of the delta-sigma ADC and DAC are shown in FIGS. 5 and 6 respectively. It will be seen that the first part of the ADC 50 is a delta-sigma modulator 51, which feeds a decimating filter 52. The output of the delta-sigma modulator 51 has N bits, where N is typically a relatively small number; preferably in the range from 1 to 5. In this example, 1 bit is used, and the system operates with a relatively high sampling rate which is typically 64 times the required audio sampling rate (the over-sampling rate). In order to obtain a good SNR, it is necessary to shape the spectrum of the noise at the output of the delta-sigma modulator 51 so that most of the noise falls outside the audio bandwidth. This is a feature of all delta-sigma ADCs. The decimating filter 52 is a digital filter that increases the number of bits to (say) 16 and reduces the sampling rate down to the audio sampling rate.

(27) The DAC 60 consists of an interpolating filter 61, followed by a delta-sigma modulator 62 and N-bit DAC 63, where N is typically 1. The interpolating filter 61 increases the sampling rate to the over-sampling rate.

(28) Higher audio quality can be achieved by performing the digital-processing of FIG. 4 at the over-sampling rate and in the 1-bit domain, as shown in FIG. 7, wherein a signal processing circuit 70 consisting of an analogue delta-sigma modulator 71, 1-bit digital filter 72, digital delta-sigma modulator 73 and 1-bit DAC 74. The circuit 70 operates at the over-sampling rate, and it will be noted that it is equivalent to the front half of a conventional delta-sigma ADC, a 1-bit processor, and the back half of a conventional delta-sigma DAC. It is important to note that the decimating and interpolating filters 52 and 61 are not present.

(29) The output from a 1-bit DAC is simply a signal that switches between two levels, and it can therefore be used to directly drive a loudspeaker, avoiding the need for a linear power amplifier, in a similar way to the well-known Pulse Width Modulated (PWM) Class D amplifier. The loudspeaker provides an effective low-pass filter and recreates the analogue waveform accurately. However, the 1-bit approach has advantages over a PWM Class D amplifier, as a lower clock is required, though to make the power stage efficient, it is desirable in practice to reduce the average number of output transitions per second, as described, for example, in Sigma-Delta Modulation in Digital Class-D Power Amplifiers: Methods for reducing the effective pulse transition rate; R Esslinger, G Gruhler, and R. W. Stewart; Audio Engineering Society 112 Convention, Munich, May 10-13, 2002, and the invention envisages the incorporation, into an ambient noise-reduction system of the kind described herein, of a circuit to implement such a method.

(30) Furthermore, the implementation of a 1-bit digital processor requires fewer logic gates than a processor with a 16-bit or higher word size. In particular, a 1-bit processor can be implemented without using any multipliers, reducing gate count considerably in a hardware design. The delta-sigma modulators, being only part of a conventional delta-sigma ADC and DAC, are cheaper to implement than the conventional converters.

(31) The present invention provides an ambient noise-reduction system affording a higher degree of noise reduction than has hitherto been possible, through the use of a low latency signal processing chain consisting of analogue-to-digital conversion, digital processing and digital-to-analogue conversion. All the advantages of digital processing described above are obtained without incurring the group delay that rules out conventional digital processing. Specifically, it becomes possible to implement the required amplitude and phase response much more accurately than is possible with practical analogue circuits. Furthermore, adjustment of the group delay can readily be achieved, in units of a fraction of a micro-second, providing the ability to fine tune the group delay for feed-forward applications.

(32) This is achieved by applying processing techniques using only a few bits to the electronic filter, i.e. by using a reduced number of bits (preferably in the range from 1 to 5 inclusive) in the audio sample, and an increased sample rate, compared to conventional digital processing techniques. In the extreme, it is possible to use 1-bit audio samples, and the following description will be presented for that example case, although the principles are equally valid for other numbers of bits per sample.

(33) The inventor has determined that the 1-bit processing technique has a very low group delay, a characteristic that is not of significant benefit in most applications. The reason for the low delay is that the cause of the delays in delta-sigma converters is primarily the decimating and interpolating filters which, as described above, are omitted from this-configuration; the delta-sigma modulators being responsible for very little delay. The inventor has also determined that it is possible to perform the required electronic filtering directly on the 1-bit signal.

(34) The low delay times associated with 1-bit (or, in general, N-bit, where N is no greater than 8) processing are of crucial value to noise reduction, and the use of such processing solves the fundamental delay problem that has, until now, prevented the use of digital processing in this context.

(35) This embodiment of the invention thus applies N-bit, and preferably 1-bit, processing principles to noise reduction, in order to obtain the advantages of digital processing without incurring the unacceptable group delay that rules out conventional digital processing.

(36) The group delay of a typical delta-sigma modulator is only a few clock cycles; and the delay of a suitable typical 1-bit processor is of the order of 10-20 clock cycles. Crucially, however, all of these delays are measured in clock cycles at the over-sampling rate, which is typically 64 times an audio sample rate of 48 kHz, i.e. around 3 MHz; equating to a clock cycle of only 0.33 micro-seconds. The entire 1-bit electronic filter can therefore have a group-delay of 10 micro-seconds or less; well within the above-exemplified target of 40 micro-seconds for a feed-forward arrangement.

(37) FIG. 8 shows an embodiment of the invention for the feed-forward arrangement, and FIG. 9 shows one for the feedback arrangement. It will be appreciated that inputs for music or other signals intended for the listener's attention can be provided in either embodiment, and coupled into any convenient point in the circuit.

(38) Referring now to FIG. 8, in which components common to FIG. 1a carry the same reference numbers, the microphone 13 feeds the loudspeaker 14 by way of a digital processing chain 80, comprising the series connection of an analogue delta-sigma modulator 81, a 1-bit digital filter 82, a digital delta-sigma modulator 83 and a 1-bit DAC 84 which is configured to drive the loudspeaker 14 directly from its output; making it possible to use the Class D principles described above.

(39) FIG. 9 shows an embodiment of the invention as applied to a feed-forward system and, accordingly, components common to FIG. 1b carry the same reference numbers. In FIG. 9, the feed-forward path from the microphone 23 to the loudspeaker 24 is via a digital processing path 90 comprising an analogue delta-sigma modulator 91, a 1-bit digital filter 92, a digital delta-sigma modulator 93 and a 1-bit DAC 94.

(40) Each of the functional units of FIGS. 8 and 9 will now be described in detail.

(41) The internal architecture of a typical analogue delta-sigma modulator 81, 91 is shown in FIG. 10. The analogue difference between an input 121 and the output of a 1-bit DAC 122 is formed by a subtractor 123, and is integrated over time by an integrator 124. The output of this integrator is compared to a reference level in a comparator 125, this performing conversion from the analogue domain to the digital domain. The output of comparator 125 is clocked into a D-type latch 126 under the control of an over-sampling clock (not shown) which applies clocking pulses over a connection 127. The output of the latch 126 is the 1-bit output signal 128 of the delta-sigma modulator, provided on an output line 128; The 1-bit output from latch 126 is also fed into the 1-bit DAC 122 to complete the feedback loop. This circuit is called a first-order delta-sigma modulator because it has one integrator stage.

(42) A basic understanding of the operation of this circuit can be obtained by appreciating that the output of the subtractor 123 represents the error between the analogue input 121 and the 1-bit digital output on line 128, as fed back through DAC 122. This error is positive if the output on line 128 is a logic 0, and is negative if the output on line 128 is a logic 1. This error causes the output of the integrator 124 to increase if the input 121 is greater than the output on line 128, or to decrease if the input is smaller than the output. When the output of the integrator 124 crosses the threshold level applied to the comparator 125, the output of comparator 25 switches state; a logic 1 indicating that the input 121 is greater than output on line 128, and a logic 0 indicating that the input is less than the output. On the next edge of the clock pulses applied on line 127, D-type latch 126 will therefore change output state; DAC 122 output and the output of subtractor 123 will both change sign; and the output of the integrator 124 will start changing in the opposite direction to previously. When the comparator threshold is again crossed, the next clock will cause the output to change state again and the cycle repeats.

(43) The output therefore continually flips between logic 1 and 0, and it will be observed that the higher the input signal, the more time the output spends as a logic 1 compared to a logic 0; and the lower the input signal, the more time the output spends as a logic 0 compared to a logic 1. The output signal therefore represents the input signal, but contains a significant amount of high-frequency noise caused by the rapid switching of the output.

(44) To understand how this signal is a useful representation of the input, and why the high frequency noise is not a-problem, it is necessary to consider the signals in the frequency domain. The circuit of FIG. 1-0 is, as mentioned previously, known as a first-order delta-sigma modulator because there is one integrator in the loop. The integrator has the effect of distributing the noise towards the higher frequency end of the spectrum but, because the clock used runs at a frequency many times greater than the audio bandwidth, most of the noise is pushed outside the audio band. It is therefore possible to low-pass filter the 1-bit signal and recreate the audio with an acceptable signal-to-noise ratio. One such simple low-pass filter is that inherent in a typical electro-mechanical loudspeaker, which has a decreasing sensitivity with increasing frequency. It is therefore possible to feed the 1-bit signal directly to a loudspeaker to re-create the original audio.

(45) In practice, higher order delta-sigma modulators are commonly used, typically up to 5.sup.th order, in order to move even more of the noise outside the audio band. FIG. 11 shows an example 3rd order delta-sigma modulator, in which a subtractor 131 performs the same function as subtractor 123 in FIG. 10. The output of the subtractor 131 is fed to a chain of three integrators 132, 133 and 134. The outputs of these integrators are multiplied by coefficients C1, C2 and C3 respectively in multipliers 135, 136 and 137, and mixed in a summer 138. The output of the summer 138 is fed into a comparator 139, which performs the same function as comparator 125 in FIG. 10. The remainder of the circuit is the same as FIG. 10. The action of combining the outputs of the integrators in this way forms an analogue filter which-defines the way that the noise is distributed across the spectrum. Such a filter is usually referred to as a noise-shaping filter, for this reason.

(46) In the embodiments of the invention shown in both FIGS. 8 and 9, the group delay can easily be adjusted in the 1-bit processor 82, 92 in increments of one sample at the over-sampling rate (for example 0.33 micro-seconds) using conventional techniques involving-shift registers, memories or chains of flip-flops, for example. This facility is of particular benefit in relation to the embodiment shown in FIG. 9, as it permits fine tuning of the group delay time, which is particularly beneficial in feed-forward systems.

(47) Common signal processing operations in a 1-bit processor result in an increase in the number of bits from input to output. FIGS. 7, 8 and 9 show the increased number of bits as a value X. It is necessary to convert back to a 1-bit format before sending the signal to the 1-bit DAC 84, 94, and this is the function of the digital delta-sigma modulator 83, 93.

(48) The function of the digital delta-sigma modulator is now described in further detail. The internal architecture of a typical digital delta-sigma modulator 83, 93 in FIGS. 8 and 9 is shown in FIG. 12. Similarities to the analogue delta-sigma modulator will be observed. The input 141, a multi-bit digital signal, is-fed into a subtractor 142, whose other input comes from a feedback loop that is described below. The output of the subtractor 142 is fed into an adder 143, which in turn feeds a latch 144, which is clocked by over-sampling clock pulses applied on a line 145. The output of the latch 144 is fed back into the adder 143. The combination of adder 143 and latch 144 forms an integrator, equivalent to the integrator 124 in FIG. 10. The Most Significant Bit (MSB) extractor indicated at 146 is the equivalent to the comparator 125 of FIG. 10, and effects a trivial operation that converts the signal from a multi-bit digital signal into a 1-bit signal. The output of MSB extractor 146 is the 1-bit output 147 of the delta-sigma modulator. The output of MSB extractor 146 is also fed into unit 148, which effects another trivial operation to convert the 1-bit signal into a two-level multi-bit digital signal to complete the feedback loop by connection into the subtractor 142. The converter unit 148 is the equivalent to the 1-bit DAC 122 of FIG. 10.

(49) The similarity of the digital and analogue versions of the delta-sigma modulator is clear, and it is commonplace to use higher order digital delta-sigma modulators in a similar way to that described above for analogue delta-sigma modulators, thus allowing a noise-shaping filter to be implemented. An example of a third order version is shown in FIG. 13.

(50) Multi-bit digital input 151 is connected to a chain of three integrators, consisting of adders 152a, 152b, 152c, and latches 153a, 153b, 153c, clocked by over-sampling clock pulses applied over a line 154. The output of the final latch 153c is connected to an MSB extractor 155, which generates the 1-bit output 156 and also feeds back via level converter 157 and individual multipliers 158 to the adders 152.

(51) The noise-shaping filter shape is determined by the multiplier coefficients C1, C2 and C3. In this respect, it should be noted that the multipliers can be implemented simply because the feedback data input is a two-state signal and therefore the output of each multiplier can only take one of two values, allowing it to be implemented as a sign switch on the coefficient value. This demonstrates one of the advantages of 1-bit processing.

(52) Just as for the analogue delta-sigma modulator, the noise-shaping filter is an important part of the delta-sigma modulator. To convert a multi-bit digital signal into a 1-bit signal without using noise shaping would be equivalent to simply taking the most significant bit of the multi-bit signal as the 1-bit version. This would introduce noise across the whole-frequency spectrum, including the audio band. The use of the noise-shaping filter within the delta-sigma modulator architecture allows the conversion from the multi-bit to the 1-bit domain to be performed without the introduction of excessive noise in the audio band. It is therefore essential, in this embodiment, that the digital delta-sigma modulator follows the 1-bit digital filter 82, 92 of FIGS. 8 and 9, as this is the only satisfactory way of converting from a multi-bit digital signal to a 1-bit digital signal.

(53) The 1-bit DAC 84 and 94 perform simple operations designed to obtain an accurate analogue representation of the 1-bit digital signal. Although it is a simple function, it is well known that designers need to take care to ensure clean switching edges, stable voltage references levels and so on.

(54) The 1-bit filter 82, 92 can be designed using the same design principles as a conventional multi-bit-digital filter, for example the second order IIR filter shown in FIG. 14. However, if the input is a 1-bit signal, the multipliers for the feed-forward coefficients (B0, B1, B2) become simple sign switches. The feedback coefficient multipliers are full multi-bit multipliers, but coefficients can usually be selected to minimise the multiplier size.

(55) It is of course possible to combine various elementary filters into a more complex arrangement in order to satisfy the filtering requirements.

(56) Some simplification of the overall circuit is sometimes possible, by combining the functions of the 1-bit filter 82, 92 and the noise-shaping filter of the digital delta-sigma modulator 83, 93 into a single filter unit.

(57) FIG. 15 shows in outline such an arrangement, usable for either feedback or feed-forward systems, with the combined 1-bit digital filter and digital delta-sigma modulator being shown at 161. It will be understood that the combined filter and modulator 161 comprises in effect a combination of components 82 and 83 (FIG. 8) or 92 and 93 (FIG. 9).

(58) It is also possible to split the combined filter and modulator 161 into two or more cascaded sections, each having its own delta-sigma modulator, so as to return to the 1-bit domain more than once.