Method for minimizing distortion of a signal in a radiofrequency circuit

Abstract

A method for minimizing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer, wherein a curve representing the distortion as a function of a power of the input or output signal exhibits a trough around a given power (P.sub.Dip), the method comprises applying, between the radiofrequency circuit and the semiconductor substrate, an electrical potential difference (V.sub.GB) chosen so as to move the trough toward a given operating power of the radiofrequency circuit.

Claims

1. A method for minimizing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer, wherein a curve representing the distortion as a function of a power of an input or output signal exhibits a trough around a given power (P.sub.Dip), the method comprising applying, between the radiofrequency circuit and the semiconductor substrate, an electrical potential difference (V.sub.GB) chosen so as to move the trough toward an operating power of the radiofrequency circuit.

2. The method of claim 1, wherein the electrical potential difference (V.sub.GB) is chosen so as to comply with the following equation: V.sub.pk=|V.sub.GBV.sub.FB|, where V.sub.pk is the peak voltage of the radiofrequency signal and V.sub.FB is the flat band voltage.

3. The method of claim 1, wherein the semiconductor substrate has an electrical resistivity of greater than 500 .Math.cm.

4. The method of claim 3, wherein a polycrystalline silicon layer is disposed between the semiconductor substrate and the electrically insulating layer.

5. The method of claim 4, wherein an additional electrically insulating layer is disposed between the semiconductor substrate and the polycrystalline silicon layer.

6. The method of claim 1, wherein the semiconductor substrate comprises silicon.

7. The method of claim 1, further comprising adjusting the electrical potential difference (V.sub.GB) applied between the semiconductor substrate and the radiofrequency circuit depending on the operating power of the radiofrequency circuit.

8. The method of claim 1, further comprising measuring a temperature of the radiofrequency circuit, and adjusting the electrical potential difference (V.sub.GB) applied between the semiconductor substrate and the radiofrequency circuit depending on the measured temperature.

9. The method of claim 1, wherein the curve representing the distortion of the signal is a curve of the level of generation of a second or of a third harmonic of the input signal or of the output signal as a function of the power of the input signal or of a fundamental component of the output signal.

10. A radiofrequency device, comprising: a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer; a contact connected electrically to the semiconductor substrate; a device configured to apply a potential difference (V.sub.GB) between the contact and the radiofrequency circuit, the potential difference (V.sub.GB) selected so as to move a trough around a given power (P.sub.Dip) in a curve representing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in the circuit as a function of a power of the input or output signal toward an operating power of the radiofrequency circuit.

11. The device of claim 10, wherein the device configured to apply the potential difference (V.sub.GB) comprises a voltage generator and a voltage control module configured to adjust the voltage of the generator depending on the operating power of the radiofrequency circuit.

12. The device of claim 11, wherein the semiconductor substrate has an electrical resistivity of greater than 500 .Math.cm.

13. The device of claim 12, further comprising a polycrystalline silicon layer disposed between the semiconductor substrate and the electrically insulating layer.

14. The device of claim 13, further comprising an additional electrically insulating layer disposed between the semiconductor substrate and the polycrystalline silicon layer.

15. The device of claim 14, wherein the semiconductor substrate comprises silicon.

16. The device of claim 15, further comprising a temperature sensor coupled to the device configured to apply the potential difference (V.sub.GB), the device configured to apply the potential difference (V.sub.GB) being configured to adjust the potential difference depending on the temperature measured by the sensor.

17. The device of claim 15, further comprising a temperature sensor coupled to the device configured to apply the potential difference (V.sub.GB), the device configured to apply the potential difference (V.sub.GB) being configured to adjust the potential difference depending on the temperature measured by the sensor.

18. The device of claim 10, wherein the semiconductor substrate has an electrical resistivity of greater than 500 .Math.cm.

19. The device of claim 18, further comprising a polycrystalline silicon layer disposed between the semiconductor substrate and the electrically insulating layer.

20. The device of claim 10, wherein the semiconductor substrate comprises silicon.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantages and features of embodiments of the present disclosure will emerge from the following detailed description, with reference to the appended drawings, in which:

(2) FIG. 1A is a perspective view of a radiofrequency circuit formed on an SOI substrate with high electrical resistivity;

(3) FIG. 1B is a perspective view of a radiofrequency circuit formed on an SOI substrate of trap rich type;

(4) FIG. 1C is a perspective view of a radiofrequency circuit formed on a trap rich SOI of double BOX type;

(5) FIG. 2 shows curves of the level of generation of the third harmonic (in dBm) as a function of the level of the first harmonic of the output signal (in dBm), for a silicon substrate with standard resistivity, for various potential differences applied between the substrate and the radiofrequency circuit;

(6) FIG. 3 shows curves of the level of generation of the second harmonic (in dBm) as a function of the level of the first harmonic of the input signal (in dBm), for a trap rich SOI substrate with a silicon carrier substrate with high resistivity;

(7) FIG. 4 shows various configurations of the voltage to be applied between the semiconductor substrate and the radiofrequency circuit in order to attain the flat band voltage of the metal-insulator-semiconductor structure as a function of the peak voltage of the signal;

(8) FIG. 5 shows the principle of the performance optimization afforded by adjusting the position of the trough of the level of generation of the second harmonic as a function of the level of the first harmonic;

(9) FIG. 6 shows curves of the level of generation of the second harmonic (in dBm) as a function of the level of the first harmonic of the output signal (in dBm), for an SOI substrate with a silicon carrier substrate with high resistivity, for various potential differences applied between the semiconductor substrate and the radiofrequency circuit;

(10) FIGS. 7A and 7B show curves of the level of generation of the second harmonic as a function of the level of the first harmonic for a trap rich SOI substrate having, under the electrically insulating layer, a polycrystalline silicon layer, with a thickness of 0.4 m and with a thickness of 1.7 m, respectively, at temperatures of 60 and 90 C.,

(11) FIGS. 8A to 8C illustrate embodiments of the present disclosure applied to an SOI substrate with a silicon carrier substrate with high resistivity, a trap rich SOI substrate and a trap rich double BOX SOI substrate, respectively.

(12) To make the figures legible, the various layers forming the substrates are not necessarily shown to scale.

DETAILED DESCRIPTION

(13) The present disclosure is based on the observation, with certain semiconductor substrates coated with an electrically insulating layer, of a local drop of the level of generation of a harmonic or of the level of intermodulation for a certain power of the input signal.

(14) The term level of generation of a harmonic is understood, in the present text, to mean the power of a given harmonic measured at the output of the radiofrequency circuit, expressed in dBm. This power may be expressed for a power of the fundamental component of the input signal (the notation in will then be used) or of the output signal (the notation out will then be used).

(15) In the remainder of the description, consideration will often be given to the level of generation of the second harmonic (denoted HD2), but the present disclosure may also be implemented with consideration to the level of a higher generated harmonic, for example, the third harmonic (denoted HD3), or even a level of intermodulation. In a general manner, these levels represent the non-linearity of the substrate.

(16) In the remainder of the description, the example will generally be taken of a silicon substrate with high resistivity coated with a layer of silicon oxide, but the present disclosure applies more generally to a semiconductor substrate coated with an electrically insulating layer. In general, these semiconductor substrates belong to SOI substrates whose semiconductor thin layer is at least locally removed in order to deposit the electrically conductive lines on the electrically insulating layer (the semiconductor thin layer being able to be kept in other regions of the substrate so as to form electronic components). As an alternative, the electrically insulating layer could be formed by oxidation of a semiconductor substrate, with high resistivity or with standard resistivity, without an SOI substrate being formed.

(17) A drop in the level of generation of the third harmonic is visible in FIG. 2, which relates to a radiofrequency circuit formed on an SOI comprising a silicon substrate having a standard electrical resistivity (lower than the abovementioned high resistivity, for example, of the order of 10 .Math.cm), for various potential differences V.sub.GB applied between the silicon substrate and the radiofrequency circuit.

(18) A drop in the level of generation of the second harmonic is also visible in FIG. 3, which relates to a radiofrequency circuit formed on an SOI comprising a silicon substrate having a high electrical resistivity, for a given potential difference V.sub.GB applied between the silicon substrate with high electrical resistivity of the trap rich SOI substrate and the radiofrequency circuit.

(19) FIGS. 2 and 3 show the level of generation of the third and of the second harmonic of the output signal, respectively, expressed in dBm, as a function of the level of the first harmonic, that is to say the fundamental component, of the input signal, also expressed in dBm.

(20) It is recalled that the powers Pin and Pout in dBm are simply offset by an interval corresponding to the losses of the conductive line in dBm. For example, if the losses are 3 dBm over the whole line at the frequency of the fundamental component, and a trough is observed in the curve Pin vs. HD2 at +20 dBm from Pin, this trough will be located at +17 dBm from Pout_H1 in the curve Pout_H1 vs. HD2.

(21) It is seen that these curves have a trough with a significant amplitude in a given range of the power Pin, this range being of small width and generally situated in the high power values, around a value denoted P.sub.Dip in FIG. 3.

(22) The presence of this trough implies that, surprisingly, in this power range, the level of generation of the third, respectively of the second, harmonic is substantially lower than if the curve had remained substantially straight.

(23) The inventors account for the position of this trough through the input power corresponding to the situation where the peak amplitude of the radiofrequency signal, denoted V.sub.pk, reaches or exceeds the flat band voltage, denoted V.sub.FB. This trough therefore appears for a level of power in watts P.sub.Dip, associated with a signal amplitude V.sub.pk.sub.Dip, and expressed by the following equations:

(24) $P_{\mathrm{Dip}}=\frac{V_{{\mathrm{pk}}_{\mathrm{DIP}}}^2}{2.Math.Z_{\mathrm{REF}}}$$V_{{\mathrm{pk}}_{\mathrm{dip}}}=.Math.V_{\mathrm{GB}}-V_{\mathrm{FB}}.Math.$

(25) Therefore:

(26) $P_{\mathrm{Dip}}=\frac{{\left(V_{\mathrm{GB}}-V_{\mathrm{FB}}\right)}^2}{2.Math.Z_{\mathrm{REF}}}$

(27) where Z.sub.REF is the reference impedance of the system (generally 50 ohms), V.sub.GB is the electrical potential difference applied between the radiofrequency circuit and the semiconductor substrate, and V.sub.FB is the flat band voltage of the semiconductor-insulator-metal structure. This voltage characterizes a state of the semiconductor substrate under the electrically insulating layer that is neither in desertion regime nor in accumulation regime. In this state, the Fermi levels of the metal, of the insulator and of the semiconductor material are aligned.

(28) The trough is thus able to be positioned at the desired level of power by applying an appropriate potential difference V.sub.GB, so as to comply with the above equations.

(29) As illustrated in FIGS. 4 (a) to (d), various situations exist, depending on the positions of the voltages V.sub.pk and V.sub.FB.

(30) In any case, it is possible to define a potential difference V.sub.GB that makes it possible to comply with this equation V.sub.pk.sub.Dip=|V.sub.GBV.sub.FB| or at the very least to get close to it.

(31) It will be noted that there may be an attenuation along the conductive line, expressed in dB/mm. The loss in terms of V.sub.pk on a substrate with high resistivity along a line of a few millimeters may thus be of a factor of 2.

(32) In such a case, it is possible, instead of considering a single value Vpk as above, to distinguish the terminals V.sub.pk_in and V.sub.pk_out:
V.sub.pk_in={square root over (2Z.sub.REFP.sub.in)}
V.sub.pk_out={square root over (2Z.sub.REFP.sub.out)}

(33) In particular, when consideration is given to a curve of HD2 of Pout as a function of H1 of Pout, and the trough P.sub.Dip is located at a certain output power point (H1 of Pout), the value of Vpk to be considered is Vpk_out.

(34) It will be noted in the case of FIG. 3 that the radiofrequency circuit is formed on an SOI substrate of trap rich type that is of poor quality, that is to say for which the polycrystalline silicon layer has partially recrystallized. The trough phenomenon is attributed to the fact that the behavior of the substrate is then similar to that of a silicon substrate with high resistivity.

(35) The inventors have therefore exploited the abovementioned phenomenon so as to minimize harmonic distortion and/or intermodulation distortion, as they are able to design and/or adjust the position of the trough to the desired operating power, so as to minimize the distortion or intermodulation terms that are generated.

(36) Thus, as is seen in FIG. 5, if the straight line A, which corresponds to a first substrate, not having the abovementioned trough, is compared with the curve B of a second substrate having the trough, it is observed that, for a given power of the input signal, the level of generation of the second harmonic reaches a ceiling that is below the value reached with the first curve.

(37) In the example illustrated, for a power P.sub.in of the input signal corresponding to 20 dBm, the level of generation of the second harmonic is 80 dBm for the first substrate, and 95 dBm at most for the second substrate. Thus, there is a gain of around 15 dBm with the second substrate if the level of the first harmonic of the input signal is within the range corresponding to the trough.

(38) Adjusting the potential difference V.sub.GB makes it possible to move the trough of the distortion curve into a range that corresponds to the power of the input signal.

(39) FIG. 6 shows curves of the level of generation of the second harmonic (in dBm) as a function of the level of the first harmonic of the output signal (in dBm), for various applied potential differences V.sub.GB.

(40) As is able to be seen in this figure, varying V.sub.GB makes it possible to significantly move the trough.

(41) According to one embodiment, the potential difference V.sub.GB is fixed.

(42) According to another embodiment, the potential difference V.sub.GB is adjusted dynamically, during operation of the radiofrequency circuit, so as to ensure that the trough of the distortion curve always corresponds to a given operating power of the radiofrequency circuit; the power may be, in particular, the maximum power of the input signal, or another power value chosen by a person skilled in the art.

(43) To this end, the radiofrequency device comprises a loop for servo-controlling the potential difference V.sub.GB to the power Pin of the input signal.

(44) It will be noted that the design of the semiconductor substrate and of the electrically insulating layer may make it possible to adjust the flat band voltage V.sub.FB. Thus, for example, the voltage V.sub.FB may be modified by modifying the quantity of electric charges in the electrically insulating layer. The voltage V.sub.FB may also be modified by doping the semiconductor substrate, but this solution is less preferable, in particular, in the case of a substrate with high resistivity given the fact that the dopants may lead to a reduction in the electrical resistivity of the semiconductor substrate and therefore to an amplification of its non-linear nature.

(45) Moreover, measurements have demonstrated the effect of the temperature of the radiofrequency circuit on the appearance of the trough in the distortion curve.

(46) FIGS. 7A and 7B thus show curves of the level of generation of the second harmonic as a function of the level of the first harmonic for a trap rich SOI substrate having, under the electrically insulating layer, a polycrystalline silicon layer with a thickness of 0.4 m (FIG. 7A) and with a thickness of 1.7 m (FIG. 7B), at temperatures of 60 and 90 C.

(47) The curves are substantially linear for a temperature of 60 C.

(48) For a temperature of 90 C., a trough is observed in the curve of FIG. 7A, whereas that of FIG. 7B remains substantially linear.

(49) FIG. 7A therefore demonstrates an effect of the temperature on the appearance of a trough in the level of generation of the second harmonic. This effect appears to be explained by the fact that the temperature generates charge carriers that will fill the traps corresponding to the grain boundaries of the polycrystalline silicon whose thickness is small. The result of this is that, for a high-power Pin, the trap rich SOI substrate behaves like a substrate with high resistivity, and therefore becomes sensitive to the flat band phenomenon.

(50) The potential difference V.sub.GB may therefore advantageously be defined at the operating temperature envisaged for the radiofrequency circuit.

(51) It is also possible to exploit this observation to control the movement of the trough depending on the temperature.

(52) Thus, by virtue of a temperature sensor that makes it possible to sense the temperature of the radiofrequency circuit or of its immediate surroundings, it is possible to take into account the measured temperature so as to control the potential difference V.sub.GB, in order to ensure that the trough is always within the operating power range of the radiofrequency circuit (for example, the maximum power of the signal).

(53) Such a temperature sensor may, for example, be of the type described in the article by Deng F, He Y, Li B, et al. Design of an Embedded CMOS Temperature Sensor for Passive RFID Tag Chips. Passaro VMN, ed. Sensors (Basle, Switzerland). 2015; 15(5):11442-11453. doi:10.3390/s150511442.

(54) In practice, the present disclosure may be implemented as follows.

(55) In a manner known per se, the radiofrequency circuit is designed, this generally involving designing the semiconductor substrate and the electrically insulating layer on which it is formed.

(56) From this design, it is possible to derive the flat band voltage of the metal-insulator-semiconductor structure.

(57) Where appropriate, it is possible to choose to modify the flat band voltage, this for example, involving modifying the quantity of charges in the electrically insulating layer.

(58) Moreover, with knowledge of the targeted power Pin and the associated peak voltage V.sub.pk, it is possible to derive, from the equation V.sub.pk=|V.sub.GBV.sub.FB|, the value of the potential difference V.sub.GB to be applied between the radiofrequency circuit and the semiconductor substrate.

(59) This potential difference may be applied in various ways. In general, it requires a voltage generator, advantageously coupled to a module for controlling the voltage, which module is configured to adjust the voltage of the generator depending on the operating power of the radiofrequency circuit. The voltage generator is separate from the device for powering the radiofrequency circuit. Moreover, a contact has to be connected electrically to the semiconductor substrate, in order to apply a reference potential to the substrate.

(60) FIG. 8A relates to an SOI comprising a silicon substrate with high resistivity, as in FIG. 1A, whose reference signs are taken up by FIG. 8A. In this case, a back gate layer 4, made of an electrically conductive material and situated on the back face of the substrate 1 (i.e., on the side opposite the dielectric layer 2) is grounded, as are the two lateral conductive lines. The central conductive line, for its part, is set to the potential V.sub.GB. As an alternative, the central conductive line could be grounded, and the other electrodes (lateral conductive lines and back gate layer) set to the potential V.sub.GB.

(61) FIG. 8B relates to a trap rich SOI comprising a polycrystalline silicon layer under the electrically insulating layer, as in FIG. 1B, whose reference signs are taken up by FIG. 8B. In this case, an electrically conductive back gate layer 4 situated on the back face of the substrate 1 (i.e., on the side opposite the dielectric layer 2 is grounded, as are the two lateral conductive lines. The central conductive line, for its part, is set to the potential V.sub.GB. As an alternative, the central conductive line could be grounded, and the other electrodes (lateral conductive lines and back gate layer) set to the potential V.sub.GB.

(62) FIG. 8C relates to a trap rich double BOX SOI comprising a polycrystalline silicon layer between two electrically insulating layers, as in FIG. 1C, whose reference signs are taken up by FIG. 8C. In this case, an electrically conductive back gate layer 4 situated on the back face of the substrate 1 (i.e., on the side opposite the dielectric layer 2b) is grounded, as are the two lateral conductive lines. The central conductive line, for its part, is set to the potential V.sub.GB. As an alternative, the central conductive line could be grounded, and the other electrodes (lateral conductive lines and back gate layer) set to the potential V.sub.GB.

(63) It will be noted that it is not essential to provide a back gate layer on the back face of the semiconductor substrate in order to make it possible to apply the potential difference V.sub.GB. A reference potential may be set in the semiconductor substrate by any other means known to a person skilled in the art, such as a via extending from the front face through the electrically insulating layer as far as into the semiconductor substrate.