Formation of a III-N semiconductor structure

Abstract

According to an aspect of the present disclosure, there is provided a III-N semiconductor structure comprising: a semiconductor-on-insulator substrate; a buffer structure comprising a superlattice including at least a first superlattice block and a second superlattice block formed on the first superlattice block, the first superlattice block including a repetitive sequence of first superlattice units, each first superlattice unit including a stack of layers of AlGaN, wherein adjacent layers of the stack have different aluminum content, the second superlattice block including a repetitive sequence of second superlattice units, each second superlattice unit including a stack of layers of AlGaN, wherein adjacent layers of the stack have different aluminum content, wherein an average aluminum content of the second superlattice block is greater than an average aluminum content of the first superlattice block; and a III-N semiconductor channel layer arranged on the buffer structure.

Claims

1. A III-N semiconductor structure comprising: a semiconductor-on-insulator substrate; a buffer structure comprising a superlattice including at least a first superlattice block, a second superlattice block formed on the first superlattice block, and an upper superlattice block formed above the second superlattice block, wherein: the first superlattice block includes a repetitive sequence of first superlattice units, each first superlattice unit including a stack of layers of AlGaN, wherein adjacent layers of the stack of layers have different aluminum content, the second superlattice block includes a repetitive sequence of second superlattice units, each second superlattice unit including a stack of layers of AlGaN, wherein adjacent layers of the stack of layers have different aluminum content, an average aluminum content of the second superlattice block is greater than an average aluminum content of the first superlattice block, and the aluminum content of the upper superlattice block is less than the average aluminum content of the second superlattice block; and a III-N semiconductor channel layer arranged on the buffer structure.

2. The semiconductor structure according to claim 1, wherein the superlattice of the buffer structure includes a plurality of superlattice blocks and wherein the first and the second superlattice blocks form an adjacent pair of superlattice blocks of the superlattice.

3. The semiconductor structure according to claim 1, wherein the superlattice includes a lower superlattice block formed below the first superlattice block and having an average aluminum content which is greater than the average aluminum content of the first superlattice block.

4. The semiconductor structure according to claim 1, wherein the superlattice includes a third superlattice block formed on the second superlattice block and a fourth superlattice block formed on the third superlattice block, wherein an average aluminum content of the fourth superlattice block is greater than an average aluminum content of the third superlattice block, and wherein the average aluminum content of the third superlattice block is smaller than the average aluminum content of the second superlattice block.

5. The semiconductor structure according to claim 1, wherein the semiconductor-on-insulator substrate includes a bottom wafer, a top semiconductor layer and an insulator layer intermediate the bottom wafer and the top semiconductor layer, and wherein a combined thickness of the buffer structure and the III-N semiconductor channel layer is greater than a thickness of top semiconductor layer.

6. The semiconductor structure according to claim 1, wherein the buffer structure includes an AlN nucleation layer formed on the semiconductor-on-insulator substrate.

7. The semiconductor structure according to claim 6, wherein the buffer structure further comprises a lower transition layer of (Al)GaN, wherein the superlattice is formed on the lower transition layer.

8. The semiconductor structure according to claim 1, wherein the buffer structure further comprises an upper transition layer of (Al)GaN formed on the superlattice.

9. A method for forming a III-N semiconductor structure, the method comprising: forming, on a semiconductor-on-insulator substrate, a buffer structure, wherein forming the buffer structure comprises: forming a superlattice including at least a first superlattice block, a second superlattice block on the first superlattice block, and an upper superlattice block above the second superlattice block, wherein: the first superlattice block is formed by epitaxially growing a repetitive sequence of first superlattice units, each first superlattice unit including a stack of layers of AlGaN, wherein adjacent layers of the stack of layers have different aluminum content, the second superlattice block is formed by epitaxially growing a repetitive sequence of second superlattice units, each second superlattice unit including a stack of layers of AlGaN, wherein adjacent layers of the stack of layers have different aluminum content, an average aluminum content of the second superlattice block is greater than an average aluminum content of the first superlattice block, and the aluminum content of the upper superlattice block is less than the average aluminum content of the second superlattice block; and epitaxially growing a III-N semiconductor channel layer on the buffer structure.

10. The method according to claim 9, wherein forming the superlattice includes forming a plurality of superlattice blocks and wherein the first and the second superlattice blocks form an adjacent pair of superlattice blocks of the superlattice.

11. The method according to claim 9, wherein the semiconductor-on-insulator substrate includes a bottom wafer, a top semiconductor layer and an insulator layer intermediate the bottom wafer and the top semiconductor layer, and wherein the buffer structure and the III-N semiconductor channel layer are formed with a combined thickness greater than a thickness of top semiconductor layer.

12. The method according to claim 9, wherein the second superlattice block is grown such that a temporal rate of change of an in situ curvature of the second superlattice block is less than or equal to zero.

13. The method according to claim 9, wherein the superlattice is grown such that an at least partial strain relaxation occurs between at least one adjacent pair of layers of the superlattice.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) The above, as well as additional, features will be better understood through the following illustrative and non-limiting detailed description of example embodiments, with reference to the appended drawings.

(2) FIG. 1 schematically shows a III-N semiconductor structure, according to an example embodiment.

(3) FIG. 2 shows a composition of superlattice units, accordingly to an example embodiment.

(4) FIG. 3 is a flow chart of a method for forming a III-N semiconductor structure, according to an example embodiment.

(5) FIG. 4a is a III-N semiconductor structure, according to an example embodiment.

(6) FIG. 4b shows an in situ wafer curvature and a post-epi wafer warp, according to an example embodiment.

(7) FIG. 4c shows the pre- and post-epi wafer warp measured along two orthogonal directions along the wafer.

(8) FIG. 5a is a III-N semiconductor structure, according to an example embodiment.

(9) FIG. 5b shows an in situ wafer curvature, according to an example embodiment.

(10) FIG. 5c shows the pre- and post-epi wafer warp measured along two orthogonal directions along the wafer.

(11) FIG. 6a is a III-N semiconductor structure, according to an example embodiment.

(12) FIG. 6b shows an in situ wafer curvature, according to an example embodiment.

(13) FIG. 6c shows the pre- and post-epi wafer warp measured along two orthogonal directions along the wafer.

(14) FIG. 7a is a III-N semiconductor structure, according to an example embodiment.

(15) FIG. 7b shows an in situ wafer curvature, according to an example embodiment.

(16) FIG. 7c shows the pre- and post-epi wafer warp measured along two orthogonal directions along the wafer.

(17) All the figures are schematic, not necessarily to scale, and generally only show parts which are necessary to elucidate example embodiments, wherein other parts may be omitted or merely suggested.

DETAILED DESCRIPTION

(18) Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. That which is encompassed by the claims may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example. Furthermore, like numbers refer to the same or similar elements or components throughout.

(19) A III-N semiconductor structure and a method of forming a III-N semiconductor structure will now be described with reference to FIGS. 1 through 3.

(20) FIG. 1 shows in a schematic cross section a semiconductor structure comprising a stack of layers. The stacking direction of the layers is indicated by Z and may in the following also be referred to as a vertical direction, a bottom-up direction, or a normal direction to the SOI substrate. It should be noted that the relative dimensions of the shown elements, in particular the relative thickness of the layers, is merely schematic and may, for the purpose of illustrational clarity, differ from a physical structure.

(21) The semiconductor structure includes in the bottom-up direction a semiconductor-on-insulator substrate 100 (hereinafter abbreviated SOI substrate 100), a buffer structure 200 and a III-N semiconductor channel layer 300.

(22) The SOI substrate 100 includes a bottom wafer 110, a top semiconductor layer 130 and an insulator layer 120 intermediate the bottom wafer 110 and the top semiconductor layer 130. The SOI substrate 100 may be of any conventional type such as a monocrystalline Si, Ge, SiGe or SiC top layer 130 formed on an oxide insulator layer 120 and supported by a bottom handling wafer 110 of for instance Si, Mo or AlN. The top semiconductor layer 130 may present a {111} plane as an upper main surface. The SOI substrate 100 may be fabricated in a conventional manner such as a layer transfer process where a top semiconductor layer is bonded to a bottom wafer 110 by a bonding oxide layer 120 and subsequently cut or grinded to form the final thinned top semiconductor layer 130

(23) The buffer structure 200 is formed on the SOI substrate 100. The buffer structure 200 includes in a bottom-up direction an AlN nucleation layer 210, a lower transition layer 220, a superlattice 230 and an upper transition layer 240. The lower transition layer 220 and the upper transition layer 240 are both optional layers and may be omitted.

(24) The AlN nucleation layer 210 (hereinafter the nucleation layer 210) is formed on and in contact with the upper surface of the SOI-substrate 100 (step 402 of the flow chart 400 of FIG. 3). The nucleation layer 210 may be epitaxially grown by vapor phase deposition, for instance MOCVD using conventional Al precursors such as trimethylaluminum (TMAl). However, some other conventional type of vapor deposition process suitable for epitaxial growth of an AlN nucleation layer is also possible. The nucleation layer 210 may be formed with a thickness of 250 nm or less, including at least 50 nm. The nucleation layer 210 may generally be formed with a thickness for reaching a sufficient crystalline quality for the growth of following layers. If a Si-based top semiconductor layer 130 is present, the nucleation layer 210 may also be formed with a thickness which is sufficient for counteracting diffusion of Ga to react with the top semiconductor layer 130. The nucleation layer 210 may be formed to present a C-plane as an upper main surface.

(25) The lower transition layer 220 is formed on and in contact with the upper main surface of the nucleation layer 210 (step 404 of FIG. 3). The lower transition layer 220 may be formed as a single layer with a uniform composition. For instance, the lower transition layer 220 may be an (Al)GaN layer having an Al content in the range of 20% to 90%. Alternatively, the lower transition layer 220 may be formed as a composite layer including two or more sub-layers of (Al)GaN with different compositions. The lower transition layer 220 may be formed to present a C-plane as an upper main surface.

(26) The lower transition layer 220 may be epitaxially grown by vapor phase deposition, for instance MOCVD using conventional group III element precursors such as trimethylgallium (TMGa), triethylgallium (TEGa), and TMAl, or some other conventional type of vapor deposition process suitable for epitaxial growth of (Al)GaN, such as molecular beam epitaxy (MBE), physical vapor deposition (PVD) or hydride vapor phase epitaxy (HVPE). The lower transition layer 220 may be formed with a (total) thickness of 200 nm or less.

(27) A superlattice 230 is formed by a number of superlattice blocks stacked on top of each other (step 406 of FIG. 3). In FIG. 1 the superlattice blocks include a first superlattice block 231 and second superlattice block 232 formed on top of the first superlattice block 231. As shown, the superlattice 230 may include further superlattice blocks such as at least one lower superlattice block 230L and/or at least one upper superlattice block 230U. Accordingly, forming of the superlattice 230 may include forming at least the first superlattice block 231 (step 406-1) and the second superlattice block 232 (step 406-2), but may optionally include forming further lower and/or upper superlattice blocks (represented by step 406-L and 406-U of FIG. 3).

(28) Each superlattice block of the superlattice may be formed by a repetition of identical and consecutively formed superlattice units. As indicated in FIG. 1 for the first superlattice block 231, the superlattice block 231 consists of a stack of a number m of superlattice units 231-1, 231-2, . . . 231-m, wherein m is 2 or greater. The second superlattice block 232 is formed on the upper main surface of the first superlattice block 231. The superlattice block 232 consists of a stack of a number n of superlattice units 232-1, 232-2, . . . 232-n, wherein n is 2 or greater. The number of superlattice units may be the same or different among the superlattice blocks. For instance, the number n of superlattice units of the second superlattice block 232 may be equal to m or different from m.

(29) As shown in FIG. 2, each superlattice unit of the first superlattice 231 is formed of a stack or laminate of j layers (wherein j is 2 or greater) of AlGaN, wherein each of the layers of the stack have an aluminum content which is different from an aluminum content of an adjacent layer of the stack (i.e. x[i1]xix[i+1], for 2ij1). Optionally, each of the layers of the stack may have an aluminum content which is different from an aluminum content of each other layer of the stack (i.e. x1x2 . . . xj). The thicknesses D1i of the i.sup.th layers of each superlattice unit 231-1, 231-2, . . . , 231-m may as indicated in FIG. 2 be identical. Thus, the superlattice units 231-1, 231-2, . . . , 231-m may have an identical/a same composition.

(30) Each superlattice unit of the second superlattice 232 is formed of a stack or laminate of k layers (wherein k is 2 or greater) of AlGaN, wherein each of the layers of the stack have an aluminum content which is different from an aluminum content of an adjacent layer of the stack (i.e. y[i1]yiy[i+1], for 2ik1). Optionally, each of the layers of the stack may have an aluminum content which is different from an aluminum content of each other layer of the stack (i.e. y1y2 . . . yk). The thicknesses D2i of the i.sup.th layers of each superlattice unit 232-1, 232-2, . . . , 232-n may as shown in FIG. 2 be identical. Thus, the superlattice units 232-1, 232-2, . . . , 232-n may have an identical/a same composition.

(31) Each layer of the superlattice units of the superlattice blocks 231, 232 may be epitaxially grown using any of the techniques discussed on connection with the lower transition layer 220. Each layer of the superlattice units of the superlattice blocks 231, 232 may be formed with a thickness less than 100 nm.

(32) The layers of the superlattice blocks 231, 232 may be formed as pseudomorphic layers (i.e. by forming each layer with a thickness less than the critical layer thickness). However, the superlattice 230 may also be formed to include one or more partially or fully strain relaxed layer (i.e. by forming the layer with a thickness greater than the critical layer thickness).

(33) Within the above bounds, the compositions of the first and the second superlattice blocks 231, 232 are such that an average aluminum content of the second superlattice block 232 is greater than an average aluminum content of the first superlattice block 231. The average aluminum content of the second superlattice block 232 may be at least 1% greater than the average aluminum content of the first superlattice block 231. In other words the AL % of the second superlattice block 232 may be 1 percentage unit greater than the AL % of the first superlattice block 231.

(34) The one or more further superlattice blocks 230L, 230U of the superlattice 230 generally presents a corresponding composition as the first and the second superlattice blocks 231, 232. A lower superlattice block 230L (if present) may present an average aluminum content which is greater than the average aluminum content of the first superlattice block 231. Meanwhile, an upper superlattice block 230U (if present) may present an average aluminum content which is less than the average aluminum content of the second superlattice block 232.

(35) According to a further variation, the superlattice 230 may include a third superlattice block formed on the second superlattice block 232 and a fourth superlattice block formed on the third superlattice block. The third and fourth superlattice block may form a second non-compressive stress inducing pair, on top of the first non-compressive stress inducing pair formed by the first and the second superlattice blocks 231, 232. Thus, the average aluminum content of the fourth superlattice block may be greater than the average aluminum content of the third superlattice block. The average aluminum content of the third superlattice block may be smaller than the average aluminum content of the second superlattice block. The superlattice 230 may include even further non-compressive stress inducing pairs, such as a third pair. The third pair may include a fifth superlattice block formed on the fourth superlattice block and a sixth superlattice block formed on the fifth superlattice block, wherein an average aluminum content of the sixth superlattice block is greater than an average aluminum content of the fifth superlattice block and wherein the average aluminum content of the fifth superlattice block is smaller than the average aluminum content of the fourth superlattice block. It is contemplated that this scheme may be even further extended to include four, five or more of such non-compressive stress inducing pairs.

(36) The upper transition layer 240 is formed on and in contact with the upper main surface of the superlattice 230 (step 408 of FIG. 3). The upper transition layer 240 may be formed as a single layer with a uniform composition. For instance, the upper transition layer 240 may be an (Al)GaN layer having an Al content in the range of 0% to 20%. Alternatively, the upper transition layer 240 may be formed as a composite layer including two or more sub-layers of (Al)GaN with different compositions. The upper transition layer 240 may also include one or more layers of (InAlGa)N. The upper transition layer 240 may be formed with a (total) thickness of 1500 nm or less. The upper transition layer 240 may be formed to present a C-plane as an upper main surface. The upper transition layer 240 may be epitaxially grown using any of the techniques discussed on connection with the lower transition layer 220.

(37) The III-N semiconductor channel layer 300 (hereinafter the channel layer 300) may as shown be formed (step 410 of FIG. 3) on and in contact with the upper main surface of the buffer structure 200 (formed either by the upper main surface of the upper transition layer 240 or the upper main surface of the superlattice 230).

(38) The channel layer 300 may be formed of B.sub.xIn.sub.yAl.sub.zGa.sub.wN (0x1, 0y1; 0z1, 0w1, and x+y+z+w=1). The channel layer 300 may be epitaxially grown by MOCVD using conventional group III element precursors, such as of TMIn and triethylboron (TEB), TMGa, TEGa, and TMAl, or by other conventional vapor phase deposition techniques. The channel layer may be grown to a total thickness in the range of 0.1 to 1 m.

(39) Subsequent to forming the channel layer 300, further layers and structures may be formed on the semiconductor structure in order to form a complete device. For instance, an B.sub.aIn.sub.bAl.sub.cGa.sub.dN layer (0a1, 0b1, 0c1, 0d1 and a+b+c+d=1) electron supply layer may be formed on the channel layer 300. An AlN spacer layer may be formed between the channel layer 300 and the electron supply layer. A cap layer, such as a GaN layer or Si.sub.3N.sub.4 layer, may be formed on top of the electron supply layer. The spacer layer, the electron supply layer and the cap layer may be formed using a same deposition technique as for the channel layer 300. Source, drain and gate electrodes may be formed on the electron supply layer (or the cap layer if present) in a conventional manner.

(40) In addition to the above discussion concerning materials and composition of the layers of the buffer structure 200, it is possible to form the layers as layers doped by impurity atoms. For example, one or more of the lower transition layer 220, layers of the superlattice 230 and/or the upper transition layer 220 may be doped to a concentration of 110.sup.18 (atom/cm.sup.3) or greater. This may improve breakdown voltage of the buffer structure 200. The dopants/impurity atoms may be one or more species selected from the group consisting of C atoms, Fe atoms, Mn atoms, Mg atoms, V atoms, Cr atoms, Be atoms and B atoms. Dopants may be introduced by adding a source of the intended dopant species to the growth chamber during the epitaxial growth of the layer to be doped. For instance, carbon doping may be achieved by adding a carbon-source to the growth chamber, such as methane (CH.sub.4), ethylene (C.sub.2H.sub.4), acetylene (C.sub.2H.sub.2), propane (C.sub.3H.sub.8) or iso-butane (i-C.sub.4H.sub.10).

(41) FIG. 4a schematically shows a III-N semiconductor structure according to a first example. FIG. 4b shows the in situ wafer curvature and the post-epi wafer warp. The sharp spikes and short-range high frequency oscillations of the curves are artefacts of the measurement system. FIG. 4c shows the pre- and post-epi wafer warp measured along two orthogonal directions along the wafer.

(42) The structure comprises: a SOI substrate 100 of 1.5 m thick Si {111} bonded to a 1071 m thick Si {100} handling wafer by a 1 m thick oxide layer, a 200 nm thick AlN nucleation layer 210, a 50 nm Al.sub.0.75GaN lower transition layer 220, a superlattice 230 of: a 1.65 m thick first superlattice block 231 formed by 50 repetitions of a superlattice unit of a [5 nm AlN/28 nm Al.sub.0.15GaN] bilayer (corresponding to an average aluminum content AL %=28%), and a 1.5 m thick second superlattice block 232 formed by 40 repetitions of a superlattice unit of a [10 nm AlN/28 nm Al.sub.0.3GaN] bilayer (corresponding to an average aluminum content AL %=48%), a 1 m thick carbon-doped GaN upper transition layer 240, and a 300 nm GaN channel layer 300.

(43) As may be seen, by introducing a superlattice block with a higher average aluminum content AL % on top of another superlattice block, tensile stress can be introduced which lowers down the in situ curvature as well as the ex situ wafer warp (measured as peak-to-peak difference). As may be seen in the chart, the second superlattice block 232 is grown such that a temporal rate of change of the in situ curvature is less than 0. This is due to the average aluminum content of the second block 232 being greater than that of the first block 231. The chart also schematically indicates the in situ shape of the structure when the in situ curvature is positive (convex shape) and when the in situ curvature is negative (concave shape). The total buffer thickness is 4.9 m. As will be shown in the following, it may otherwise in alternative schemes be challenging to grow >4 m thickness III-N structures without reaching the substrate plastic deformation limit.

(44) FIG. 5a schematically shows a III-N semiconductor structure according to a second example. FIG. 5b shows the in situ wafer curvature. FIG. 5c shows the pre- and post-epi wafer warp measured along two orthogonal directions along the wafer. The structure comprises: a SOI substrate 100 of 1.5 m thick Si {111} bonded to a 1071 m thick Si {100} handling wafer by a 1 m thick oxide layer, a 200 nm thick AlN nucleation layer 210, a 50 nm Al.sub.0.75GaN lower transition layer 220, a superlattice 230 of: a 1.65 m thick first superlattice block 231 formed by 50 repetitions of a superlattice unit of a [5 nm AlN/28 nm Al.sub.0.15GaN] bilayer (corresponding to an average aluminum content AL %=28%), and a 0.5 m thick second superlattice block 232 formed by 15 repetitions of a superlattice unit of a [7 nm AlN/28 nm Al.sub.0.15GaN] bilayer (corresponding to an average aluminum content AL %=32%), a 1.65 m thick third superlattice block 233 formed by 50 repetitions of a superlattice unit of a [4 nm AlN/30 nm Al.sub.0.1GaN] bilayer (corresponding to an average aluminum content AL %=20.6%), a 0.5 m thick fourth superlattice block 234 formed by 15 repetitions of a superlattice unit of a [5 nm AlN/30 nm Al.sub.0.1GaN] bilayer (corresponding to an average aluminum content AL %=22.9%), a 1 m thick carbon-doped GaN upper transition layer 240, and a 400 nm GaN channel layer 300.

(45) Thus, there are in total 4 superlattice blocks in the structure. By alternating the average aluminum content Al % in each superlattice block both compressive strain and tensile strain can be introduced which consequently increase or decrease the in situ wafer curvature at a relatively low value when growing a rather thick SL structure of 4.3 um. The resulting max in situ curvature is then still below the limit for wafer plastic deformation for this structure of 6 m. The final wafer warp is at a much lower level compared with reference 1 which is only 3 m in thickness.

(46) FIGS. 6a, 6b, and 6c show a first comparative example of transferring a buffer that is designed for Si bulk substrate directly onto SOI substrate. FIG. 6a schematically shows a III-N semiconductor structure, FIG. 6b shows the in situ wafer curvature, and FIG. 6c shows the pre- and post-epi wafer warp measured along two orthogonal directions along the wafer. The SOI substrate 610 was of a same configuration as in the previous examples. The structure further comprised: a 200 nm AlN nucleation layer 620, a 40 nm Al.sub.0.3GaN lower transition layer 630, a superlattice 640 formed by 50 repetitions of a superlattice unit of a [5 nm AlN/28 nm Al.sub.0.1GaN] bilayer, a 1 m carbon-doped GaN channel layer 650, a 300 nm GaN layer 660, an 18 nm Al.sub.0.175GaN layer 670 and a 70 nm p-doped GaN layer 680.

(47) As shown in FIGS. 6a, 6b, and 6c the total stack is 3.3 m. In situ wafer curvature and ex situ wafer warp are summarized for 2 runs. In each run (#1 and #2), one SOI and one Si reference substrate were loaded into the reactor at the same time. One can see that the in situ wafer curvature of SOI substrates increase significantly compared with Si reference substrate. It reached a very high value of 80 km.sup.1 for SOI substrates when the substrate deformed plastically (i.e. cracked). The ex situ wafer warp of SOI substrate is also much higher compared to the Si substrates.

(48) FIGS. 7a, 7b, and 7c show a second comparative example indicating the challenges to grow thicker Epi layers using a conventional buffer scheme. In this example, a step-graded buffer of only 2.8 m was grown on SOI and Si substrates in the same run. FIG. 7a schematically shows a III-N semiconductor structure, FIG. 7b shows the in situ wafer curvature, and FIG. 7c shows the pre- and post-epi wafer warp measured along two orthogonal directions along the wafer. The SOI substrate 710 was of a same configuration as in the previous examples. The structure further comprised: a 200 nm AlN layer 720, a 300 nm Al.sub.0.44GaN layer 730, a 2 m C-doped Al.sub.0.08GaN layer 740, a 300 nm GaN layer 750, a 12.5 nm Al.sub.0.25GaN layer 760, and a 70 nm p-doped GaN layer 770. In the chart of FIG. 7b, the pocket denotes the position of the wafer on the carrier during the epitaxial process. Again, the in-situ curvature of SOI substrate is higher than the Si substrates. Following the same buffer scheme but simply increasing the layer thickness, it will soon inevitably reach the in situ curvature limit for substrate plastic deformation. As the two standard (STD) Si have very similar curves, the table only shows a single warp value for STD Si.

(49) In the above, the concepts have mainly been described with reference to a limited number of examples. However, as is readily appreciated by a person skilled in the art, other examples than the ones disclosed above are equally possible within the scope of the disclosure, as defined by the appended claims.

(50) While some embodiments have been illustrated and described in detail in the appended drawings and the foregoing description, such illustration and description are to be considered illustrative and not restrictive. Other variations to the disclosed embodiments can be understood and effected in practicing the claims, from a study of the drawings, the disclosure, and the appended claims. The mere fact that certain measures or features are recited in mutually different dependent claims does not indicate that a combination of these measures or features cannot be used. Any reference signs in the claims should not be construed as limiting the scope.