Method for precoding to mitigate nonlinear distortions and precoder for performing the same

Abstract

A method for precoding to mitigate nonlinear distortions and a precoder for performing the same are disclosed. The precoder for mitigating distortions of a communication signal may include a filter configured to generate a filtering signal based on a third signal and filter coefficients corresponding to a selected signal generated based on a first signal, a second signal, and the third signal, and a modulo operator configured to generate the third signal by performing a modulo operation on the second signal, wherein the second signal is generated based on the first signal and the filtering signal.

Claims

1. A precoder for mitigating distortions of a communication signal, the precoder implemented at a transmitter and comprising: a filter configured to generate a filtering signal based on a third signal and filter coefficients corresponding to a selected signal generated based on a first signal, a second signal, and the third signal, wherein the filter coefficients have nonlinear characteristics and are selected such that the filter compensates for nonlinear distortions; and a modulo operator configured to generate the third signal by performing a modulo operation on the second signal, wherein the second signal is generated based on the first signal and the filtering signal.

2. The precoder of claim 1, wherein the filter comprises: a level detector configured to generate the selected signal; a plurality of delay elements configured to output delayed signals by delaying the third signal; a plurality of selectors configured to select and output the filter coefficients based on the selected signal; a plurality of multipliers configured to multiply the third signal and the delayed signals by the filter coefficients; and an adder configured to output the filtering signal by adding multiplication results obtained by the plurality of multipliers.

3. The precoder of claim 2, wherein the level detector comprises: an adder configured to generate a level signal based on the first to third signals; and a comparator configured to output the selected signal based on the level signal and a plurality of comparison signals.

4. The precoder of claim 2, wherein the plurality of delay elements comprises: a first delay element configured to output a first delayed signal by delaying the third signal; and a second delay element configured to output a second delayed signal by delaying the first delayed signal.

5. The precoder of claim 4, wherein the plurality of selectors comprises: a first selector configured to output a first filter coefficient corresponding to, the third signal; a second selector configured to output a second filter coefficient corresponding to the first delayed signal; and a third selector configured to output a third filter coefficient corresponding to the second delayed signal.

6. A precoder for mitigating distortions of a communication signal, the precoder implemented at a transmitter and comprising: a filter configured to generate a filtering signal based on a third signal and filter coefficients respectively corresponding to a plurality of selected signals generated based on a first signal, a second signal, and the third signal, wherein the filter coefficients have nonlinear characteristics and are selected such that the filter compensates for nonlinear distortions; and a modulo operator configured to generate the third signal by performing a modulo operation on the second signal, wherein the second signal is generated based on the first signal and the filtering signal.

7. The precoder of claim 6, wherein the filter comprises: a level detector configured to generate the plurality of selected signals; a plurality of delay elements configured to output delayed signals by delaying the third signal; a plurality of selectors configured to select and output the filter coefficients based on the plurality of selected signals respectively; a plurality of multipliers configured to multiply the third signal and the delayed signals by the filter coefficients; and an adder configured to output the filtering signal by adding multiplication results obtained by the plurality of multipliers.

8. The precoder of claim 7, wherein the level detector comprises: an adder configured to generate a level signal based on the first to third signals; a plurality of delay elements configured to output delayed signals by delaying the level signal; and a plurality of comparators configured to output the plurality of selected signals based on the level signal and the delayed level signals respectively.

9. A method for precoding to mitigate distortions of a communication signal, the method performed at a transmitter and comprising: generating a filtering based on a third signal and filter coefficients selected based on a selected signal generated based on a first signal, a second signal, and the third signal, wherein the filter coefficients have nonlinear characteristics and are selected so as to compensate for nonlinear distortions; and generating the third signal by performing a modulo operation on the second signal, wherein the second signal is generated based on the first signal and the filtering signal.

10. The method of claim 9, wherein the generating of the filtering signal comprises: generating the selected signal; outputting delayed signals by delaying the third signal; selecting and, outputting the filter coefficients based on the selected signal; multiplying the third signal and the delayed signals by the filter coefficients; and outputting the filtering signal by adding multiplication results.

11. The method of claim 10, wherein the generating of the selected signal comprises: generating a level signal based on the first to third signals; and outputting the selected signal based on the level signal and a plurality of comparison signals.

12. The method of claim 10, wherein the outputting by delaying comprises: outputting a first delayed signal by delaying the third signal; and outputting a second delayed signal by delaying the first delayed signal.

13. The method of claim 12, wherein the selecting and outputting of the filter coefficients comprises: outputting a first filter coefficient corresponding to the third signal; outputting a second filter coefficient corresponding to the first delayed signal; and outputting a third filter coefficient corresponding to the second delayed signal.

14. The method of claim 9, wherein the outputting of the filtering signal comprises: generating a plurality of selected signals; outputting the delayed signals by delaying the third signal; selecting and outputting the filter coefficients based on the plurality of selected signals respectively; multiplying the third signal and the delayed signal by the filter coefficients; and outputting the filtering signal by adding multiplication results.

15. The method of claim 14, wherein the generating of the plurality of selected signals comprises: generating a level signal based on the first to third signals; outputting delayed level signals by delaying the level signal; and outputting the plurality of selected signals based on the level signal and the delayed level signals respectively.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) These and/or other aspects, features, and advantages of the invention will become apparent and more readily appreciated from the following description of example embodiments, taken in conjunction with the accompanying drawings of which:

(2) FIG. 1 illustrates a communication system according to an example embodiment;

(3) FIG. 2 illustrates an example of the precoder of FIG. 1;

(4) FIG. 3 illustrates the level detector of FIG. 2;

(5) FIG. 4 illustrates another example of the precoder of FIG. 1;

(6) FIG. 5 illustrates the level detector of FIG. 4; and

(7) FIGS. 6A and 6B illustrates a level signal of a level detector and a comparison signal of a level detector respectively.

DETAILED DESCRIPTION

(8) The following detailed structural or functional description is provided as an example only and various alterations and modifications may be made to the examples. Here, the examples are not construed as limited to the disclosure and should be understood to include all changes, equivalents, and replacements within the idea and the technical scope of the disclosure.

(9) Terms, such as first, second, and the like, may be used herein to describe components. Each of these terminologies is not used to define an essence, order or sequence of a corresponding component but used merely to distinguish the corresponding component from other component(s). For example, a first component may be referred to as a second component, and similarly the second component may also be referred to as the first component.

(10) It should be noted that if it is described that one component is “connected”, “coupled”, or “joined” to another component, a third component may be “connected”, “coupled”, and “joined” between the first and second components, although the first component may be directly connected, coupled, or joined to the second component.

(11) The singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises/comprising” and/or “includes/including” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

(12) Unless otherwise defined, all terms, including technical and scientific terms, used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms, such as those defined in commonly used dictionaries, are to be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art, and are not to be interpreted in an idealized or overly formal sense unless expressly so defined herein.

(13) Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings. When describing the example embodiments with reference to the accompanying drawings, like reference numerals refer to like components and a repeated description related thereto will be omitted.

(14) FIG. 1 illustrates a communication system according to an example embodiment.

(15) A communication system 10 may include a precoder 100 to mitigate a nonlinear distortion and inter-symbol interference (ISI) in a signal being transmitted and received. The precoder 100 may be implemented at a transmitter of the communication system 10. A demodulator may be implemented at a receiver corresponding to the precoder 100. FIG. 1 illustrates only a configuration to mitigate a nonlinear distortion and ISI in the communication system 10. Thus, it shall be understood that descriptions of general components of the communication system 10 are omitted.

(16) The precoder 100 may remove the ISI occurring in the communication system 10 using an inverse function H(Z)−1 of a channel response H(Z) through a filter 200. The precoder 100 may limit a maximum swing value transmitted for stabilizing the filter 200 to remove post-cursor ISI by performing a modulo operation Mod 2M by a modulo operator 130.

(17) The precoder 100 may output a third signal Y.sub.n by performing precoding when a first signal X.sub.n is input. The filter 200 may generate a filtering signal Z.sub.n based on the third signal Y.sub.n. A mixer 110 may generate a second signal X.sub.n′ based on the first signal X.sub.n and the filtering signal Z.sub.n. The second signal X.sub.n′ may be a signal removing the filtering signal Z.sub.n from the first signal X.sub.n. The modulo operator 130 may generate the third signal Y.sub.n by performing a modulo operation on the second signal X.sub.n′. The third signal Y.sub.n may be a signal transmitted to the receiver.

(18) The demodulator 150 may restore a received signal r.sub.n received from the receiver. The received signal r.sub.n may be a signal including noise when passing through a channel. A modulo operator 153 may restore the received signal r.sub.n by performing the modulo operation Mod 2M on the received signal r.sub.n.

(19) The precoder 100 may mitigate a nonlinear distortion occurring in the communication system 10 by selecting filter coefficients having nonlinear characteristics based on a level of a signal. The filter 200 may compensate for the nonlinear distortion by selecting the filter coefficients to generate the filtering signal Z.sub.n based on the first signal X.sub.n, the second signal X.sub.n′ and the third signal Y.sub.n.

(20) FIG. 2 illustrates an example of the precoder of FIG. 1.

(21) The precoder 100 may include the modulo operator 130 and the filter 200. The filter 200 may include a level detector 300, a plurality of delay elements 210-1 and 210-2, a plurality of selectors 230-1 to 230-3, a plurality of multipliers 250-1 to 250-3, and an adder 270.

(22) The level detector 300 may generate a selected signal Sel based on the first signal X.sub.n, the second signal X.sub.n′, and the third signal Y.sub.n. The level detector 300 may generate a level signal L.sub.n based on the first signal X.sub.n, the second signal X.sub.n′ and the third signal Y.sub.n and may output the selected signal Sel based on a level value of the level signal L.sub.n. For example, the selected signal Sel may have a value of 1 to m (m is a natural number) according to a level value of the level signal L.sub.n.

(23) The selectors 230-1 to 230-3 may output filter coefficients based on the selected signal Sel. For example, the selectors 230-1 to 230-3 may output filter coefficients corresponding to the selected signal Sel among a plurality of filtering signals h.sub.41 to h.sub.4m, h.sub.31 to h.sub.3m, and h.sub.21 to h.sub.2m. For example, when the selected signal Sel is k (k is a natural number greater than or equal to 1 and less than or equal to m), the selectors 230-1 to 230-3 may output the filter coefficients h.sub.4k, h.sub.3k, and h.sub.2k respectively.

(24) The delay elements 210-1 and 210-2 may output delayed signals by delaying the third signal Y.sub.n. For example, the first delay element 210-1 may output a first delayed signal Y.sub.n-1 by delaying the third signal Y.sub.n by a unit of time and the second delay element 210-2 may output a second delayed signal Y.sub.n-2 by delaying the first delayed signal Y.sub.n-1 by a unit of time. That is, the second delayed signal Y.sub.n-2 may be an output signal of the third signal Y.sub.n delayed by two units of time.

(25) The multipliers 250-1 to 250-3 may multiply the third signal Y.sub.n, the first delayed signal Y.sub.n-1 and the second delayed signal Y.sub.n-2 by the filter coefficient and may output multiplication results. For example, the first multiplier 250-1 may multiply the second delayed signal Y.sub.n-2 by the filter coefficient output from the first selector 230-1 and may output a multiplication result, the second multiplier 250-2 may multiply the first delayed signal Y.sub.n-1 by the filter coefficient output from the second selector 230-2 and may output a multiplication result, and the third multiplier 250-3 may multiply the third signal Y.sub.n by the filter coefficient output from the third selector 230-3 and may output a multiplication result.

(26) The adder 270 may add the multiplication results obtained by the multipliers 250-1 to 250-3 and output the filtering signal Z.sub.n. For example, the adder 270 may output the filtering signal Z.sub.n by adding all multiplication results output from the first multiplier 250-1 to the third multiplier 250-3 respectively. For example, when the selected signal Sel is k so that filter coefficients output from the selectors 230-1 to 230-3 are the filter coefficient h.sub.4k, h.sub.3k, and h.sub.2k respectively, the filtering signal Z.sub.n may be expressed by Equation 1.
Z.sub.n=h.sub.2kY.sub.n+h.sub.3kY.sub.n-1+h.sub.4kY.sub.n-2  [Equation 1]

(27) FIG. 3 illustrates the level detector of FIG. 2.

(28) The level detector 300 may include an adder 310 to generate a level signal L.sub.n based on a first signal X.sub.n, a second signal X.sub.n, and a third signal Y.sub.n and a comparator 330 to output the selected signal Sel based on the level signal L.sub.n and a plurality of comparison signals L.sub.th1 to L.sub.thm.

(29) The level signal L.sub.n output from the adder 310 may be expressed by Equation 2.
L.sub.n=X.sub.n−X.sub.n′+Y.sub.n  [Equation 2]

(30) The comparator 330 may determine which comparison signal among the plurality of comparison signals L.sub.th1 to L.sub.thm has a same level value as the level signal L.sub.n. For example, when a difference of level values between the level signal L.sub.n and a comparison signal Lt.sub.hk is less than or equal to a threshold value, the comparator 330 may determine that the level signal L.sub.n has a same level value as the comparison signal L.sub.thk.

(31) The comparator 330 may output the selected signal Sel corresponding to the comparison signal Lt.sub.hk which is determined to have a same level value as the level signal L.sub.n. For example, the comparator 330 may output k as the selected signal Sel corresponding to the comparison signal L.sub.thk having a same level value as the level signal L.sub.n.

(32) When the first signal X.sub.n is a pulse amplitude modulation-4 (PAM-4) signal, the level signal L.sub.n may include four signal levels as shown in FIG. 6A. The plurality of comparison signals Lt.sub.h1 to L.sub.thm may correspond to six signal levels as shown in FIG. 6B, and in this case, the selected signal Sel may be output as any one of 1 to 6.

(33) FIG. 4 illustrates another example of the precoder of FIG. 1 and FIG. 5 illustrates the level detector of FIG. 4.

(34) The precoder 100 may include the filter 200 to generate the filtering signal Z.sub.n using three selected signals Sel1 to Sel3. Since the precoder 100 of FIG. 4 may be same as the precoder 100 of FIG. 2 except for the level detector 300, a duplicate description of the configuration to perform the same operation is omitted.

(35) The level detector 300 may further include a plurality of delay elements 350-1 and 350-2. The delay elements 350-1 and 350-2 may output delayed signals by delaying the level signal L.sub.n output from the adder 310. For example, the first delay element 350-1 may output a first delayed level signal L.sub.n-1 by delaying the level signal L.sub.n by a unit of time and the second delay element 350-2 may output a second level signal L.sub.n-2 by delaying the first delayed level signal L.sub.n-1 by a unit of time. That is, the second delayed level signal L.sub.n-2 may be a delayed signal of the level signal L.sub.n by two units of time.

(36) The level detector 300 may further include a plurality of comparators 330-1 to 330-3. The respective comparators 330-1 to 330-3 may perform the same operation as the comparator 330 of FIG. 3. For example, the comparators 330-1 to 330-3 may output the first selected signal Sel1, the second selected signal Sel2, and the third selected signal Sel3 respectively based on the level signal L.sub.n, the first delayed level signal L.sub.n-1, and the second delayed level signal L.sub.n-2.

(37) The first selected signal Sel1, the second selected signal Sel2, and the third selected signal Sel3 may be input to the corresponding selectors 230-1 to 230-3. That is, since the selected signals Sel1 to Sel3 different from each other may be input to each of the selectors 230-1 to 230-3, the selectors 230-1 to 230-3 may output filter coefficients different from each other and the filtering signal Z.sub.n may be generated based on the different filter coefficients. For example, when the selected signals Sel1 to Sel3 are p, q, and r (p, q, and r are natural numbers greater than or equal to 1 and less than or equal to m) respectively, the filtering signal Z.sub.n may be expressed by Equation 3.
Z.sub.n=h.sub.2pY.sub.n+h.sub.3qY.sub.n-1+h.sub.4rY.sub.n-2  [Equation 3]

(38) The components described in the example embodiments may be implemented by hardware components including, for example, at least one digital signal processor (DSP), a processor, a controller, an application-specific integrated circuit (ASIC), a programmable logic element, such as a field programmable gate array (FPGA), other electronic devices, or combinations thereof. At least some of the functions or the processes described in the example embodiments may be implemented by software, and the software may be recorded on a recording medium. The components, the functions, and the processes described in the example embodiments may be implemented by a combination of hardware and software.

(39) The examples described herein may be implemented using hardware components, software components and/or combinations thereof. A processing device may be implemented using one or more general-purpose or special-purpose computers, such as, for example, a processor, a controller and an arithmetic logic unit (ALU), a DSP, a microcomputer, an FPGA, a programmable logic unit (PLU), a microprocessor or any other device capable of responding to and executing instructions in a defined manner. The processing device may run an operating system (OS) and one or more software applications that run on the OS. The processing device also may access, store, manipulate, process, and create data in response to execution of the software. For purpose of simplicity, the description of a processing device is used as singular; however, one skilled in the art will appreciate that a processing device may include multiple processing elements and multiple types of processing elements. For example, the processing device may include a plurality of processors, or a single processor and a single controller. In addition, different processing configurations are possible, such as parallel processors.

(40) The software may include a computer program, a piece of code, an instruction, or some combination thereof, to independently or uniformly instruct or configure the processing device to operate as desired. Software and data may be embodied permanently or temporarily in any type of machine, component, physical or pseudo equipment, computer storage medium or device, or in a propagated signal wave capable of providing instructions or data to or being interpreted by the processing device. The software also may be distributed over network-coupled computer systems so that the software is stored and executed in a distributed fashion. The software and data may be stored by one or more non-transitory computer-readable recording mediums.

(41) The methods according to the above-described example embodiments may be recorded in non-transitory computer-readable media including program instructions to implement various operations of the above-described example embodiments. The media may also include, alone or in combination with the program instructions, data files, data structures, and the like. The program instructions recorded on the media may be those specially designed and constructed for the purposes of example embodiments, or they may be of the kind well-known and available to those having skill in the computer software arts. Examples of non-transitory computer-readable media include magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROM discs, DVDs, and/or Blue-ray discs; magneto-optical media such as optical discs; and hardware devices that are specially configured to store and perform program instructions, such as read-only memory (ROM), random access memory (RAM), flash memory (e.g., USB flash drives, memory cards, memory sticks, etc.), and the like. Examples of program instructions include both machine code, such as produced by a compiler, and files containing higher-level code that may be executed by the computer using an interpreter.

(42) The above-described devices may be configured to act as one or more software modules in order to perform the operations of the above-described examples, or vice versa.

(43) A number of example embodiments have been described above. Nevertheless, it should be understood that various modifications may be made to these example embodiments. For example, suitable results may be achieved if the described techniques are performed in a different order and/or if components in a described system, architecture, device, or circuit are combined in a different manner and/or replaced or supplemented by other components or their equivalents.

(44) Accordingly, other implementations are within the scope of the following claims.