System with multiple signal loops and switched mode converter

Abstract

In accordance with embodiments of the present disclosure, a system may include an impedance estimator configured to estimate an impedance of a load and generate a target current based at least on an input voltage and the impedance, a voltage feedback loop responsive to a difference between the input voltage and an output voltage of the load, and a current controller configured to, responsive to the voltage feedback loop, the impedance estimator, and the input voltage, generate an output current to the load.

Claims

1. A system, comprising: an impedance estimator configured to estimate an impedance of a passive load and generate a target current based at least on an input voltage and the impedance; a voltage feedback loop responsive to a difference between the input voltage and an output voltage of the passive load; and a current controller configured to, responsive to the voltage feedback loop, the impedance estimator, and the input voltage, generate an output current to the passive load to generate an output voltage that is a function of the input voltage.

2. The system of claim 1, wherein the impedance of the passive load is estimated based on the output voltage and the output current.

3. The system of claim 1, wherein the voltage feedback loop comprises a delta-sigma modulator.

4. The system of claim 3, wherein the delta-sigma modulator is a continuous-time delta-sigma modulator.

5. The system of claim 1, wherein the impedance estimator comprises an adaptive filter responsive to the output current and configured to estimate the impedance of the passive load in order to adaptively minimize a difference between the output voltage at the passive load and a target output voltage for the passive load based on the input voltage.

6. The system of claim 5, wherein the adaptive filter is a least-mean-squares filter.

7. The system of claim 1, wherein the input voltage comprises an audio signal and the passive load comprises an acoustic transducer.

8. The system of claim 1, wherein the impedance estimator is configured to: determine impedance of the passive load as a function of a frequency of the output voltage; and control the target current to compensate for variance of the impedance as a function of the frequency.

9. The system of claim 1, wherein the impedance estimator is configured to control the target current to compensate for variance of the impedance over time.

10. A method, comprising: estimating an impedance of a passive load and generating a target current based at least on an input voltage and the impedance; generating a feedback voltage responsive to a difference between the input voltage and an output voltage of the passive load; and responsive to the feedback voltage, estimated impedance of the passive load, and the input voltage, generating an output current to the passive load to generate an output voltage that is a function of the input voltage.

11. The method of claim 10, wherein estimating the impedance of the passive load comprises estimating the impedance based on the output voltage and the output current.

12. The method of claim 10, further comprising generating the feedback voltage with a voltage feedback loop comprising a delta-sigma modulator.

13. The method of claim 12, wherein the delta-sigma modulator is a continuous-time delta-sigma modulator.

14. The method of claim 10, wherein estimating the impedance of the passive load comprises filtering responsive to the output current to adaptively minimize a difference between the output voltage at the passive load and a target output voltage for the passive load based on the input voltage.

15. The method of claim 14, wherein the adaptive filter is a least-mean-squares filter.

16. The method of claim 10, wherein the input voltage comprises an audio signal and the passive load comprises an acoustic transducer.

17. The method of claim 10, wherein estimating the impedance of the passive load comprises: determining the impedance of the passive load as a function of a frequency of the output voltage; and controlling the target current to compensate for variance of the impedance as a function of the frequency.

18. The method of claim 10, wherein the impedance estimator is configured to control the target current to compensate for variance of the impedance over time.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) A more complete understanding of the present embodiments and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein:

(2) FIG. 1 illustrates an example speaker driver, as is known in the relevant art;

(3) FIG. 2 illustrates an example personal audio device, in accordance with embodiments of the present disclosure;

(4) FIG. 3 illustrates a block diagram of selected components of an example audio integrated circuit of a personal audio device, in accordance with embodiments of the present disclosure;

(5) FIG. 4 illustrates a block and circuit diagram of selected components of an example switched mode amplifier, in accordance with embodiments of the present disclosure;

(6) FIG. 5 illustrates a circuit diagram of selected components of another example power converter, in accordance with embodiments of the present disclosure;

(7) FIG. 6 illustrates a table setting forth switch configurations of the power converter of FIG. 5 when operating in a single-ended boost mode, in accordance with embodiments of the present disclosure;

(8) FIG. 7 illustrates an equivalent circuit diagram of selected components of the power converter of FIG. 5 operating in a charging phase of a single-ended boost mode, in accordance with embodiments of the present disclosure;

(9) FIG. 8 illustrates an equivalent circuit diagram of selected components of the power converter of FIG. 5 operating in a discharge phase of a single-ended boost mode, in accordance with embodiments of the present disclosure;

(10) FIG. 9 illustrates a table setting forth switch configurations of the power converter of FIG. 5 when operating in a differential-output buck-boost mode, in accordance with embodiments of the present disclosure;

(11) FIG. 10 illustrates an equivalent circuit diagram of selected components of the power converter of FIG. 5 operating in a charging phase of a differential-output buck-boost mode, in accordance with embodiments of the present disclosure;

(12) FIG. 11 illustrates an equivalent circuit diagram of selected components of the power converter of FIG. 5 operating in a discharge phase of a differential-output buck-boost mode, in accordance with embodiments of the present disclosure;

(13) FIG. 12 illustrates a table setting forth switch configurations of the power converter of FIG. 5 when operating in a differential-output buck mode, in accordance with embodiments of the present disclosure;

(14) FIG. 13 illustrates an equivalent circuit diagram of selected components of the power converter of FIG. 5 operating in a charging phase of a differential-output buck mode, in accordance with embodiments of the present disclosure;

(15) FIG. 14 illustrates an equivalent circuit diagram of selected components of the power converter of FIG. 5 operating in another charging phase of a differential-output buck mode, in accordance with embodiments of the present disclosure;

(16) FIG. 15 illustrates an equivalent circuit diagram of selected components of the power converter of FIG. 5 operating in a discharge phase of a differential-output buck mode, in accordance with embodiments of the present disclosure;

(17) FIG. 16 illustrates a table setting forth switch configurations of the power converter of FIG. 5 when operating in a turn-around mode, in accordance with embodiments of the present disclosure;

(18) FIG. 17 illustrates an equivalent circuit diagram of selected components of the power converter of FIG. 5 operating in a charging phase of a differential-output turn-around mode, in accordance with embodiments of the present disclosure;

(19) FIG. 18 illustrates an equivalent circuit diagram of selected components of the power converter of FIG. 5 operating in another charging phase of a differential-output turn-around mode, in accordance with embodiments of the present disclosure;

(20) FIG. 19 illustrates an equivalent circuit diagram of selected components of the power converter of FIG. 5 operating in a discharge phase of a differential-output turn-around mode, in accordance with embodiments of the present disclosure;

(21) FIG. 20 illustrates a table setting forth switch configurations of the power converter of FIG. 5 when operating in a single-ended buck mode, in accordance with embodiments of the present disclosure;

(22) FIG. 21 illustrates an equivalent circuit diagram of selected components of the power converter of FIG. 5 operating in a charging phase of a single-ended buck mode, in accordance with embodiments of the present disclosure;

(23) FIG. 22 illustrates an equivalent circuit diagram of selected components of the power converter of FIG. 5 operating in a discharge phase of a single-ended buck mode, in accordance with embodiments of the present disclosure;

(24) FIG. 23 illustrates an equivalent circuit diagram of selected components of the power converter of FIG. 5 operating in another charging phase of a single-ended buck mode, in accordance with embodiments of the present disclosure;

(25) FIG. 24 illustrates an equivalent circuit diagram of selected components of the power converter of FIG. 5 operating in another discharge phase of a single-ended buck mode, in accordance with embodiments of the present disclosure;

(26) FIG. 25 illustrates the power converter of FIG. 5 including a linear amplifier implemented as a quadrant digital-to-analog converter, in accordance with embodiments of the present disclosure;

(27) FIG. 26 illustrates the power converter of FIG. 5 including a linear amplifier implemented as a hemispherical digital-to-analog converter, in accordance with embodiments of the present disclosure;

(28) FIG. 27 illustrates a circuit diagram of selected components of another example power converter, in accordance with embodiments of the present disclosure;

(29) FIG. 28 illustrates a graph of an example output voltage having a sinusoidal waveform, the graph indicating example ranges for operation in the various operational modes of the power converter of FIG. 5, in accordance with embodiments of the present disclosure;

(30) FIG. 29 illustrates a block diagram of selected components of an example loop filter, in accordance with embodiments of the present disclosure;

(31) FIG. 30 illustrates a block diagram of selected components of a power converter control, in accordance with embodiments of the present disclosure; and

(32) FIG. 31 illustrates a block and circuit diagram of selected components of an example switched mode amplifier including an impedance estimator, in accordance with embodiments of the present disclosure.

DETAILED DESCRIPTION

(33) FIG. 2 illustrates an example personal audio device 1, in accordance with embodiments of the present disclosure. FIG. 2 depicts personal audio device 1 coupled to a headset 3 in the form of a pair of earbud speakers 8A and 8B. Headset 3 depicted in FIG. 2 is merely an example, and it is understood that personal audio device 1 may be used in connection with a variety of audio transducers, including without limitation, headphones, earbuds, in-ear earphones, and external speakers. A plug 4 may provide for connection of headset 3 to an electrical terminal of personal audio device 1. Personal audio device 1 may provide a display to a user and receive user input using a touch screen 2, or alternatively, a standard liquid crystal display (LCD) may be combined with various buttons, sliders, and/or dials disposed on the face and/or sides of personal audio device 1. As also shown in FIG. 2, personal audio device 1 may include an audio integrated circuit (IC) 9 for generating an analog audio signal for transmission to headset 3 and/or another audio transducer.

(34) FIG. 3 illustrates a block diagram of selected components of an example audio IC 9 of a personal audio device, in accordance with embodiments of the present disclosure. As shown in FIG. 3, a microcontroller core 18 may supply a digital audio input signal DIG_IN to a digital-to-analog converter (DAC) 14, which may convert the digital audio input signal to an analog signal V.sub.IN. DAC 14 may supply analog signal V.sub.IN to an amplifier 16 which may amplify or attenuate audio input signal V.sub.IN to provide a differential audio output signal V.sub.OUT, which may operate a speaker, headphone transducer, a line level signal output, and/or other suitable output. In some embodiments, DAC 14 may be an integral component of amplifier 16. A power supply 10 may provide the power supply rail inputs of amplifier 16. In some embodiments, power supply 10 may comprise a battery. Although FIGS. 2 and 3 contemplate that audio IC 9 resides in a personal audio device, systems and methods described herein may also be applied to electrical and electronic systems and devices other than a personal audio device, including audio systems for use in a computing device larger than a personal audio device, an automobile, a building, or other structure.

(35) FIG. 4 illustrates a block and circuit diagram of selected components of an example switched mode amplifier 20, in accordance with embodiments of the present disclosure. In some embodiments, switched mode amplifier 20 may implement all or a portion of amplifier 16 described with respect to FIG. 3. As shown in FIG. 4, switched mode amplifier 20 may comprise a loop filter 22, a converter controller 24, and a power converter 26.

(36) Loop filter 22 may comprise any system, device, or apparatus configured to receive an input signal (e.g., audio input signal V.sub.IN or a derivative thereof) and a feedback signal (e.g., audio output signal V.sub.OUT, a derivative thereof, or other signal indicative of audio output signal V.sub.OUT) and based on such input signal and feedback signal, generate a controller input signal to be communicated to converter controller 24. In some embodiments, such controller input signal may comprise a signal indicative of an integrated error between the input signal and the feedback signal, as is described in greater detail below with reference to FIGS. 6, 9 and 25. In other embodiments, such controller input signal may comprise a signal indicative of a target current signal to be driven as an output current I.sub.OUT to a load coupled to the output terminals of power converter 26, as described in greater detail below with reference to FIGS. 26 and 27.

(37) Converter controller 24 may comprise any system, device, or apparatus configured to, based on the controller input signal, sequentially select among operational modes of power converter 26 and based on a selected operational mode, communicate a plurality of control signals to power converter 26 to apply a switch configuration from a plurality of switch configurations of switches of power converter 26 to selectively activate or deactivate each of the plurality of switches in order to transfer electrical energy from a power supply V.sub.SUPPLY to the load of switched-mode amplifier 20 in accordance with the selected operational mode. Examples of operational modes and switch configurations associated with each are described in greater detail elsewhere in this disclosure. Example implementations of converter controller 24 are also described in greater detail elsewhere in this disclosure. In addition, in some embodiments, converter controller 24 may control switches of a power converter 26 in order to regulate a common mode voltage of the output terminals of power converter 26 to the maximum of a first voltage associated with switched-mode amplifier 20 and a second voltage associated with switched-mode amplifier 20. In some embodiments, the first voltage may comprise one-half of the supply voltage V.sub.SUPPLY. In these and other embodiments, the second voltage may comprise one-half of output voltage V.sub.OUT, or another signal indicative of an expected voltage for output voltage V.sub.OUT (e.g, input voltage signal V.sub.IN).

(38) Power converter 26 may receive at its input a voltage V.sub.SUPPLY (e.g., provided by power supply 10) at its input, and may generate at its output audio output signal V.sub.OUT. Although not explicitly shown in FIG. 3, in some embodiments, voltage V.sub.SUPPLY may be received via input terminals including a positive input terminal and a negative input terminal which may be coupled to a ground voltage. As described in greater detail in this disclosure, power converter 26 may comprise a power inductor and a plurality of switches that are controlled by control signals received from converter controller 24 in order to convert voltage V.sub.SUPPLY to audio output signal V.sub.OUT, such that audio output signal V.sub.OUT is a function of the input signal to loop filter 22. Examples of power converter 26 are described in greater detail elsewhere in this disclosure.

(39) FIG. 5 illustrates a circuit diagram of selected components of an example power converter 26, in accordance with embodiments of the present disclosure. In some embodiments, power converter 26 depicted in FIG. 5 may implement all or a portion of power converter 26 described with respect to FIG. 4. As shown in FIG. 5, power converter 26 may receive at its input a voltage V.sub.SUPPLY (e.g., provided by power supply 10) at input terminals, including a positive input terminal and a negative input terminal which may be coupled to a ground voltage, and may generate at its output a differential output voltage V.sub.OUT. Power converter 26 may comprise a power inductor 62 and plurality of switches 51-60. Power inductor 62 may comprise any passive two-terminal electrical component which resists changes in electrical current passing through it and such that when electrical current flowing through it changes, a time-varying magnetic field induces a voltage in power inductor 62, in accordance with Faraday's law of electromagnetic induction, which opposes the change in current that created the magnetic field.

(40) Each switch 51-60 may comprise any suitable device, system, or apparatus for making a connection in an electric circuit when the switch is enabled (e.g., closed or on) and breaking the connection when the switch is disabled (e.g., open or off) in response to a control signal received by the switch. For purposes of clarity and exposition, control signals for switches 51-60 (e.g., control signals communicated from converter controller 24) are not depicted although such control signals would be present to selectively enable and disable switches 51-60. In some embodiments, a switch 51-60 may comprise an n-type metal-oxide-semiconductor field-effect transistor. Switch 51 may be coupled between the positive input terminal and a first terminal of power inductor 62. Switch 52 may be coupled between a second terminal of power inductor 62 and ground. Switch 53 may be coupled between a positive terminal of the output of power converter 26 and a second terminal of power inductor 62. Switch 54 may be coupled between a negative terminal of the output of power converter 26 and the first terminal of power inductor 62. Switch 55 may be coupled between a negative terminal of the output of power converter 26 and the second terminal of power inductor 62. Switch 56 may be coupled between a positive terminal of the output of power converter 26 and the first terminal of power inductor 62. Switch 57 may be coupled between the ground voltage and the first terminal of power inductor 62. Switch 58 may be coupled between the negative terminal of the output of power converter 26 and the ground voltage. Switch 59 may be coupled between the positive terminal of the output of power converter 26 and the ground voltage. Switch 60 may be coupled between the positive input terminal and the second terminal of power inductor 62.

(41) In addition to switches 51-60 and power inductor 62, power converter 26 may include a first output capacitor 66 coupled between the positive terminal of the output of power converter 26 and the ground voltage and a second output capacitor 68 coupled between the negative terminal of the output of power converter 26 and the ground voltage. Each output capacitor 66 and 68 may comprise a passive two-terminal electrical component used to store energy electrostatically in an electric field, and may generate a current in response to a time-varying voltage across the capacitor.

(42) As shown in FIG. 5, power converter 26 may in some embodiments comprise a linear amplifier 70. Functionality of power converter 26 is described in greater detail elsewhere in this disclosure for those embodiments including linear amplifier 70.

(43) As described above, a power converter 26 may operate in a plurality of different operational modes, and may sequentially operate in a number of switch configurations under each operational mode. The plurality of modes may include, without limitation, a single-ended boost mode, a differential-output buck-boost mode, a differential-output buck mode, and a low-voltage mode.

(44) Power converter 26 may operate in a single-ended boost mode when output voltage V.sub.OUT has a magnitude significantly larger than the supply voltage V.sub.SUPPLY (e.g., |V.sub.OUT|>V.sub.SUPPLY=2V). FIG. 6 illustrates a table setting forth switch configurations of power converter 26 when operating in the single-ended boost mode, in accordance with embodiments of the present disclosure. As shown in FIG. 6, when output voltage V.sub.OUT is positive, and during a charging phase T1 of power converter 26, converter controller 24 may enable switches 51, 52, and 58 of power converter 26, with such switch configuration resulting in the equivalent circuit depicted in FIG. 7. In such switch configuration, power inductor 62 may be charged via a current flowing between the power supply (e.g., power supply 10) and ground. When output voltage V.sub.OUT is positive, and during a discharge phase T2 of power converter 26, converter controller 24 may enable switches 51, 53, and 58 of power converter 26, with such switch configuration resulting in the equivalent circuit depicted in FIG. 8. In such switch configuration, power inductor 62 may be discharged, with charge transferred from the power supply (e.g., power supply 10) to the positive terminal of the output of power converter 26. Similarly, when output voltage V.sub.OUT is negative, and during the charging phase T1 of power converter 26, converter controller 24 may enable switches 51, 52, and 59 of power converter 26, wherein in accordance with such switch configuration, power inductor 62 may be charged via a current flowing between the power supply (e.g., power supply 10) and ground. In addition, when output voltage V.sub.OUT is negative, and during the discharge phase T2 of power converter 26, converter controller 24 may enable switches 51, 55, and 59 of power converter 26, wherein in accordance with such switch configuration, power inductor 62 may be discharged, with charge transferred from the power supply (e.g., power supply 10) to the negative terminal of the output of power converter 26.

(45) Notably, in the boost configuration, one of either of the terminals of the output of power converter 26 remains grounded in order to provide for operation in the boost mode, thus allowing power converter 26 to act as a boost converter when in the boost mode.

(46) In some embodiments, it may be desirable to operate in a continuous current mode (CCM) as opposed to a discontinuous current mode (DCM) when operating power converter 26 in the single-ended boost mode. This preference is because a CCM boost converter may have lower root-means-square (e.g., ripple) currents compared to a corresponding DCM boost converter.

(47) For an input voltage signal V.sub.I to loop filter 22, loop filter 22 may generate a target current signal I.sub.TGT as the controller input signal which may be given by I.sub.TGT=V.sub.I/R.sub.OUT, where R.sub.OUT is an impedance of a load at the output of power converter 26. A duration of charging phase T1 may be given by T1=DTT, where D is a unitless variable given by D=1(V.sub.SUPPLY/V.sub.I) and TT is a switching period of power converter 26 which is the sum of the durations of the charging phase T1 and the transfer phase T2 (e.g., TT=T1+T2). A change in power inductor current I.sub.L occurring during charging phase T1 may be given by I.sub.L=T1(V.sub.SUPPLY/L) where L is an inductance of power inductor 62. A minimum inductor current I.sub.min may be given by:
I.sub.min=[2TTI.sub.TGT(V.sub.SUPPLYV.sub.I)/LI.sub.L.sup.2]/2I.sub.L
and a peak current I.sub.pk for inductor current I.sub.L may be given as I.sub.pk=I.sub.min+I.sub.L.

(48) Power converter 26 may operate in a differential-output buck-boost mode when output voltage V.sub.OUT has a magnitude lower than that for which the single-ended boost mode is appropriate (e.g., |V.sub.OUT|<V.sub.SUPPLY+2V) but higher than a particular threshold magnitude (e.g., |V.sub.OUT|>3V) for which the duration of a charging phase T1 becomes too small to operate power converter 26 in a buck-boost mode. FIG. 9 illustrates a table setting forth switch configurations of power converter 26 when operating in the differential-output buck-boost mode, in accordance with embodiments of the present disclosure. As shown in FIG. 9, when output voltage V.sub.OUT is positive, and during a charging phase T1 of power converter 26, converter controller 24 may enable switches 51 and 52 of power converter 26, with such switch configuration resulting in the equivalent circuit depicted in FIG. 10. In such switch configuration, power inductor 62 may be charged via a current flowing between the power supply (e.g., power supply 10) and ground. When output voltage V.sub.OUT is positive, and during a discharge phase T2 of power converter 26, converter controller 24 may enable switches 53 and 54 of power converter 26, with such switch configuration resulting in the equivalent circuit depicted in FIG. 11. In such switch configuration, power inductor 62 may be discharged, with charge transferred from the negative terminal of the output of power converter 26 to the positive terminal of the output of power converter 26. Similarly, when output voltage V.sub.OUT is negative, and during the charging phase T1 of power converter 26, converter controller 24 may enable switches 51 and 52 of power converter 26, wherein in accordance with such switch configuration, power inductor 62 may be charged via a current flowing between the power supply (e.g., power supply 10) and ground. In addition, when output voltage V.sub.OUT is negative, and during the discharge phase T2 of power converter 26, converter controller 24 may enable switches 55 and 56 of power converter 26, wherein in accordance with such switch configuration, power inductor 62 may be discharged, with charge transferred from the positive terminal of the output of power converter 26 to the negative terminal of the output of power converter 26.

(49) Thus, in the differential-output buck-boost mode, power inductor 62 may be charged from V.sub.SUPPLY to ground during charging phases T1, and in discharging phases T2, power inductor 62 may be coupled across the output terminals of a load at the output of power converter 26 in order to discharge power inductor 62 and create a differential output. Coupling power inductor 62 across the output terminals in a differential output fashion may lead to a greater charge differential between capacitors 66 and 68 than would be in a single-ended configuration (e.g., with one of the output terminals grounded). Thus, lower power inductor peak currents may be required to achieve the same output current.

(50) Within the output voltage range of operation for the differential-output buck-boost mode, power converter 26 may operate in CCM for larger output voltages (e.g., 7V<V.sub.OUT<V.sub.SUPPLY+2V) and DCM for smaller output voltages (e.g., 3V<V.sub.OUT<7V). In DCM, peak current I.sub.pk of power inductor 62 may be given by:

(51) $I_{pk}=\sqrt{\frac{2I_{\mathrm{TGT}}{V}_{\mathrm{OUT}}\mathrm{TT}}{L}}$
where TT is a switching period of power converter 26.

(52) In CCM, a duration of charging phase T1 may be given by T1=DTT, where D is a unitless variable given by D=V.sub.OUT/(V.sub.OUT+V.sub.SUPPLY) and TT is a switching period of power converter 26 which is the sum of the durations of the charging phase T1 and the transfer phase T2 (e.g., TT=T1+T2). A change in power inductor current I.sub.L occurring during charging phase T1 may be given by I.sub.L=T1(V.sub.SUPPLY/L). A minimum inductor current I.sub.min may be given by:
I.sub.min=[I.sub.OUTTTV.sub.OUT/LI.sub.L.sup.2/2]/I.sub.L
and a peak current I.sub.pk for inductor current I.sub.L may be given as I.sub.pk=I.sub.min+I.sub.L.

(53) Power converter 26 may operate in a differential-output buck mode when output voltage V.sub.OUT has a magnitude lower than that for which the duration of a charging phase T1 becomes too small to operate power converter in a buck-boost mode (e.g., |V.sub.OUT|<3V) and a magnitude higher than for which the duration of a charging phase T1 becomes too small (e.g. |V.sub.OUT|>1V) to operate power converter 26 in a buck mode. FIG. 12 illustrates a table setting forth switch configurations of power converter 26 when operating in the differential-output buck-boost mode, in accordance with embodiments of the present disclosure. As shown in FIG. 12, in the differential-output buck mode, switch configurations may not only be based on the polarity of output voltage V.sub.OUT, but also on whether the common-mode voltage of the positive output terminal and the negative output terminal of power converter 26 is to be increased or decreased to regulate the common-mode voltage at a desired level, as shown in the column with the heading CM in FIG. 12. For example, in some embodiments, converter controller 24 may control switches of power converter 26 in order to regulate the common mode to a voltage associated with switched-mode amplifier 20. In some embodiments, the voltage may comprise one-half of the supply voltage V.sub.SUPPLY.

(54) As shown in FIG. 12, during a charging phase T1 of power converter 26, when output voltage V.sub.OUT is positive and the common-mode voltage of the output terminals is to be increased, converter controller 24 may enable switches 51 and 53 of power converter 26, with such switch configuration resulting in the equivalent circuit depicted in FIG. 13. In such switch configuration, power inductor 62 may be charged via a current flowing between the power supply (e.g., power supply 10) and the positive terminal of the output of power converter 26, thus generating a positive output voltage V.sub.OUT and increasing the common-mode voltage by increasing the electrical charge on capacitor 66. On the other hand, during a charging phase T1 of power converter 26, when output voltage V.sub.OUT is positive and the common-mode voltage of the output terminals is to be decreased, converter controller 24 may enable switches 52 and 54 of power converter 26, with such switch configuration resulting in the equivalent circuit depicted in FIG. 14. In such switch configuration, power inductor 62 may be charged via a current flowing between the negative terminal of the output of power converter 26 and ground, thus generating a positive output voltage V.sub.OUT and decreasing common-mode voltage by decreasing the electrical charge on capacitor 68. During a discharge phase T2 of power converter 26, when target current I.sub.TGT is positive and regardless of whether the common-mode voltage of the output terminals is to be increased or decreased, converter controller 24 may enable switches 53 and 54 of power converter 26, with such switch configuration resulting in the equivalent circuit depicted in FIG. 15. In such switch configuration, power inductor 62 may be discharged, with charge transferred from the negative terminal of the output of power converter 26 to the positive terminal of the output of power converter 26 in order to provide a positive output voltage V.sub.OUT while maintaining the same common-mode voltage.

(55) Similarly, during a charging phase T1 of power converter 26, when output voltage V.sub.OUT is negative and the common-mode voltage of the output terminals is to be increased, converter controller 24 may enable switches 51 and 55 of power converter 26. In such switch configuration, power inductor 62 may be charged via a current flowing between the power supply (e.g., power supply 10) and the negative terminal of the output of power converter 26, thus generating a negative output voltage V.sub.OUT and increasing the common-mode voltage by increasing the electrical charge on capacitor 68. On the other hand, during a charging phase T1 of power converter 26, when output voltage V.sub.OUT is negative and the common-mode voltage of the output terminals is to be decreased, converter controller 24 may enable switches 52 and 56 of power converter 26. In such switch configuration, power inductor 62 may be charged via a current flowing between the positive terminal of the output of power converter 26 and ground, thus generating a negative output voltage V.sub.OUT and decreasing common-mode voltage by decreasing the electrical charge on capacitor 66. During a discharge phase T2 of power converter 26, when output voltage V.sub.OUT is negative and regardless of whether the common-mode voltage of the output terminals is to be increased or decreased, converter controller 24 may enable switches 55 and 56 of power converter 26. In such switch configuration, power inductor 62 may be discharged, with charge transferred from the positive terminal of the output of power converter 26 to the negative terminal of the output of power converter 26 in order to provide a negative output voltage V.sub.OUT while maintaining the same common-mode voltage.

(56) Thus, during charging phases T1, converter controller 24 may cause power converter 26 to couple a capacitor 66 or 68 to supply voltage V.sub.SUPPLY or ground to increase or decrease the total amount of charge in capacitors 66 and 68 in order to regulate common-mode voltage of the output terminals. On the other hand, discharge phases T2 of converter controller 24 may cause power converter 26 to couple a power inductor 62 across the output terminals, which may redistribute charge between capacitors 66 and 68. Accordingly, in the differential-output buck mode, power converter 26 uses common-mode voltage at the output to create differential output voltage V.sub.OUT, as the duration of charging phase T1 may determine the common mode voltage and differential voltage V.sub.OUT while the duration of discharge phase T2 may additionally determine the differential voltage V.sub.OUT. As compared to other modes of operation, the differential-output buck mode provides for efficient charge transfer as charge is pushed to an output capacitor 66 or 68 during charging phase T1 and redistributed between output capacitors 66 and 68 during discharge phase T2. Because of such charge-transfer scheme, lower peak currents through power inductor 62 may be necessary to transfer charge as compared to other modes. Also, root-mean-square current through switch 51 may be reduced as it is not exercised as much as it is in other modes of operation, which may minimize power dissipation of switch 51. Common-mode voltage at the output terminals may also be well-controlled, as common-mode control is achieved by coupling an output capacitor 66 or 68 to supply voltage V.sub.SUPPLY or ground through power inductor 62.

(57) When operating in the differential-output buck mode, power converter 26 may typically operate in DCM, unless power inductor 62 has a very high inductance (e.g., greater than 500 nH). In DCM, peak current I.sub.pk of power inductor 62 may be given by:

(58) $I_{pk}=\sqrt{\frac{2I_{\mathrm{TGT}}{V}_{\mathrm{OUT}}\left(V_{\mathrm{SUPPLY}}-V_{\mathrm{OUT}}\right)\mathrm{TT}}{L{V}_{\mathrm{SUPPLY}}}}$
where TT is a switching period of power converter 26.

(59) In CCM, a duration of charging phase T1 may be given by T1=DTT, where D is a unitless variable given by D=V.sub.OUT/(V.sub.OUT+V.sub.SUPPLY) and TT is a switching period of power converter 26 which is the sum of the durations of the charging phase T1 and the transfer phase T2 (e.g., TT=T1+T2). A change in power inductor current I.sub.L occurring during charging phase T1 may be given by I.sub.L=T1(V.sub.SUPPLYV.sub.OUT)/2L. A minimum inductor current I.sub.min may be given by:
I.sub.min=[I.sub.OUTTT(V.sub.SUPPLYV.sub.OUT)TT/(LV.sub.SUPPLY)I.sub.L.sup.2/2]/I.sub.L
and a peak current I.sub.pk for inductor current I.sub.L may be given as I.sub.pk=I.sub.min+I.sub.L.

(60) Power converter 26 may operate in a low-voltage mode in order to allow output voltage V.sub.OUT to cross zero, as the differential-output buck mode and operational modes discussed above may not be capable of effectuating a polarity change in output voltage V.sub.OUT. Accordingly, when output voltage V.sub.OUT has a magnitude lower than a particular threshold (e.g., |V.sub.OUT|<1V), power converter 26 may operate in the low-voltage mode. As described below, the low-voltage mode may be implemented in one of a plurality of ways, including a single-ended buck mode and a linear amplifier mode.

(61) Power converter 26 may transition to operation in a differential-output turn-around mode from the differential-output buck mode when, while operating in the differential-output buck mode, output voltage V.sub.OUT has a polarity opposite that of a target voltage V.sub.TGT for output voltage V.sub.OUT wherein target voltage V.sub.TGT corresponds to input signal INPUT. In such a situation, output voltage V.sub.OUT may need to effectively change polarity in a quick fashion, which may not be possible using any of the operational modes described above. FIG. 16 illustrates a table setting forth switch configurations of power converter 26 when operating in the differential-output turn-around mode, in accordance with embodiments of the present disclosure. As shown in FIG. 16, in the differential-output turn-around mode, switch configurations may not only be based on the polarities of output voltage V.sub.OUT and target voltage V.sub.TGT, but also on whether the common-mode voltage of the positive output terminal and the negative output terminal of power converter 26 is to be increased or decreased to regulate the common-mode voltage at a desired level, as shown in the column with the heading CM in FIG. 16. For example, in some embodiments, converter controller 24 may control switches of power converter 26 in order to regulate the common mode to a voltage associated with switched-mode amplifier 20. In some embodiments, the voltage may comprise one-half of the supply voltage V.sub.SUPPLY.

(62) As shown in FIG. 16, during a charging phase T1 of power converter 26, when output voltage V.sub.OUT is negative, target voltage V.sub.TGT is positive (meaning output voltage V.sub.OUT needs to switch from a negative to a positive polarity), and the common-mode voltage of the output terminals is to be increased, converter controller 24 may enable switches 51 and 53 of power converter 26, with such switch configuration resulting in the equivalent circuit depicted in FIG. 17. In such switch configuration, power inductor 62 may be charged via a current flowing between the power supply (e.g., power supply 10) and the positive terminal of the output of power converter 26, thus generating an increasing output voltage V.sub.OUT and increasing the common-mode voltage by increasing the electrical charge on capacitor 66. On the other hand, during a charging phase T1 of power converter 26, when output voltage V.sub.OUT is negative, target voltage V.sub.TGT is positive (meaning output voltage V.sub.OUT needs to switch from a negative to a positive polarity), and the common-mode voltage of the output terminals is to be decreased, converter controller 24 may enable switches 52 and 54 of power converter 26, with such switch configuration resulting in the equivalent circuit depicted in FIG. 18. In such switch configuration, power inductor 62 may be charged via a current flowing between the negative terminal of the output of power converter 26 and ground, thus generating an increasing output voltage V.sub.OUT and decreasing common-mode voltage by decreasing the electrical charge on capacitor 68. During a discharge phase T2 of power converter 26, when output voltage V.sub.OUT is negative, target voltage V.sub.TGT is positive (meaning output voltage V.sub.OUT needs to switch from a negative to a positive polarity), and regardless of whether the common-mode voltage of the output terminals is to be increased or decreased, converter controller 24 may enable switches 53 and 57 of power converter 26, with such switch configuration resulting in the equivalent circuit depicted in FIG. 19. In such switch configuration, power inductor 62 may be discharged, with charge transferred from the ground to the positive terminal of the output of power converter 26 in order to provide an increasing output voltage V.sub.OUT.

(63) Similarly, during a charging phase T1 of power converter 26, when output voltage V.sub.OUT is positive, target voltage V.sub.TGT is negative (meaning output voltage V.sub.OUT needs to switch from a positive to a negative polarity), and the common-mode voltage of the output terminals is to be increased, converter controller 24 may enable switches 51 and 55 of power converter 26. In such switch configuration, power inductor 62 may be charged via a current flowing between the power supply (e.g., power supply 10) and the negative terminal of the output of power converter 26, thus generating a decreasing output voltage V.sub.OUT and increasing the common-mode voltage by increasing the electrical charge on capacitor 68. On the other hand, during a charging phase T1 of power converter 26, when output voltage V.sub.OUT is positive, target voltage V.sub.TGT is negative (meaning output voltage V.sub.OUT needs to switch from a positive to a negative polarity), and the common-mode voltage of the output terminals is to be decreased, converter controller 24 may enable switches 52 and 56 of power converter 26. In such switch configuration, power inductor 62 may be charged via a current flowing between the positive terminal of the output of power converter 26 and ground, thus generating a decreasing output voltage V.sub.OUT and decreasing common-mode voltage by decreasing the electrical charge on capacitor 66. During a discharge phase T2 of power converter 26, voltage V.sub.OUT is positive, target voltage V.sub.TGT is negative (meaning output voltage V.sub.OUT needs to switch from a positive to a negative polarity), and regardless of whether the common-mode voltage of the output terminals is to be increased or decreased, converter controller 24 may enable switches 55 and 57 of power converter 26. In such switch configuration, power inductor 62 may be discharged, with charge transferred from the ground to the negative terminal of the output of power converter 26 in order to provide a decreasing output voltage V.sub.OUT.

(64) Thus, during charging phases T1, converter controller 24 may cause power converter 26 to couple a capacitor 66 or 68 to supply voltage V.sub.SUPPLY or ground to increase or decrease the total amount of charge in capacitors 66 and 68 in order to regulate common-mode voltage of the output terminals. On the other hand, discharge phases T2 of converter controller 24 may cause power converter 26 to couple a power inductor 62 between the ground and one of the output terminals, to increase or decrease output voltage V.sub.OUT. Accordingly, in the differential-output turn-around mode, power converter 26 uses common-mode voltage at the output to create differential output voltage V.sub.OUT, as the duration of charging phase T1 may determine the common mode voltage and differential voltage V.sub.OUT while the duration of discharge phase T2 may additionally determine the differential voltage V.sub.OUT.

(65) FIG. 20 illustrates a table setting forth switch configurations of power converter 26 when operating in the single-ended buck mode, in accordance with embodiments of the present disclosure. As shown in FIG. 20, when target voltage V.sub.TGT is positive and the common-mode voltage of the output terminals is to be increased, power converter 26 may have a charging phase T1 in which converter controller 24 enables switches 51 and 53 (as shown in the equivalent circuit depicted in FIG. 21), followed immediately by a discharge phase T2 in which converter controller 24 enables switches 54 and 60 of power converter 26 (as shown in the equivalent circuit depicted in FIG. 22). In such charging phase T1, power inductor 62 may be charged via a current flowing between the power supply (e.g., power supply 10) and the positive terminal of the output of power converter 26, thus generating an increasing output voltage V.sub.OUT and increasing the common-mode voltage by increasing the electrical charge on capacitor 66. In such discharge phase T2, power inductor 62 may be discharged, with charge transferred from the negative terminal of the output of power converter 26 to the power supply in order to provide an increasing output voltage V.sub.OUT. Discharge phase T2 may have the effect of decreasing the common-mode voltage, but the net effect of charging phase T1 and discharge phase T2 may be an increase in common-mode voltage.

(66) Also as shown in FIG. 20, when target voltage V.sub.TGT is positive and the common-mode voltage of the output terminals is to be decreased, power converter 26 may have a charging phase T1 in which converter controller 24 enables switches 52 and 54 (as shown in the equivalent circuit depicted in FIG. 23), followed immediately by a discharge phase T2 in which converter controller 24 enables switches 53 and 57 of power converter 26 (as shown in the equivalent circuit depicted in FIG. 24). In such charging phase T1, power inductor 62 may be charged via a current flowing between the negative terminal of the output of power converter 26 and ground, thus generating an increasing output voltage V.sub.OUT and decreasing common-mode voltage by decreasing the electrical charge on capacitor 68. In such discharge phase T2, power inductor 62 may be discharged, with charge transferred from the ground to the positive terminal of the output of power converter 26 in order to provide an increasing output voltage V.sub.OUT. Discharge phase T2 may have the effect of increasing the common-mode voltage, but the net effect of charging phase T1 and discharge phase T2 may be a decrease in common-mode voltage.

(67) Similarly, when target voltage V.sub.TGT is positive and the common-mode voltage of the output terminals is to be increased, power converter 26 may have a charging phase T1 in which converter controller 24 enables switches 51 and 55, followed immediately by a discharge phase T2 in which converter controller 24 enables switches 56 and 60 of power converter 26. In such charging phase T1, power inductor 62 may be charged via a current flowing between the power supply (e.g., power supply 10) and the negative terminal of the output of power converter 26, thus generating a decreasing output voltage V.sub.OUT and increasing the common-mode voltage by increasing the electrical charge on capacitor 68. In such discharge phase T2, power inductor 62 may be discharged, with charge transferred from the positive terminal of the output of power converter 26 to the power supply in order to provide a decreasing output voltage V.sub.OUT. Discharge phase T2 may have the effect of decreasing the common-mode voltage, but the net effect of charging phase T1 and discharge phase T2 may be an increase in common-mode voltage.

(68) On the other hand, when target voltage V.sub.TGT is positive and the common-mode voltage of the output terminals is to be increased, power converter 26 may have a charging phase T1 in which converter controller 24 enables switches 52 and 56, followed immediately by a discharge phase T2 in which converter controller 24 enables switches 55 and 57 of power converter 26. In such charging phase T1, power inductor 62 may be charged via a current flowing between the positive terminal of the output of power converter 26 and ground, thus generating a decreasing output voltage V.sub.OUT and decreasing common-mode voltage by decreasing the electrical charge on capacitor 66. In such discharge phase T2, power inductor 62 may be discharged, with charge transferred from the ground to the negative terminal of the output of power converter 26 in order to provide a decreasing output voltage V.sub.OUT. Discharge phase T2 may have the effect of increasing the common-mode voltage, but the net effect of charging phase T1 and discharge phase T2 may be a decrease in common-mode voltage.

(69) In the linear amplifier mode, linear amplifier 70 may receive a digital linear amplifier input signal from converter controller 24, loop filter 22, or elsewhere within switched mode amplifier 20. For example, in some embodiments, digital linear amplifier input signal may comprise an output of a quantizer of loop filter 22. To provide for fine resolution in the low-voltage mode of output voltages at magnitudes lower than the operational range of the differential-output buck mode, power converter 26 may operate in a linear amplifier mode, in which linear amplifier 70 of FIG. 5, operating in effect as a digital-to-analog converter (DAC), may be used to convert the digital linear amplifier control signal (which may be indicative of a desired output current I.sub.OUT) communicated from loop filter 22, converter controller 24, or elsewhere within switched mode amplifier into an analog current driven to a load coupled between output terminals of power converter 26. Linear amplifier 70, which is shown as a current source in FIG. 5, may comprise any system, device, or apparatus configured to generate a current in response to an input signal.

(70) An example embodiment for linear amplifier 70 is depicted in FIG. 25, in which linear amplifier 70 is embodied as a current-mode quadrant DAC having variable current sources 70A, 70B, 70C, and 70D. In the linear amplifier mode, when output voltage V.sub.OUT is positive, current sources 70A and 70B may be enabled to deliver a current to a load at the output of power converter 26 with a magnitude to generate the desired positive output voltage V.sub.OUT. Conversely, when output voltage V.sub.OUT is negative, current sources 70C and 70D may be enabled to deliver a current to a load at the output of power converter 26 with a magnitude to generate the desired negative output voltage V.sub.OUT.

(71) Another example embodiment for linear amplifier 70 is shown in FIG. 26, in which linear amplifier 70 is embodied as a current-mode hemispherical DAC having variable current sources 70E and 70F and switches 71A, 71B, 71C, and 71D. In the linear amplifier mode, when output voltage V.sub.OUT is positive, switches 71A and 71B may be enabled (e.g., closed or on) and switches 71C and 71D may be disabled (e.g, open or off) to deliver a current to a load at the output of power converter 26 with a magnitude to generate the desired positive output voltage V.sub.OUT. Conversely, when output voltage V.sub.OUT is negative, switches 71C and 71D may be enabled (e.g., closed or on) and switches 71A and 71B may be disabled (e.g, open or off) to deliver a current to a load at the output of power converter 26 with a magnitude to generate the desired negative output voltage V.sub.OUT.

(72) In some embodiments, converter controller 24 may control switches of power converter 26 such that the switches perform synchronous rectification, wherein all switches of power converter 26 are controlled (e.g., disabled if inductor current I.sub.L decrease to zero) in order to prevent inductor current I.sub.L from decreasing below zero. In other embodiments, power converter 26 may include a diode (e.g., with anode terminal coupled to power inductor 62 and cathode terminal coupled to switches 53 and 55) in order to prevent inductor current I.sub.L from decreasing below zero.

(73) FIG. 27 illustrates a circuit diagram of selected components of another example power converter 26A, in accordance with embodiments of the present disclosure. Power converter 26A may, in some embodiments, be used as an alternative to power converter 26 depicted in FIG. 5, and may in many respects, be mathematically equivalent to power converter 26 depicted in FIG. 5 and/or operate in a similar manner to power converter 26 depicted in FIG. 5. As shown in FIG. 27, power converter 26A may receive at its input a voltage V.sub.SUPPLY (e.g., provided by power supply 10) at input terminals, including a positive input terminal and a negative input terminal which may be coupled to a ground voltage, and may generate at its output a differential output voltage V.sub.OUT. Power converter 26A may comprise a power inductor 62A, and a plurality of switches 51A-58A. Although not shown in FIG. 27, power converter 26A may also include across its output terminals a linear amplifier identical or similar to linear amplifier 70 of power converter 26. Power inductor 62A may comprise any passive two-terminal electrical component which resists changes in electrical current passing through it and such that when electrical current flowing through it changes, a time-varying magnetic field induces a voltage in power inductor 62A, in accordance with Faraday's law of electromagnetic induction, which opposes the change in current that created the magnetic field.

(74) Each switch 51A-58A may comprise any suitable device, system, or apparatus for making a connection in an electric circuit when the switch is enabled (e.g., closed or on) and breaking the connection when the switch is disabled (e.g., open or off) in response to a control signal received by the switch. For purposes of clarity and exposition, control signals for switches 51A-58A (e.g., control signals communicated from converter controller 24) are not depicted although such control signals would be present to selectively enable and disable switches 51A-58A. In some embodiments, a switch 51A-58A may comprise an n-type metal-oxide-semiconductor field-effect transistor. Switch 51A may be coupled between the positive input terminal and a first terminal of power inductor 62A. Switch 52A may be coupled between the positive input terminal and a second terminal of power inductor 62A. Switch 53A may be coupled between the first terminal of power inductor 62A and the ground voltage. Switch 54A may be coupled between the second terminal of power inductor 62A and the ground voltage. Switch 55A may be coupled between the first terminal of power inductor 62A and a negative terminal of the output of power converter 26A. Switch 56A may be coupled between the second terminal of power inductor 62A and a positive terminal of the output of power converter 26A. Switch 57A may be coupled between the negative terminal of the output of power converter 26A and the ground voltage. Switch 58A may be coupled between the positive terminal of the output of power converter 26A and the ground voltage.

(75) In addition to switches 51A-58A and power inductor 62A, power converter 26A may include a first output capacitor 66A coupled between the positive terminal of the output of power converter 26A and the ground voltage and a second output capacitor 68A coupled between the negative terminal of the output of power converter 26A and the ground voltage. Each output capacitor 66A and 68A may comprise a passive two-terminal electrical component used to store energy electrostatically in an electric field, and may generate a current in response to a time-varying voltage across the capacitor.

(76) FIG. 28 illustrates a graph of an example output voltage V.sub.OUT having a sinusoidal waveform, the graph indicating example ranges for operation in the various operational modes of power converter 26. Thus, for a full-scale sinusoidal signal, power converter 26 may sequentially operate in the low-voltage mode (e.g., single-ended buck, or linear amplifier mode), the differential-output buck mode, the differential output buck-boost mode, the single-ended boost mode, the differential output buck-boost mode, the differential-output buck mode, and the low-voltage mode (e.g., single-ended buck, or linear amplifier mode) for each half-cycle of output voltage V.sub.OUT. Although not shown in FIG. 28, in some embodiments, while operating in the differential-output buck mode, power converter 26 may switch to operation in the differential-output turn-around mode, in order to change a signal polarity of the output voltage V.sub.OUT in response to a target voltage corresponding to input signal INPUT having an opposite polarity of output voltage V.sub.OUT. In addition, in these and other embodiments, the low-voltage mode may employ the differential-output turn-around mode or a similar mode (e.g., instead of the single-ended buck or linear amplifier mode) in order to operate at lower voltage magnitudes and change the polarity of output voltage V.sub.OUT.

(77) FIG. 29 illustrates a block diagram of selected components of an example loop filter 22, in accordance with embodiments of the present disclosure. In some embodiments, loop filter 22 depicted in FIG. 29 may implement all or a portion of loop filter 22 described with respect to FIG. 4.

(78) Loop filter 22 may comprise a delta-sigma filter or similar filter which may have the function of moving quantization errors outside the audio band. Loop filter 22 may include an input summer 73 for generating a difference between an input signal (e.g., an analog voltage signal V.sub.IN) and a feedback signal (e.g., output voltage V.sub.OUT), and one or more integrator stages 74, such that loop filter 22 operates as analog filter of an error signal equal to the difference between the input signal and the feedback signal, and generates, at the output of output summer 75 a filtered analog signal to analog-to-digital converter (ADC) 78 based on the input signal and the feedback signal. The inputs to output summer 75 may include the input signal as modified by a feed-forward gain coefficient K.sub.F applied by a gain element 76, the outputs of individual integrator stages 74 as each is modified by a respective integrator gain coefficient K.sub.1, K.sub.2, . . . , K.sub.N applied by gain elements 76, and the output of a feedback digital-to-analog converter 80 as modified by a delay-compensation coefficient K.sub.F applied by a gain element 76 in order to compensate for excess loop delay of loop filter 22.

(79) ADC 78 may comprise any system, device, or apparatus for converting the analog output signal generated by loop filter 22 (e.g., the output of output summer 75) into an equivalent digital signal, which, in some embodiments, may represent a desired output voltage to be generated at the output of switched mode amplifier 20 (e.g., across the terminals labeled V.sub.OUT in FIG. 5). Such digital signal or a derivative thereof (e.g., a current signal based on the input signal) may be communicated to converter controller 24, such that converter controller 24 may control switches of power converter 26 in accordance with a selected mode corresponding to such quantized integrated error.

(80) DAC 80 may comprise any suitable system, device, or apparatus configured to convert the digital signal into an equivalent analog feedback signal.

(81) FIG. 30 illustrates a block diagram of selected components of an example converter controller 24A, in accordance with embodiments of the present disclosure. In some embodiments, converter controller 24A depicted in FIG. 30 may implement all or a portion of converter controller 24 described with respect to FIG. 4. In the embodiments represented by FIG. 30 the controller input signal received by converter controller 24A is a target current signal I.sub.TGT. As shown in FIG. 30, converter controller 24A may implement an ADC 82, a mode determiner 84, a peak current computation block 86, a DAC 88, a peak current detector 90, a clock 92, a phase determiner 94, and a switch controller 96.

(82) ADC 82 may comprise any system, device, or apparatus configured to convert analog output voltage V.sub.OUT (or a derivative thereof) into an equivalent digital signal V.sub.OUT_DIG.

(83) Mode determiner 84 may comprise any system, device, or apparatus configured to select a mode of operation from a plurality of modes of operation (e.g., single-ended boost mode, differential-output buck-boost mode, differential-output buck mode, low-voltage mode, etc.) based on digital output voltage signal V.sub.OUT_DIG (or another signal indicative of output voltage V.sub.OUT) and/or a digital input voltage signal V.sub.I_DIG indicative of input voltage V.sub.IN. For example, mode determiner 84 may select the mode of operation based upon a voltage range of digital output voltage signal V.sub.OUT_DIG, digital input voltage signal V.sub.I_DIG, or a signal derivative or indicative thereof, such as analog feedback voltage V.sub.FB described in greater detail below with respect to FIG. 31 (e.g., select single-ended boost mode for |V.sub.FB|>14V, select differential-output buck-boost mode for 3V<|V.sub.FB|<14V, select differential-output buck mode for 1V<|V.sub.FB|<3V, and select the low-voltage mode for |V.sub.1|<1V).

(84) Peak current computation block 86 may comprise any system, device, or apparatus configured to compute a peak current I.sub.pk to be driven through power inductor 62 during a switching cycle of power converter 26. Such peak current I.sub.pk may be calculated based on the selected mode of operation, digital output voltage signal V.sub.OUT_DIG (or another signal indicative of output voltage V.sub.OUT), supply voltage V.sub.SUPPLY, output current I.sub.OUT (or another signal indicative of output current I.sub.OUT), and/or target current I.sub.TGT in accordance with the various equations for peak current I.sub.pk set forth above.

(85) DAC 88 may comprise any system, device, or apparatus configured to convert a digital signal generated by peak current computation block 106 indicative of peak current I.sub.pk into an equivalent analog peak current signal I.sub.pk.

(86) Peak current detector 90 may comprise any system, device, or apparatus configured to compare power inductor current I.sub.L to the analog peak current signal I.sub.pk and generate an output signal indicative of the comparison, thus providing an indication for when power inductor current I.sub.L has reached its desired peak current. Power inductor current I.sub.L reaching its desired peak current may indicate the end of a charging phase T1 and beginning of a transfer phase T2 of power converter 26.

(87) Clock 92 may comprise any system, device, or apparatus configured to generate a periodic timing signal indicative of an occurrence of or within a switching cycle of power converter 26. For example, a zero crossing, edge, or other characteristic of a waveform generated by clock 92 may indicate the beginning of a charging phase T1 of power converter 26.

(88) Phase determiner 94 may comprise any system, device, or apparatus configured to, based on the outputs of peak current detector 90 and clock 92, determine which phase (e.g., charging phase T1 or discharge phase T2) power converter 26 is to operate.

(89) Switch controller 96 may comprise any system, device, or apparatus configured to, based on the mode of operation, phase, polarity of digital input signal V.sub.I_DIG (or another signal indicative of input voltage V.sub.IN or output voltage V.sub.OUT), and (for the differential-output buck mode of power converter 26) a common-mode voltage V.sub.CM of the output terminals of power converter 26, generate switch control signals for controlling the switches of power converter 26.

(90) Thus, during each switching cycle for converter controller 24A, converter controller 24A may select a mode of operation based on input voltage V.sub.IN and output voltage V.sub.OUT, calculate a peak current I.sub.pk based on input voltage V.sub.IN, output voltage V.sub.OUT, target current signal I.sub.TGT, and/or output current I.sub.OUT, and use information regarding the selected mode and the phase of power converter 26 to select a switch configuration to control the switches of power converter 26. In alternative embodiments, rather than operating as a peak current system as depicted in FIG. 28, converter controller 24 may operate as a time-based system based on measurements of supply voltage V.sub.SUPPLY, output voltage V.sub.OUT, and output current I.sub.OUT.

(91) Thus, in the various embodiments disclosed herein, the choice of sequence for switches of power converter 26 may be made consistent with a desired change in output voltage V.sub.OUT. By repeatedly increasing and decreasing output voltage V.sub.OUT in small steps, output voltage V.sub.OUT may be made to follow, on average, the desired audio signal. Accordingly, quantization error present in output voltage V.sub.OUT may be moved outside the audio band in a manner similar to a delta-sigma modulator.

(92) FIG. 31 illustrates a block and circuit diagram of selected components of an example switched mode amplifier 20B including an impedance estimator 23, in accordance with embodiments of the present disclosure. In the embodiments represented by FIG. 31, switched mode amplifier 20B may operate as voltage feedback loop (e.g., a delta-sigma modulator) responsive to input voltage V.sub.I and output voltage V.sub.OUT. Switched mode amplifier 20B may be similar to switched mode amplifier 20 of FIG. 4, except that switched mode amplifier 20B may also include impedance estimator 23 and a current calculator 21 interfaced between loop filter 22 and converter controller 24, and a differential amplifier 25 and a current sensor 27. Loop filter 22, converter controller 24, and power converter 26 may respectively comprise any suitable loop filters, converter controllers, and power converters, including without limitation the various loop filters, converter controllers, and power converters disclosed herein. In the embodiments represented by FIG. 31, loop filter 22 may receive an input voltage V.sub.I as its input and generate, based on input voltage V.sub.I and an analog voltage feedback signal V.sub.FB, a target voltage signal V.sub.TGT representative of a voltage to be applied as output voltage V.sub.OUT.

(93) Impedance estimator 23 may comprise any system, device, or apparatus for estimating an impedance of a load at the output of switched mode amplifier 20B (e.g., across the terminals labeled V.sub.OUT in FIG. 31). Impedance estimator 23 may estimate load impedance Z.sub.OUT based on a measured output current I.sub.OUT and analog voltage feedback signal V.sub.FB (or other signal indicative of output voltage V.sub.OUT), and applying Ohm's law to determine load impedance Z.sub.OUT (e.g., Z.sub.OUTV.sub.FB/I.sub.OUT). In some embodiments, impedance estimator 23 may comprise or implement an adaptive filter (e.g., a least-mean-squares filter) configured to adaptively minimize a difference between target output voltage V.sub.TGT of a load and an actual output voltage of the load (e.g., V.sub.OUT, V.sub.FB), wherein target output voltage V.sub.TGT is equal to an output voltage expected from applying target current signal I.sub.TGT to the load assuming no variance of a nominal impedance of the load, and the actual output voltage at the load is the output voltage of the load generated by applying the output current (e.g., I.sub.OUT) to the load. In these and other embodiments, impedance estimator 23 may be configured to determine impedance of a load at the output of switched-mode amplifier 20B as a function of a frequency of output voltage V.sub.OUT and control target current signal I.sub.TGT to compensate for variance of the impedance as a function of the frequency. In these and other embodiments, impedance estimator 23 may be configured to control target current signal I.sub.TGT to compensate for variance of the impedance Z.sub.OUT over time.

(94) Current calculator 21 comprise any system, device, or apparatus for calculating a target current I.sub.TGT to be applied to the output load of power converter 26 based on target output voltage V.sub.TGT generated by loop filter 22 and estimated load impedance Z.sub.OUT generated by impedance estimator 23, and applying Ohm's law to determine target current I.sub.TGT(e.g. I.sub.TGTV.sub.TGT/Z.sub.OUT).

(95) Differential amplifier 25 may comprise any system, device, or apparatus configured to receive at its input terminals differential output voltage V.sub.OUT and generate analog voltage feedback signal V.sub.FB indicative of differential output voltage V.sub.OUT.

(96) Current sensor 27 may comprise any system, device, or apparatus configured to sense output current F.sub.OUT and generate a signal indicative of such sensed output current.

(97) Thus, switched-mode amplifier 20B may comprise a system which includes an impedance estimator 23 configured to estimate an impedance of a load at the output of switched-mode amplifier 20B and a current calculator 21 configured to generate a target current I.sub.TGT based at least on an input voltage V.sub.I and the impedance. In some embodiments, current calculator 21 may be integral to impedance estimator 23 such that impedance estimator 23 includes both the functionality of impedance estimator 23 and current calculator 21 depicted on FIG. 31. Such system may also include a voltage feedback loop (e.g., implemented by differential amplifier 25 and loop filter 22) responsive to a difference between the input voltage V.sub.I and an output voltage of the load (represented by analog voltage feedback signal V.sub.FB). Such system may also include a current controller (e.g., implemented by converter controller 24 and power converter 26) configured to, responsive to the voltage feedback loop, impedance estimator 23, and the input voltage V.sub.I, generate an output current F.sub.OUT to the load.

(98) As used herein, absolute voltage values (e.g., 1V, 3V, 7V, 14V) are given merely as examples, and any other suitable voltages may be used to define ranges of operation of the various power converter modes described herein.

(99) As used herein, when two or more elements are referred to as coupled to one another, such term indicates that such two or more elements are in electronic communication or mechanical communication, as applicable, whether connected indirectly or directly, with or without intervening elements.

(100) This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative.

(101) All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present inventions have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the disclosure.