AN ELECTRONIC CIRCUIT THAT GENERATES A HIGH-IMPEDANCE LOAD AND AN ASSOCIATED METHOD

Abstract

An electronic circuit configured to present a high-impedance load between a load point and a reference point includes a capacitive element (C) provided between a first node (Node A) and the reference point, a first element (D.sub.1) connected in parallel with the capacitive element (C), a first switching element (S.sub.1) provided in series between the first node (A) and a voltage source point, a second switching element (S.sub.2) provided between the first node (A) and a second node (Node B), a second element (D.sub.2) connected between the second switching element (S.sub.2), the load point, and the reference point, and timing control logic configured to implement three stages. In a charging stage, the first switching element (S.sub.1) is closed and the second switching element (S.sub.2) to charge a nodal voltage v.sub.D(t) at the first node (A). In discharge stage, the first switching element (S.sub.1) is open and the second switching element (S.sub.2) is open to enable discharging of the capacitive element (C) through the first element (D.sub.1). In a transfer stage, the second switching element (S.sub.2) is closed to connect the first node (A) and the second node (B), after which the second switching element (S.sub.2) is opened and the second element (D.sub.2) is biased to present the high-impedance load.

Claims

1. An electronic circuit configured to present a high-impedance load between a load point and a reference point (further referred to as the high-impedance electronic circuit), the high-impedance electronic circuit including: a capacitive element (C) provided between a first node (Node A) and the reference point; a first element having a non-linear voltage-to-current relationship (D.sub.1) connected in parallel with the capacitive element (C) between the first node (A) and the reference point; a first switching element (S.sub.1) provided in series between the first node (A) and a voltage source point; a second switching element (S.sub.2) provided between the first node (A) and a second node (Node B); and a second element having a non-linear voltage-to-current relationship (D.sub.2) connected between the second switching element (S.sub.2), the load point, and the reference point; and timing control logic configured to control the first switching element (S.sub.1) and the second switching element (S.sub.2) to bias the second element (D.sub.2) to operate in at least three stages comprising: a charging stage wherein the first switching element (S.sub.1) is closed and the second switching element (S.sub.2) is open for a charging duration (T.sub.CH) to enable the capacitive element (C) to charge a nodal voltage v.sub.D(t) at the first node (A) to a pre-defined initial voltage threshold V.sub.i; a discharge stage wherein the first switching element (S.sub.1) is open and the second switching element (S.sub.2) is open for a discharge duration (T.sub.DCH) to enable discharging of the capacitive element (C) through the first element (D.sub.1) such that a current through the first element (D.sub.1) reaches a pre-defined bias current (I.sub.BIAS) and/or the nodal voltage v.sub.D(t=T.sub.CH+T.sub.DCH) equals a pre-defined bias voltage (V.sub.BIAS); and a transfer stage in which the second switching element (S.sub.2) is closed for a transfer duration (T.sub.XFR) to connect the first node (A) and the second node (B), thereby to apply or transfer the bias voltage (V.sub.BIAS) to a contact of the second element (D.sub.2) connected to the second node (B) to bias the second element (D.sub.2) according to the bias voltage (V.sub.BIAS); wherein the timing control logic is configured to open the second switching element (S.sub.2) after the transfer stage, the second element (D.sub.2) being biased to present the high-impedance load between the load point and the reference point.

2. The electronic circuit as claimed in claim 1, in which the first and second elements (D.sub.1, D.sub.2) are diodes or transistors.

3. The electronic circuit as claimed in claim 2, in which the first element (D.sub.1) is a diode-connected transistor and the second element (D.sub.2) is a transistor.

4. The electronic circuit as claimed in claim 3, in which: the first and second elements (D.sub.1, D.sub.2) are MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors); the first and second elements (D.sub.1, D.sub.2) are BJTs (Bipolar Junction Transistors); the first element (D.sub.1) is a BJT and the second element (D.sub.2) is a MOSFET; or the first element (D.sub.1) is a diode and the second element (D.sub.2) is a BJT.

5. The electronic circuit as claimed in claim 1, in which the first and second elements (D.sub.1, D.sub.2) have related voltage-current relationships.

6. The electronic circuit as claimed in claim 1, in which the transfer duration T.sub.XFR is calculated to transfer the voltage V.sub.D(t) between the first node (A) and the second node (B) using the second switching element (S.sub.2) and to keep the capacitive element (C) charged to ensure that the bias point voltage on the second node (B) of the second element (D.sub.2) remains above ground potential (0 V).

7. The electronic circuit as claimed in claim 1, in which the timing control logic is configured to repeat the charging stage, discharging stage, and transfer stage periodically or intermittently.

8. The electronic circuit as claimed in claim 7, in which the timing control logic is configured to repeat the charging stage, discharging stage and transfer stage at a frequency depending on the load voltage v.sub.L.

9. The electronic circuit as claimed in claim 8, in which the timing control logic is configured to keep a ratio v.sub.L/i.sub.L constant in order to establish a constant real impedance.

10. The electronic circuit as claimed in claim 1, which is, or which forms part of, an Integrated Circuit (IC).

11. A method of generating a high-impedance load between a load point and a reference point (further referred to as the high-impedance electronic circuit), the method comprising: providing a high-impedance electronic circuit including: a capacitive element (C) provided between a first node (Node A) and the reference point; a first element having a non-linear voltage-to-current relationship (D.sub.1) connected in parallel with the capacitive element (C) between the first node (A) and the reference point; a first switching element (S.sub.1) provided in series between the first node (A) and a voltage source point; a second switching element (S.sub.2) provided between the first node (A) and a second node (Node B); and a second element having a non-linear voltage-to-current relationship (D.sub.2) connected between the second switching element (S.sub.2), the load point, and the reference point; and timing control logic configured to actuate the first switching element (S.sub.1) and the second switching element (S.sub.2) to bias the second element (D.sub.2) in at least three stages, the method further comprising: charging the capacitive element (C), during a charging stage wherein the first switching element (S.sub.1) is closed and the second switching element (S.sub.2) is open for a charging duration (T.sub.CH), to a nodal voltage v.sub.D(t) at the first node (A) to a sufficient or pre-defined initial voltage threshold V.sub.i; discharging the capacitive element (C), during a discharge stage wherein the first switching element (S.sub.1) is open and the second switching element (S.sub.2) is open for a discharge duration (T.sub.DCH), through the first element (D.sub.1) such that a current through the first element (D.sub.1) reaches a sufficient or pre-defined bias current (I.sub.BIAS) and/or the nodal voltage v.sub.D(t=T.sub.CH+T.sub.DCH) equals a sufficient or pre-defined bias voltage (V.sub.BIAS); transferring the bias voltage (V.sub.BIAS), during a transfer stage in which the second switching element (S.sub.2) is closed for a transfer duration (T.sub.XFR) to connect the first node (A) and the second node (B), to a contact of the second element (D.sub.2) connected to the second node (B) to bias the second element (D.sub.2) according to the bias voltage (V.sub.BIAS); and opening the second switching element (S.sub.2) after the transfer stage, the second element (D.sub.2) being biased to present the high-impedance load between the load point and the reference point.

12. The method as claimed in claim 11, in which the charging stage, discharging stage, and transfer stage are repeated periodically or intermittently.

13. The method as claimed in claim 12, in which the charging stage, discharging stage, and transfer stage are repeated at a frequency depending on the load voltage v.sub.L.

14. The method as claimed in claim 13, which includes keeping a ratio v.sub.L/i.sub.L constant in order to establish a constant real impedance.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0062] The invention will now be further described, by way of example, with reference to the accompanying diagrammatic drawings.

[0063] In the drawings:

[0064] FIG. 1 shows a schematic circuit diagram of a PRIOR ART circuit, showing capacitive discharge through a diode, of Reference [1];

[0065] FIG. 2 shows a schematic circuit diagram with the diode in FIG. 1 replaced with a transistor;

[0066] FIG. 3 shows a schematic circuit diagram of an electronic circuit configured to generate a high-impedance load, in accordance with the invention;

[0067] FIG. 4 shows a graph of various stages of operation of the electronic circuit of FIG. 3 and timing signals on switches;

[0068] FIG. 5 shows a schematic circuit diagram of another embodiment of an electronic circuit configured to generate a high-impedance load, in accordance with the invention; and

[0069] FIG. 6 shows a schematic circuit diagram of a further embodiment of an electronic circuit configured to generate a high-impedance load, in accordance with the invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENT

[0070] The present invention will be described first with reference to some enabling theory and then with reference to a practical implementation of that theory.

[0071] This invention proposes that the above-mentioned characteristics of non-linear elements (e.g., MOS transistors, diodes and BJTs) can be used to create high-impedance terminating elements. An aspect of this invention pertains to the method with which such a high-impedance element can be biased in an appropriate region of operation to yield the intended results.

[0072] The present invention builds on the phenomenon explained in Equation (1) and FIG. 1 by noting that, if the calculation is rewritten in terms of the diode current i.sub.D(t), it can be shown that

[00002]$\begin{array}{cc}{i}_D\left(t\right)\approx m{V}_T\frac{C}{t}& \left(2\right)\end{array}$

[0073] for currents much larger than I.sub.0. This is significant since the result shows that for a capacitor discharging through a forward-biased diode, the diode current only depends on the total nodal capacitance C and time t.

[0074] This result can be extended to MOS transistors by analysing the circuit in FIG. 2, where the diode of FIG. 1 is replaced by a diode-connected NMOS (n-type MOS) transistor.

[0075] It can be shown that, where the term t/C and the nodal voltage v.sub.D(t) (from Equation (1)) are appropriately constrained, the current through the MOS transistor follows the expression

[00003]$\begin{array}{cc}{i}_D\left(t\right)\approx n{V}_T{e}^{\left(\frac{-V_t}{{\mathrm{nV}}_T}\right)}\frac{C}{t}& \left(3\right)\end{array}$

[0076] where n is a technology constant, V.sub.T is the thermal voltage, V.sub.t is the MOS transistor's threshold voltage and C represents the nodal capacitance.

[0077] To generalize both cases, Equations (2) and (3) can be rewritten and interpreted as

[00004]$\begin{array}{cc}{i}_D\left(t\right)=k\frac{C}{t}& \left(4\right)\end{array}$

[0078] where k is a technology constant, C the capacitance being discharged and t the time. The resulting Equation (4) yields an unexpected insight that it is possible to set the discharge current, and consequently the operating point of the device or circuit, by choosing only C and an appropriate t.

[0079] The present invention discloses that the characteristics described above, resulting in Equation (4), may be used in a unique way to establish a well-controlled bias point for a device to serve as a high-impedance element.

[0080] This can be illustrated using a typical field effect transistor, such as an NMOS transistor, as would normally be available to a circuit designer implementing a design using a CMOS fabrication process. The device has four terminals comprising a gate (G), drain (D), source (S) and bulk (B). In strong inversion operation, the gate-source voltage V.sub.GS>V.sub.t, while with subthreshold operation it is required that V.sub.GS<V.sub.t. It is known that in the subthreshold region the device has a significantly higher output impedance between the drain-source terminal than in strong inversion.

[0081] Referring again to the circuit in FIG. 2, the capacitor may start with an initial voltage V.sub.i at t=0 that is well above the threshold voltage V.sub.t of the device. Since V.sub.GS=V.sub.DS>V.sub.t, the device starts in strong inversion and within a very short time; the device discharges so that V.sub.GS drops below V.sub.t. In a typical 0.35 μm CMOS process, given a reasonable value for C, this happens within a few hundred nanoseconds or less. Once V.sub.GS is lower than V.sub.t, the transistor enters its subthreshold region of operation and the rate of discharge becomes significantly slower. From Equation (3), generalized as Equation (4), the magnitude of the current becomes dependent only on time t, the nodal capacitance C and a technology or device constant k.

[0082] By using Equation (4) and choosing a target MOS element bias current I.sub.BIAS (which may be considered as i.sub.D(t=T.sub.CH+T.sub.DCH)) while selecting C, it is possible to determine the required discharge time T.sub.DCH so that i.sub.D(t=T.sub.CH+T.sub.DCH)=I.sub.BIAS and conversely it is possible to determine a C value for a predefined T.sub.DCH, given that an initial voltage was present on the node so that v.sub.D(t=T.sub.CH)=V.sub.i.

[0083] Since the discharging device is used to establish I.sub.BIAS, the same device cannot be used to act as a high-impedance circuit element by itself. However, the gate-source voltage V.sub.GS of the transistor associated with the current i.sub.D(t=T.sub.CH+T.sub.DCH) can now be used to replicate the bias point of the transistor by “copying” the gate voltage to another, second, MOS transistor. If the second transistor is sized the same, and operating under the same conditions on its terminals, the second transistor can be employed as the intended high-impedance circuit element by considering the behaviour between its drain and source terminal. Since it is known from Gray [2] for subthreshold operation that

[00005]$\begin{array}{cc}{I}_D=\frac{W}{L}{I}_t{e}^{\left(\frac{V_{GS}-V_t}{{\mathrm{nV}}_T}\right)}\left[1-e^{\left(-\frac{V_{DS}}{V_T}\right)}\right]& \left(5\right)\end{array}$

[0084] which shows that, for V.sub.DS»V.sub.T, the output current remains largely constant for a given V.sub.GS and the small-signal output impedance is shown, excluding drain-induced barrier lowering and body effects, to be

[00006]$\begin{array}{cc}{r}_{DS}=\frac{\partial V_{DS}}{\partial I_D}=\frac{V_T}{\frac{W}{L}{e}^{\left(\frac{V_{\mathrm{GS}}-V_t}{{\mathrm{nV}}_T}\right)}-I_D}& \left(6\right)\end{array}$

[0085] for a constant V.sub.GS that, although non-linear, can realize very large impedances (for small signals). Alternatively, the terminating element can be used to create very small but predictable and well-controlled currents using this approach.

[0086] Similar behaviour can be expected from a bipolar junction transistor (BJT). Equation (2) can be adapted for a BJT by including the forward current gain term β where i.sub.C=βi.sub.B and noting that the total current is i.sub.D=(β+1)i.sub.B, while the small signal output impedance of a BJT can be approximated as

[00007]$\begin{array}{cc}{r}_{CE}=\frac{V_A}{I_C}& \left(7\right)\end{array}$

[0087] where V.sub.A is the Early-voltage associated with a specific device. r.sub.CE may become very large for very low values of I.sub.C that are expected from making use of Equation (2) with appropriate choices for C and t.

[0088] Turning now to a practical or technical implementation of the above theory, FIG. 3 illustrates an example electronic circuit 100 configured to generate a high-impedance load, in accordance with the invention. The electronic circuit 100 may be configured in light of conclusions made from Equation (4) to implement a high-impedance element or load. In the drawings, the reference point is illustrated as a ground point.

[0089] This example illustrates the electronic circuit 100 using an active element (D.sub.1) with a non-linear voltage-to-current relationship in the form of an NMOS transistor, but other implementations are practicable (see below). The electronic circuit 100 may comprise three conceptual sections, each serving a particular purpose during various stages of operation. [0090] 1. A first section (Section 1) of the electronic circuit 100 that generates a voltage signal that can be used to bias a transistor in subthreshold or low current region depending on the required load impedance Δv.sub.L/Δi.sub.L or load current bias point i.sub.L. [0091] 2. A second section (Section 2) of the electronic circuit 100 that transfers the bias point voltage signal on node A of the first section of the circuit to node B of the third section. [0092] 3. A third section (Section 3) of the electronic circuit 100 containing the element that utilizes the transferred voltage signal to bias a transistor in a way to establish a high-impedance load as seen from the behaviour of v.sub.L (which is the voltage at the load point) and i.sub.L. Section 3, after the transfer stage, presents a high-impedance load, as represented by R.sub.EFF in circuit 110.

[0093] Sections 1 and 2 may be considered a biasing portion of the circuit 100 while the third section is the load-presenting section.

[0094] During design, a circuit designer must choose the target current setpoint I.sub.BIAS for transistor D.sub.1 or required small-signal impedance using Equations (4) and/or (6) and then derive values for the capacitance C and the discharge duration T.sub.DCH.

[0095] The first section of the electronic circuit 100 comprises three main elements: [0096] an element which may be an active element such as a transistor or diode, D.sub.1 in FIG. 3, either n-type or p-type depending on the exact circuit implementation; [0097] a capacitive element (C), typically a capacitor and the parasitic capacitance on node A in FIG. 3, and [0098] a switching element, S.sub.1 in FIG. 3, that can connect and disconnect the capacitive element from a power source so that an initial voltage can be set or established on the node.

[0099] FIG. 4 shows a graph 200 illustrating the different stages of circuit operation that enables D.sub.2 in FIG. 3 to act as a high-impedance element as described above. The timing signals that close S.sub.1 and S.sub.2 are also indicated.

[0100] The four stages of the circuit operation in FIG. 4 can be explained as: [0101] 1. Stage 1 (charging): During this stage 1, a switch S.sub.1 connects the charge storing node to a charging source, usually a power supply rail and possibly through a resistive element to limit the inrush current to the storage element, while switch S.sub.2 is open. The charging stage duration T.sub.CH should be long enough to ensure that the nodal voltage v.sub.D(t) reaches a level sufficiently high so that Equation (2) is valid for a diode or bipolar transistor or Equation (3) for a diode-connected MOS device. Although a small current will flow through the discharge element, the NMOS transistor D.sub.1 in FIG. 3, it should be negligible compared to the charging current flowing through S.sub.1. Once a sufficient initial voltage v.sub.D(t=T.sub.CH)=V.sub.i is reached, the switch S.sub.1 opens, where T.sub.CH marks the duration of the charging stage and the next stage commences.

[0102] 2. Stage 2 (discharge) During this stage 2, S.sub.1 and S.sub.2 are both open and v.sub.D(t=T.sub.CH)=V.sub.i is the initial voltage on node A at the onset of the discharge stage. The first part of the circuit now follows the behaviour of general Equation (4) with the charge stored on node A discharging through the element, the diode-connected NMOS D.sub.1 in FIG. 3. Depending on the parameters the designer chose, the duration of this stage should be T.sub.DCH at which the current through D.sub.1 will reach the target value of I.sub.BIAS with a nodal voltage v.sub.D(t=T.sub.CH+T.sub.DCH)=V.sub.BIAS. [0103] 3. Stage 3 (transfer): At the end of the discharge stage, switch S.sub.2 closes in order to transfer the voltage on node A, V.sub.BIAS, to node B. Ideally, the voltage on node B is now equal to the voltage on node A and will persist after S.sub.2 opens, although this may take plural repetitions to occur. For the example in FIG. 3 V.sub.BIAS would now be present on the gate of D.sub.2 and thereby bias the device according to Equations (5) and (6) to act as the intended high-impedance circuit element, e.g., between its drain and source terminals. The duration of this stage 3 T.sub.XFR, with S.sub.2 being closed, should be sufficiently long for effective voltage transfer between nodes A and B, but not too long to unreasonably influence the discharge circuit and bias point. The transfer stage ends when switch S.sub.2 opens. A total node capacitance on node B should be high enough to retain this voltage and inhibit discharge (and voltage drop/change) during the time when S.sub.2 is open. [0104] 4. Stage 4 (idle stage): After the bias point was transferred to the load device D.sub.2, the system may enter an optional idle stage 4 for a duration of T.sub.IDLE, depending on the exact implementation of the timing signals, before commencing the next charging stage. For most cases, T.sub.IDLE will likely be zero. This stage may be optional. [0105] 5. Repeating the process to establish and maintain bias: In order to establish and maintain the bias point the three stages above need to be repeated periodically or intermittently to maintain an accurate V.sub.BIAS, especially when using bipolar devices with non-negligible base currents influencing the setpoint on node B. In addition, when first establishing the bias point, node B may require multiple cycles of charge transfer from node A before settling on or around the intended bias voltage V.sub.BIAS, due to the capacitance ratio of node A to node B. The initial condition of each of the repeating cycles is v.sub.D(t=T.sub.CH)=V.sub.i that therefore allows v.sub.D(t=T.sub.CH+T.sub.DCH)=V.sub.BIAS to settle after multiple cycles allowing a stable high-impedance operating point to be applied to D.sub.2. The timing control logic may be configured to repeat the charging stage, discharging stage, and transfer.

[0106] Other variations of the electronic device 100 are possible, as illustrated in FIGS. 5-6. The first variation from the circuit shown in FIG. 3 is that the two NMOS transistors may be implemented using bipolar junction devices (BJTs) and adapting the circuit for the necessary changes in behaviour, such as the continued presence of base currents, as shown in FIG. 5 as electronic device 300, in accordance with the invention. Such adaptation may require adding capacitance in addition to any existing parasitic capacitance to node B for sustaining these currents while maintaining the nodal voltage.

[0107] The second variation from the circuit shown in FIG. 3 is that the transistors, either MOS or BJT devices or combination thereof, may be implemented by either n-type or p-type devices by adapting the circuit and associated polarities accordingly.

[0108] While the method of circuit operation described in the preceding section focuses on using the discharge time T.sub.DCH as the determining factor when interpreting Equation (4), it should be noted that Equation (4) can also be amended to express I.sub.BIAS, the bias current through D.sub.1 as on t=T.sub.CH+T.sub.DCH in terms of frequency as

I.sub.BIAS(f)=kCf   (8)

where, for each period the voltage on node A starts at a repeatable initial voltage V.sub.i and f=1/(T.sub.CH+T.sub.DCH+T.sub.XFR) when omitting the idle stage. The frequency f can be changed by changing the respective durations of each stage accordingly.

[0109] The circuit of FIG. 3, and similar circuits in general, may be adapted so that device D.sub.1 is geometrically different from device D.sub.2 so that the ultimate current through D.sub.2 is a scaled version of the current through D.sub.1. For example, suppose for FIG. 3 the (W/L)—ratio of D.sub.2 over D.sub.1 is 2, then D.sub.2 would conduct approximately twice the current for given V.sub.BIAS than D.sub.1—that is, i.sub.L=2I.sub.BIAS. In this way, geometrical adaptations to the devices may be made to compensate or fine-tune the current of the high impedance terminating element D.sub.2 for different applications. For BJTs, the emitter area can be scaled to the same effect.

[0110] While D.sub.2 presents a very high small-signal impedance for a given operating bias point, such an impedance is non-linear as the voltage v.sub.L on the drain (for field-effect transistors) or collector (for bipolar transistors) of D.sub.2 changes. In another variation it is possible to dynamically compensate for this by adapting T.sub.DCH in absolute terms as illustrated in diagram 400 in FIG. 6. For a fixed repeating period of T.sub.TOTAL=T.sub.CH+T.sub.DCH+T.sub.XFR+T.sub.IDLE=1/f, T.sub.DCH may be adapted in isolation by appropriately adjusting the switching signals of S.sub.1 and S.sub.2. The frequency f may also be dynamically adapted, thereby implicitly changing T.sub.DCH to accommodate for changes in v.sub.L and consequently R.sub.EFF shown in FIG. 3 in order to keep the value of R.sub.EFF relatively constant.

[0111] The Applicant believes that the invention as exemplified is advantageous in that the circuit 100, 300, 400 can be fabricated using cost-effective, industry standard manufacturing processes such as silicon-based CMOS (complementary metal-oxide-semiconductor). The circuit 100, 300, 400 finds application in read-out circuits of passive infrared (PIR) sensors and other sensors.

[0112] The invention as described provides a new way to create a high-impedance terminating element that fulfils the requirements for such a circuit 100, 300, 400 as part of a sensor circuit front-end. As an added advantage, the circuit 100, 300, 400 and method described enables a highly dynamic and adaptable solution that can form part of modern-day high-performance integrated circuits in a cost-effective way.

REFERENCES

[0113] [1] Hellen, E. H., “Verifying the diode-capacitor circuit voltage delay”, American Journal of Physics, Vol. 71, no. 8, 10 Jul. 2003. [0114] [2] Grey, P. R., et al, “Analysis and design of analog integrated circuits”, 4.sup.th edition, John Wiley and Sons, Inc., 2001.