Method for programming a resistive random access memory

Abstract

A method for programming a resistive random access memory including a matrix of memory cells. This method includes a programming procedure that includes applying a programming voltage ramp to the memory cells of a part at least of the matrix, the programming voltage ramp starting at a first non-zero voltage value, called start voltage, and ending at a second voltage value, called stop voltage, greater in absolute value than the first voltage value. The stop voltage is determined such that each memory cell of said at least one part of the matrix has a first probability between 1/(10N) and 1/N of having a programming voltage greater in absolute value than the stop voltage (V.sub.stop), N being the number of memory cells in the at least one part of the matrix.

Claims

1. A method for programming a resistive random access memory comprising a matrix of memory cells, comprising a programming step that includes applying a programming voltage ramp to the memory cells of a part at least of the matrix, the programming voltage ramp starting at a start voltage having a first non-zero voltage value and ending at a stop voltage having a second voltage value greater in absolute value than the first voltage value, wherein the stop voltage is determined such that each memory cell of said at least one part of the matrix has a first probability comprised between 1/(10N) and 1/N of having a programming voltage greater in absolute value than the stop voltage, N being the number of memory cells in said at least one part of the matrix.

2. The method according to claim 1, wherein the stop voltage is determined from a distribution of programming voltages of a sample of memory cells, said distribution obeying a normal law.

3. The method according to claim 1, wherein the start voltage is determined such that each memory cell of said at least one part of the matrix has a second probability comprised between 1/(10N) and 1/N of having a programming voltage less in absolute value than the start voltage.

4. The method according to claim 3, wherein the start voltage is determined from a distribution of programming voltages of a sample of memory cells, said distribution obeying a normal law.

5. The method according to claim 3, wherein the first probability and the second probability are equal.

6. The method according to claim 5, wherein the first probability and the second probability are equal to 1/N.

7. The method according to claim 3, initially comprising a calibration step to determine the start voltage and the stop voltage of the programming voltage ramp, knowing the number N of memory cells in said at least one part of the matrix, said calibration step comprising the following operations: providing a plurality of reference memory cells identical to the memory cells of the matrix; measuring, for each reference memory cell, a voltage value at which said reference memory cell is programmed; establishing a distribution law from the programming voltage values of the reference memory cells; and determining, using the distribution law, the stop voltage corresponding to the first probability and the start voltage corresponding to the second probability.

8. The method according to claim 7, wherein the programming voltage value of each reference memory cell is measured by applying to said reference memory cell a characterization voltage ramp, the characterization voltage ramp comprising successive voltage stages, and by measuring during successive voltage stages a current passing through said memory cell.

9. The method according to claim 1, wherein the programming voltage ramp comprises successive voltage stages.

10. Electronic device comprising means for implementing the programming method according to claim 1.

11. A method for programming a resistive random access memory comprising a matrix of memory cells, said method comprising: a preliminary step of characterization of a plurality of reference memory cells, making it possible to measure a programming voltage value for each reference memory cell; a step of statistical adjustment of the programming voltage values, making it possible to establish a probability law followed by the memory cells of the matrix; a step of determining a programming voltage value at which a predetermined number of memory cells of the matrix is programmed, according to the probability law; a step of applying the programming voltage value at which a predetermined number of memory cells of the matrix is programmed to the memory cells of the matrix.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) Other characteristics and advantages of the invention will become clear from the description that is given thereof below, for indicative purposes and in no way limiting, with reference to the appended figures, among which:

(2) FIGS. 1A and 1B, described previously, represent two methods for programming a resistive memory cell according to the prior art;

(3) FIG. 2, described previously, represents the distribution of the programming times of a plurality of OxRAM memory cells programmed according to the method of FIG. 1A;

(4) FIG. 3 represents the current-voltage characteristics of a plurality of OxRAM memory cells programmed according to the method of FIG. 1B;

(5) FIG. 4 shows a voltage ramp applied to resistive random access memory cells, during a programming method according to a preferential embodiment of the invention;

(6) FIG. 5 represents an exemplary embodiment of a preliminary step of the programming method according to the invention, in order to determine the start voltage and the stop voltage of the ramp of FIG. 4;

(7) FIG. 6 represents the distribution of the programming times of a plurality of OxRAM memory cells programmed according to the method of the invention and according to the method of FIG. 1A; and

(8) FIG. 7 represents the distribution of the resistances in the state LRS and in the state HRS of two OxRAM memory cells programmed according to the method of the invention and according to the method of FIG. 1B.

(9) For greater clarity, identical or similar elements are marked by identical reference signs in all of the figures.

DETAILED DESCRIPTION OF AT LEAST ONE EMBODIMENT

(10) In the following description, programming designates the operation consisting in making a resistive random access memory (RRAM) cell switch reversibly between a high resistance state called HRS and a low resistance state called LRS. When the resistive memory cell passes from the state HRS to the state LRS, the corresponding programming operation is called writing or set. Conversely, when the resistive memory cell passes from the state LRS to the state HRS, the corresponding programming operation is called erasing or reset. A programming operation may thus be either a writing operation, or an erasing operation.

(11) The resistive memory cell has in the state HRS an electrical resistance value R.sub.HRS above a first resistance threshold and in the state LRS an electrical resistance value R.sub.LRS below a second resistance threshold. The second resistance threshold is lower than the first resistance threshold. The difference between the first and second resistance thresholds is commonly called programming window of the memory cell.

(12) FIG. 3 shows as an example the current-voltage (I-V) characteristics of a group of memory cells programmed in the state LRS by the RVS method of FIG. 1B. These memory cells are of OxRAM (Oxide-based Random Access Memory) type and comprise successively an upper electrode made of nickel, a dielectric layer made of hafnium oxide and a lower electrode made of doped silicon (i.e. stack of Ni/HfO.sub.2/p.sup.+-Si type). The voltage ramp that has been applied to these memory cells starts at a voltage of 0.1 V and increases by stages of 100 mV at a constant rate of 1.9 MV.Math.s.sup.1 up to a maximum voltage V.sub.max, for example 7.5 V.

(13) As indicated previously, the passage from the state HRS to the state LRS (writing) of a resistive memory cell is reflected in its I-V characteristic by an abrupt increase in the electrical current. To avoid a too important increase in temperature and a destruction of the memory cells, a compliance current has been set at 1 mA.

(14) In this example, the fastest memory cell of the group is programmed at a first voltage V.sub.prog_1 of around 3.5 V and the slowest memory cell of the group is programmed at a final voltage V.sub.prog_n of around 6.8 V.

(15) The portion 30 of the I-V characteristic that precedes the abrupt increase in the current does not contribute to the programming of the memory cell and thus represents a loss of time and energy. In other words, the part of the voltage ramp comprised between the first voltage stage at 0.1 V and the first programming voltage V.sub.prog_1 (here 3.5 V) represents useless electrical stress for the memory cells and the time that the voltage ramp takes to reach this first programming voltage V.sub.prog1 is a superfluous programming time.

(16) In an analogous manner, it may be observed in FIG. 3 that an important voltage difference separates the programming voltage (V.sub.prog_n=6.8 V) of the last memory cell (i.e. the slowest to program) and the maximum voltage of the programming ramp (7.5 V). This voltage difference also represents a loss of time and a useless electrical stress, because all the cells have already been programmed.

(17) On the basis of these observations, the inventors have developed a novel method for programming a resistive random access memory. This programming method applies to any type of resistive random access memory of which the cells may be programmed collectively by applying thereto a voltage. The resistive random access memory is for example a PCRAM (Phase-Change Random Access Memory), a CBRAM (Conductive-Bridging Random Access Memory) or an OxRAM (Oxide-based Random Access Memory). Conventionally, the resistive random access memory comprises a plurality of memory cells arranged in lines and in columns, in the form of a matrix. Each memory cell comprises a first electrode, a second electrode and a layer of a dielectric material with variable electrical resistance arranged between the first and second electrodes. The electrodes and the dielectric material layer are generally stacked one upon another. The terms upper electrode and lower electrode are thus also used hereafter.

(18) FIG. 4 schematically illustrates a preferential embodiment of the programming method according to the invention.

(19) The programming method comprises a programming step consisting in applying to several memory cells of the matrix a same voltage ramp 40. The voltage ramp 40 may be applied to all of the memory cells of the matrix or to only a part of the matrix. In the following description, the example of a block of memory cells is taken. A block of memory cells designates a sub-matrix of memory cells, that is to say a group of memory cells arranged in lines and in columns, the number of lines of the block being less than the number of lines of the matrix and/or the number of columns of the block being less than the number of columns of the matrix. A block of memory cells contains for example 4096 memory cells distributed in 256 lines and 16 columns.

(20) The programming step may be a step of writing or a step of erasing the block of memory cells, as a function of the sign of the voltage applied between the electrodes of the memory cells. Typically, a positive voltage ramp, increasing, is applied between the electrodes to write the memory cell (cf. FIG. 4) and a negative voltage ramp, decreasing, is applied between the electrodes to erase the memory cell.

(21) The voltage ramp 40 is preferably in staircase form, that is to say that it comprises a succession of voltage stages 41. These voltage stages 41 make it possible to stress the memory cells and, if needs be, to measure the current that passes through the memory cells during programming. The ramp rate (equal to the voltage step V between two successive stages 41 divided by the duration V of the stages 41) is chosen notably as a function of the desired programming rate. The higher this ramp, the shorter the programming time t.sub.prog of each memory cell but, on the other hand, the higher the programming voltage V.sub.prog. The ramp rate 40 is for example comprised between 15 kV.Math.s.sup.1 and 140 kV.Math.s.sup.1.

(22) The voltage ramp 40 starts (at the instant t.sub.start) at a first non-zero voltage value V.sub.start, called start voltage, and ends (at the instant t.sub.stop) at a second voltage value V.sub.stop, called stop voltage. The stop voltage V.sub.stop is greater in absolute value than the start voltage V.sub.start.

(23) The stop voltage V.sub.stop of the ramp 40 is determined from a first probability that each memory cell of the block has a programming voltage greater than the stop voltage V.sub.stop of the ramp, in other words from a first probability that each memory cell is not programmed at the stop voltage V.sub.stop. This first probability is a function of the size of the block of memory cells to program, that is to say the number N of memory cells in the block. The first probability is chosen between 1/(10N) and 1/N (limits included), preferably between 1/(2N) and 1/N (limits included). With such a probability, the number of cells risking not being programmed is statistically 1 at the most. The stop voltage V.sub.stop is thereby brought back to a value close to the programming voltage of the slowest memory cell of the block, rather than set at an excessively high value (V.sub.max).

(24) In a preferential embodiment of FIG. 4, the start voltage V.sub.start of the ramp 40 is a non-zero voltage value well above the voltage step V used in the RVS method of the prior art, close to the programming voltage of the fastest memory cell of the block. It is determined from a second probability that each memory cell of the block has a programming voltage below the start voltage V.sub.start of the ramp. Like the first probability, this second probability is a function of the number N of memory cells in the block. The second probability is comprised between 1/(10N) and 1/N (limits included), preferably between 1/(2N) and 1/N (limits included). With such a probability, the number of cells risking being programmed at a voltage value (V.sub.start) greater than their real programming voltage is statistically 1 at the most.

(25) The stop voltage V.sub.stop of the ramp 40 is preferably determined during a preliminary step called calibration step from a distribution of programming voltages. This distribution of programming voltages may be established from a sample of memory cells. The start voltage V.sub.start may also be determined from a distribution of programming voltages if it is sought to optimize the start point of the ramp.

(26) To begin, the calibration step comprises the selection of a number N.sub.ref of reference memory cells. The reference memory cells are memory cells identical to the memory cells of the block to program, that is to say of same size and comprising the same stack of active layers (upper electrode, resistive material and lower electrode). The reference memory cells may be chosen within the resistive random access memory to which the block to program belongs or another resistive random access memory. The reference memory cells may also be unitary devices and thus not be arranged in lines and in columns like the memory cells of the block to program.

(27) In order to obtain a distribution representative of a matrix of memory cells and reliable statistics, the number N.sub.ref of reference memory cells is advantageously greater than or equal to 70, preferably greater than equal to 100.

(28) The calibration step next comprises an operation consisting in measuring the programming voltage value V.sub.prog of each reference memory cell. Preferably, the RVS characterization technique described in relation with FIG. 1B is used to measure the programming voltage V.sub.prog of each reference memory cell. As indicated previously, this technique consists in applying to each reference memory cell a so-called characterization voltage ramp until a predetermined current level is obtained, for example equal to 1 mA. This characterization voltage ramp comprises sufficiently long successive voltage stages to enable several measurements of the electrical current. The voltage ramp rate is for example equal to 140 kV/s. Several programming voltage values V.sub.prog are obtained at the end of this measuring operation.

(29) The distribution of the programming voltage values V.sub.prog may next be represented on a graph, for example of the type of FIG. 5, by plotting on the X-axis the programming voltage V.sub.prog and the quantities on the Y-axis. The Y-axis scale of FIG. 5 is a gaussian-arithmetic scale, which can represent the cumulative number in percentages or percentiles (on the left in FIG. 5) or quantiles in number of a units (on the right in FIG. 5, being the standard deviation of the distribution law). The median value, obtained at 50% where 0 , corresponds to half of the reference memory cells. For example, 50% of the reference memory cells here have a programming voltage less than 0.6 V.

(30) In the example of FIG. 5, the number of reference memory cells is equal to 100. The fastest memory cell is programmed at a voltage of 0.5 V and the slowest memory cell is programmed at a voltage of 0.75 V. All of the measured programming voltage values V.sub.prog are comprised between 0.5 V and 0.75 V. A voltage ramp 40 starting at 0.5 V and ending at 0.75 V would thus make it possible to program simultaneously these 100 reference memory cells.

(31) By performing a statistical adjustment of the programming voltage values V.sub.prog, it is observed that the programming voltage V.sub.prog obeys a normal distribution law. This normal distribution law is represented by a straight line 50 (known as a Henry line) in FIG. 5.

(32) The straight line 50 gives the tendency that the memory cells of one type in particular follow. Once established, it makes it possible to determine the start voltage V.sub.start and the stop voltage V.sub.stop of the programming ramp 40 whatever the size of the block (or matrix) to program, that is to say whatever the number N of memory cells of this type in the block (or the matrix), without having need to characterize them all.

(33) Indeed, each size of matrix (for example 16 Kb, 1 Mb, 1 Gb, etc.) corresponds to cumulative numbers of memory cells (in percentage) or quantiles (in number of a units, i.e. n* where n is a natural integer, positive or negative) which make it possible, using the normal distribution law 50, to determine the corresponding start voltage V.sub.start and stop voltage V.sub.stop. These numbers or quantiles are calculated from the first and second probabilities defined above.

(34) For example, in the case of a block of 16 Kb, i.e. 16384 memory cells, a first probability equal to 1/N is considered to determine the stop voltage V.sub.stop (i.e. it is allowed that one out of the N memory cells has a programming voltage greater than V.sub.stop) and a second probability also of 1/N to determine the start voltage V.sub.start (i.e. it is allowed that one out of the N memory cells has a programming voltage less than V.sub.start). The percentage of memory cells having a programming voltage greater than the stop voltage V.sub.stop (i.e. the allowed programming error rate) is thus equal to 0.0061% (1/16384*100) and the percentage of memory cells having a programming voltage less than the start voltage V.sub.start is also equal to 0.0061%. The percentage of memory cells having a programming voltage less than V.sub.stop (i.e. the targeted programming rate) is equal to 99.9939% (100%0.0061%). The percentage interval [0.0061%99.9939%] corresponds to a deviation around the average value of 4 . According to the distribution law 50, the start voltage V.sub.start corresponding to 4 (or 0.0061%) is equal to 0.45 V and the stop voltage V.sub.stop corresponding to +4 (or 99.9939%) is equal to 0.8 V. A voltage ramp 40 between 0.45 V and 0.8 V will thus make it possible to program (rapidly and while minimizing stresses) the block of 16384 memory cells (16 Kb) in one go.

(35) FIG. 6 shows the distribution of the programming time t.sub.prog obtained with 150 OxRAM cells programmed in the state LRS using the method of the invention (designated optimised RVS in the figure) and, as a comparison, the distribution of the programming time t.sub.prog obtained with these same cells when they are programmed (in the state LRS) with the CVS method of the prior art. This graph, of the same type as that of FIG. 5, represents (on the Y-axis) the number of memory cells (expressed in percentage on the left scale and in number of a on the right scale), as a function of the logarithm of the programming time t.sub.prog. The distribution of the programming time t.sub.prog globally has the form of a straight line, because the programming time t.sub.prog obeys a normal distribution law, like the programming voltage V.sub.prog (FIG. 5).

(36) It may be noted thanks to this figure that the programming method according to the invention (optimised RVS method, such as described in relation with FIGS. 4 and 5) makes it possible to tighten considerably the distribution of the programming time t.sub.prog. Indeed, for a statistic of 2 (i.e. 95% of the memory cells), the distribution extends over approximately a half-decade in the case of the method according to the invention compared to more than 3 decades for the CVS method. Furthermore, the programming time t.sub.prog at the median (i.e. at 50% or 0 ) is improved by around an order of magnitude, passing from around 10.sup.4.5 s in the case of the CVS method to 10.sup.5.6 s with the programming method according to the invention.

(37) FIG. 7 is another graph showing the distribution of the resistance values in the state LRS (R.sub.LRS) and in the state HRS (R.sub.HRS) obtained during the cycling of two OxRAM memory cells. One cell has been programmed according to the RVS method of the prior art (designated conventional RVS in the figure) and another cell has been programmed according to the method of the invention (optimised RVS). The cycling is in this example constituted of one million writing-erasing cycles separated by reading operations to measure the resistance values. This graph, of the same type as those of FIGS. 5 and 6, represents (on the Y-axis) the difference compared to the average value of the resistance values (expressed in quantiles or number of a), as a function of the electrical resistance values (in logarithmic scale on the X-axis). Since the resistance also obeys a normal distribution law, the distributions of the resistances R.sub.HRS and R.sub.LRS each globally have the form of a straight line.

(38) The optimization of the start voltage V.sub.start and the stop voltage V.sub.stop has the consequence of straightening the distributions of resistance R.sub.LRS and R.sub.HRS (the straight lines are more sloping). After 1 million programming cycles following the method of the invention, the resistance states LRS and HRS may still be distinguished, unlike the situation obtained with the conventional RVS method (where the distribution tails cross each other). The programming window may thus be respected during a greater number of cycles. These resistance distributions reflect an improvement in the reliability of the memory cell, because said cell undergoes less electrical stress during its programming thanks to the method according to the invention.

(39) To implement the programming method according to the invention, the resistive random access memory could be equipped with a supply source configured to generate a voltage ramp between the start voltage V.sub.start and the stop voltage V.sub.stop and means for applying this voltage ramp to the memory cells of the matrix, such as one or more addressing circuits, word lines and bit lines.