FREQUENCY LOCK LOOP FOR CONSTANT SWITCHING FREQUENCY OF DC-DC CONVERTERS
20230010611 · 2023-01-12
Inventors
- Jiwei Fan (Cary, NC, US)
- Yingqian Ma (Shenzhen, CN)
- Jingyuan Chen (Shenzhen, CN)
- Hal Chen (Short Hill, NJ, US)
- Jialun Du (Dublin, OH, US)
Cpc classification
H02M1/44
ELECTRICITY
Y02B70/10
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
International classification
Abstract
A frequency lock loop for a constant switching frequency of DC-DC converter, wherein the frequency lock loop includes a modulation circuit to generate a modulation signal in response to an input signal of the DC-DC converter and a frequency signal. Wherein a timer of the DC-DC converter generates a timing signal in response to the input signal, and wherein the frequency signal is a function of the timing signal.
Claims
1. A switching power supply controller comprising: a modulation circuit to generate a modulation signal in response to an input signal and a frequency signal; and a timer to generate a timing signal in response to the input signal, wherein the frequency signal is a function of the timing signal.
2. The switching power supply controller of claim 1, wherein a timer input of the timer references a reference voltage and the modulation signal.
3. The switching power supply controller of claim 2, further comprising a comparator operatively associated with the input signal and a threshold voltage, wherein an output of the comparator is connected to said timer input.
4. The switching power supply controller of claim 3, wherein the modulation circuit and the comparator comprise a frequency feedback loop operatively associated with said timer input.
5. The switching power supply controller of claim 4, wherein the timer is a constant on/off time generator.
6. A method of removing variable switching frequencies from a direct current to direct current (DC-DC) converter utilizing a constant on/off time generator, the method comprising: operatively associating the frequency feedback loop of the switching power supply controller of claim 4 with the comparator operatively having two input ports associated with the input signal and a threshold voltage, respectively, and wherein an output port of the comparator is electrically coupled to the timer of claim 4.
7. The method of claim 6, wherein the timer is a constant on/off time generator.
8. The method of claim 7, further comprising sensing a switching frequency from a pulse-width modulation; and changing the switching change to a voltage signal.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0015]
[0016]
[0017]
DETAILED DESCRIPTION OF THE INVENTION
[0018] The following detailed description is of the best currently contemplated modes of carrying out exemplary embodiments of the invention. The description is not to be taken in a limiting sense, but is made merely for the purpose of illustrating the general principles of the invention, since the scope of the invention is best defined by the appended claims.
[0019] Broadly, an embodiment of the present invention provides a frequency lock loop for a constant switching frequency of DC-DC converter, wherein the frequency lock loop includes a modulation circuit to generate a modulation signal in response to an input signal of the DC-DC converter and a frequency signal. Wherein a timer of the DC-DC converter generates a timing signal in response to the input signal, and wherein the frequency signal is a function of the timing signal.
[0020] Referring now to
[0021] DC-DC converter using constant on-time or constant off-time schemes having modulating or variable switching frequencies, wherein a timing circuit embodying control signals of a pulse-width modulation (PWM) is used to control the output of the power supplied by way of the DC-DC converter. This PWM timing circuitry may be configured to sense the switching frequency from a modulation circuit 100 input signal and generate a timing signal in response to the input signal in such a way that a frequency lock loop so that the switching frequency is affected so that the modulation circuit 100 output signal (V.sub.FSW) has the voltage level proportional to the reciprocal of the DC-DC converter's switching frequency, FSW.
[0022] Referring to
[0023] The modulation circuit 100 may further include the following: a switch, SWsample 5, which will be close at the peak of the charging voltage on Cchg 3; a capacitor, Csample 6, which will sample the peak voltage of Cchg 3; a resistor, Rfilter 7 operatively associated with a capacitor, Cfilter, 8 in such a way as to be configured as a low pass filter Rfilter-Cfilter.
[0024] The constant on-time or constant off-time schemes may be implemented by a TON/TOFF generator 10 having an input element operatively associated with a TON/TOFF comparator 9 configured to compare a Ramp voltage, which is related to VIN and the threshold voltage (Vth).
[0025] The present invention may be adapted to define a target frequency by way of generating a selectable reference voltage V.sub.REF or to a voltage value related to the reference voltage V.sub.REF.
[0026] The TON/TOFF comparator 9 may configured (or may be reconfigured for methods of improving a pre-existing DC-DC converter using constant on-time or constant off-time schemes) in such a way that the TON/TOFF comparator 9 can adjust its input offset according to the difference between V.sub.REF and V.sub.FSW.
[0027] In certain embodiments, a FSW Feedback Loop/Path or Frequency Lock Loop (FLL) may be operatively associated with the TON/TOFF comparator 9 so that the switching frequency (FSW) is affected by the TON/TOFF width generated by the TON/TOFF generator 10.
[0028] For constant TON control scheme, the FSW is determined by the following equation (ignore other small variables): FSW=VOUT/(VIN×TON). For TOFF control, FSW is determined by: FSW=(VIN−VOUT)/(VIN×TOFF).
[0029] Again, the FSW may be sensed by the PWM control signal, wherein the PWM timing block 1 generates the Tchg timing signal to control the charging/discharging of Cchg 3. The Tsample signal samples the peak voltage of Vchg and holds it with Csample 6. The Low pass filter Rfilter+Cfilter helps to compensate the FSW feedback loop and filter out the sampling noise. After the filter, V.sub.FSW and V.sub.REF are sent to TON/TOFF comparator 9 to adjust the TON/TOFF time.
[0030] One of the possible implementations of the TON/TOFF comparator 9 is shown in the
[0031] The control circuit disclosed herein may be an integrated silicon chip or build it on PCB using discrete components. Adding some circuitry for FSW frequency selection and trimming of the Ichg may make the control circuit more accurate and support more frequency options.
[0032] To use the present invention, one need adds the new FSW Feedback Loop/FLL 200 to a TON/TOFF generator 10 in the constant time DC-DC converter. The present invention can be utilized to create a DC-DC Buck Converter, a DC-DC Boost Converter, and/or a DC-DC Buck-Boost Converter.
[0033] It should be understood, of course, that the foregoing relates to exemplary embodiments of the invention and that modifications may be made without departing from the spirit and scope of the invention as set forth in the following claims.