INTEGRATED DOHERTY AMPLIFIER

Abstract

An integrated Doherty amplifier based on a multichip module structure is disclosed. The amplifier comprises an input integrated passive die including a Wilkinson power divider, a phase compensation circuit and input matching circuits for the main and peaking amplifiers based on lumped components, the active GaN HEMT die including the main device, a peaking device and a bondwire inductor connected between the drain terminals of the main and peaking devices, and an output matching network including a two-section matching circuit with low-pass and high-pass matching section operating as an impedance-transforming bandpass filter and a dc-feed power supply circuit based on lumped components and microstrip lines.

Claims

1. A Doherty amplifier including a carrier amplifier and a peak amplifier, comprising: an input splitter that evenly divides an input radio frequency (RF) signal to the carrier amplifier and the peak amplifier; an amplifying unit that includes the carrier amplifier and the peak amplifier provided on a semiconductor chip; an offset unit that includes offset transmission lines each connected with the carrier amplifier and the peak amplifier; and an output combiner that combines outputs of the carrier amplifier and the peak amplifier each provided through the offset transmission line, wherein the output combiner and the offset unit that provided on a dielectric substrate;

2. The Doherty amplifier including a carrier amplifier and a peak amplifier to claim 1, wherein the input splitter provided on another semiconductor chip.

3. The Doherty amplifier including a carrier amplifier and a peak amplifier to claim 1, wherein one end of the offset transmission line of the offset unit connected with the carrier amplifier and other end of the offset transmission line of the offset unit connected with the peak amplifier by each wire boding.

4. The Doherty amplifier including a carrier amplifier and a peak amplifier to claim 3, wherein one end of the offset transmission line of the offset unit connected with one end of the output combiner.

5. The Doherty amplifier including a carrier amplifier and a peak amplifier to claim 1, wherein the offset unit that includes two equal grounded capacitors connected with both ends of the offset transmission line.

6. The Doherty amplifier including a carrier amplifier and a peak amplifier to claim 1, wherein the transmission line comprises a microstrip line.

7. The Doherty amplifier including a carrier amplifier and a peak amplifier to claim 1, wherein the input splitter comprises a conductive feature of an integrated passive device (IPD).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The foregoing and other purposes, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:

[0011] FIG. 1 shows a circuit schematic of the prior art of an integrated Doherty amplifier;

[0012] FIG. 2A shows a planar structure of a Wilkinson power divider and its equivalent, and FIG. 2B shows a planar structure of a transmission line and its equivalent;

[0013] FIG. 3 shows a circuit schematic of a proposed integrated Doherty amplifier;

[0014] FIG. 4 shows an implementation of the proposed integrated Doherty amplifier of FIG. 3;

[0015] FIG. 5 shows an implementation of another embodiment of the proposed integrated Doherty amplifier;

[0016] FIG. 6 shows an implementation of another embodiment of the proposed integrated Doherty amplifier;

[0017] FIG. 7 shows another circuit schematic of a proposed integrated Doherty amplifier; and

[0018] FIG. 8 shows an implementation of the proposed integrated Doherty amplifier of FIG. 7.

DETAILED DESCRIPTION

[0019] FIG. 3 shows the circuit schematic of proposed integrated Doherty amplifier with improved insertion loss, isolation between the main and peaking amplifiers, and spurious suppression. Here, the impedance inverter consists of two drain-source capacitances C.sub.ds (capacitances C.sub.ds are different if the main and peaking devices have different numbers of cells) and inductor L.sub.4 which is implemented as a bonding wire, the output impedance transformation is provided by a two-section matching circuit (an output combiner) representing a band-pass filter structure with the first low-pass matching section (L.sub.6C.sub.6) to suppress harmonic and intermodulation components above operating bandwidth and the second high-pass matching section (C.sub.7L.sub.7) to suppress the modulation, intermodulation, and subharmonic components below operating bandwidth. The two-section matching circuit combines outputs of main and peaking devices each provided through the offset transmission line (L.sub.0 or L.sub.6).

[0020] The choke inductor L.sub.ch and the bypass capacitor C.sub.bp are used to connect the RF amplifying path with a dc-feed power supply, and the value of the inductor L.sub.ch can be adjusted by varying the value of the shunt capacitor C.sub.6.

[0021] In addition to the lumped Wilkinson power divider (C.sub.1L.sub.1C.sub.1-C.sub.2L.sub.2C.sub.2-R.sub.0) and the phase compensation line (C.sub.3L.sub.3C.sub.3), two input low-pass matching sections (C.sub.4L.sub.4 for the main device and C.sub.5L.sub.5 for the peaking device) are used where L.sub.4 and L.sub.5 are implemented by bonding wires connecting the device gate to an external input circuit.

[0022] The capacitor C.sub.b is a dc-blocking capacitor to isolate a dc-bias circuit for the peaking device from an RF input path.

[0023] FIG. 4 shows the implementation of the proposed integrated Doherty amplifier where the main and peaking devices are located on separate active die (semiconductor chip) using GaN HEMT technology, the integrated passive die (IPD) is used for an input circuit including the Wilkinson power divider, and the output matching network (OMN) is used to implement the output matching circuit including a dc-feed power supply circuit.

[0024] The key benefits of the IPD technology using gallium arsenide or silicon high-resistivity substrate to implement multiple passive components such as inductors, capacitors, and resistors on a single substrate are a competitive cost structure, a small form factor, and reduced power losses. In view of high dc supply voltage (up to 50 V) and high peak output power (several tens of watt), the best choice for OMN implementation with minimum insertion loss is to use the ceramic or laminate substrate. The magnetic coupling between the bondwire inductances L.sub.0 and L.sub.6 is minimized due to their orthogonal orientation to each other.

[0025] An input IPD comprises the combined metal-insulator-metal (MIM) series capacitor C.sub.1+C.sub.2, series spiral inductors L.sub.1 and L.sub.2, the combined shunt MIM capacitors C.sub.1+C.sub.4 and C.sub.2+C.sub.3 grounded through substrate vias, the ballast resistor R.sub.0, the blocking series MIM capacitor C.sub.b, the series spiral inductor L.sub.3 and the combined shunt MIM capacitor C.sub.3+C.sub.5 grounded through substrate via.

[0026] The series bondwire inductors L.sub.4 and L.sub.5 represent the corresponding parts of the input low-pass matching sections directly connected to the gates of the main and peaking devices, respectively. The bondwire inductor L.sub.0 directly connects the drains of the main and peaking devices as a part of the impedance inverter, whereas the bondwire inductor L.sub.6 connected to the drain of the peaking device operates as a series inductor of the output low-pass matching section of a two-section OMN. One end of bondwire inductor L.sub.0 is directly connected with the drain of the main device, and other end of bondwire inductor L.sub.0 is directly connected with the drain of the peaking device. One end of bondwire inductor L.sub.0 is also directly connected with one end of the bondwire inductor L.sub.6.

[0027] An OMN also includes the chip capacitor C.sub.6 (grounded through substrate via) as a shunt element of the low-pass matching section, and the series chip capacitor C.sub.7 and shunt inductor L.sub.7 (grounded through the substrate via) as elements of the high-pass matching section.

[0028] The combination of the low-pass and high-pass matching sections in a single matching network operates as an impedance-transforming bandpass filter to suppress the low-frequency and high-frequency intermodulation and harmonic components simultaneously. To improve the quality factors of the inductance and to reduce the insertion loss in the OMN, the shunt inductor L.sub.7 and the choke inductor L.sub.ch are implemented as short-length microstrip lines.

[0029] As an example, using the laminate substrate with dielectric permittivity of 3.5 and thickness of 0.5 mm, the lengths of the microstrip lines L.sub.ch and L.sub.7 when using two 20-W GaN HEMT devices for symmetrical Doherty structure (or 10 W and 30 W devices for 1:3 asymmetrical Doherty configuration) are equal to 3 mm and 2 mm, respectively, whereas the width of these microstrip lines are of 0.2 mm.

[0030] FIG. 5 shows another embodiment of the proposed integrated Doherty amplifier which is used when the bondwire L.sub.0 is too long and cannot be physically implemented as a single bondwire between two device drains. In this case, a narrow microstrip line implemented on OMN can be used, whose length and width can be adjusted depending on the required overall inductance value for L.sub.0. Each device drain from active GaN die is connected by short bondwire to the corresponding end of this microstrip line.

[0031] FIG. 6 shows the implementation of the proposed integrated Doherty amplifier where the main and peaking devices are located on separate active die using GaN HEMT technology, the narrow microstrip line TL and bondwire inductor L.sub.01, bondwire inductor L.sub.02 provided instead of the bondwire inductor L.sub.0 in the implementation of the proposed integrated Doherty amplifier of FIG. 4.

[0032] FIG. 7 shows the circuit schematic of the proposed integrated Doherty amplifier with improved insertion loss, high isolation between the carrier and peaking amplifier, and spurious suppression. Here, the impedance inverter in the peaking amplifying path consists of two equal grounded capacitors C.sub.6 and transmission line TL.sub.1, while the impedance transformation at the output of the carrier device is provided by the drain-source capacitance C.sub.ds and bondwire inductor L.sub.7 and at the output of the peaking device (at high-power region when the transistor is turned on) by the drain-source capacitance C.sub.ds and bondwire inductor L.sub.6 (capacitances C.sub.ds are different if the carrier and peaking devices have different number of cells).

[0033] The output impedance transformation is provided by a two-section matching circuit representing a band-pass filter with the first low-pass matching section (L.sub.8C.sub.7) to suppress harmonic and intermodulation components above operating bandwidth and the second high-pass matching section (C.sub.8L.sub.9) to suppress the modulation, intermodulation, and subharmonic components below operating bandwidth.

[0034] The choke inductor L.sub.ch and bypass capacitor C.sub.bp are used to connect the RF amplifying path with dc-feed power supply, and the value of the inductor L.sub.ch can be adjusted by varying the value of the shunt capacitor C.sub.7 to optimize the size of the output matching network (OMN).

[0035] In addition to lumped Wilkinson divider (C.sub.1L.sub.1C.sub.1-C.sub.2L.sub.2C2-R.sub.0) and the phase compensation line (C.sub.3L.sub.3C.sub.3), two input low-pass matching sections (C.sub.4L.sub.4 for carrier device and C.sub.5L.sub.5 for peaking device) are used where L.sub.4 and L.sub.5 are implemented by bonding wires connecting the corresponding device gate to external input circuit. The capacitor C.sub.b is a dc-blocking capacitor to isolate dc-bias circuit for the peaking device from RF input path.

[0036] FIG. 8 shows the implementation of the proposed integrated Doherty amplifier where the carrier and peaking devices are located on separate active die using GaN HEMT technology, the integrated passive die (IPD) is used for input circuit including Wilkinson power divider, and the laminate or ceramic OMN is used to implement the output matching circuit.

[0037] The key benefits of the IPD technology using gallium arsenide or silicon high-resistivity substrate to implement multiple passive device on a single substrate are a competitive cost structure, a small form factor, and reduced power losses. In view of high dc supply voltage (up to 50 V) and high peak output power (several tens of watt), the best choice for OMN implementation with minimum insertion loss is to use the ceramic or laminate substrate (dielectric substrate).

[0038] An input IPD comprises the combined metal-insulator-metal (MIM) series capacitor C.sub.1+C.sub.2, series spiral inductors L.sub.1 and L.sub.2, the combined shunt MIM capacitors C.sub.1+C.sub.4 and C.sub.2+C.sub.3 grounded through substrate vias, the ballast resistor R.sub.0, the blocking series MIM capacitor C.sub.b, the series spiral inductor L.sub.3 and the combined shunt MIM capacitor C.sub.3+C.sub.5 grounded through substrate via.

[0039] The series bondwire inductors L.sub.4 and L.sub.5 represent the corresponding parts of the input low-pass matching sections directly connected to the gates of the carrier and peaking devices, respectively. An OMN comprises the transmission line TL.sub.1 with two equal shunt capacitors C.sub.6 representing an impedance inverter, the bondwire inductors L.sub.6 and L.sub.7 connected to the drains of the peaking and carrier devices, respectively, operating as the series inductors of the impedance-transforming low-pass matching sections together with the drain-source capacitances C.sub.ds, the series inductor L.sub.8 and shunt chip capacitor C.sub.7 (grounded through substrate via) as elements of the low-pass matching section, and the series chip capacitor C.sub.8 and shunt inductor L.sub.9 (grounded through the substrate via) as elements of the high-pass matching section of a two-section output matching network.

[0040] The combination of the low-pass and high-pass matching sections in a single matching network operates as an impedance-transforming bandpass filter to suppress the low-frequency and high-frequency intermodulation and harmonic components simultaneously. To improve the quality factors of the inductance and reduce the insertion loss in the output matching network, the series inductor L.sub.8, shunt inductor L.sub.9, and choke inductor L.sub.ch are implemented as short-length high-impedance microstrip lines.

[0041] As an example, using the laminate substrate with dielectric permittivity of 3.5 and thickness of 0.5 mm, the lengths of the microstrip lines L.sub.ch and L.sub.9 using two 20-W GaN HEMT devices for symmetrical Doherty structure (or 15 W and 30 W devices for 1:2 asymmetrical Doherty configuration) are equal to 3.5 mm each, while the width of these microstrip lines are of 0.2 mm at 3.5 GHz.