ELECTRICAL CONNECTING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Abstract

An electrical connecting structure and a method for manufacturing the same are disclosed. The electrical connecting structure comprises: a first substrate; a second substrate; and an interconnect element disposed between the first substrate and the second substrate, wherein the interconnect element has a width, and no joint surface is present in the interconnect element in a range of 50% or more of the width.

Claims

1. An electrical connecting structure, comprising: a first substrate; a second substrate; and an interconnect element disposed between the first substrate and the second substrate, wherein the interconnect element has a width, and no joint surface is present in the interconnect element in a range of 50% or more of the width.

2. The electrical connecting structure of claim 1, wherein no joint surface is present in a range of 50% or more of the width in a cross section of the interconnect element.

3. The electrical connecting structure of claim 2, wherein no joint surface is present in a continuous range of 50% or more of the width in the cross section of the interconnect element.

4. The electrical connecting structure of claim 1, wherein the interconnect element comprises a monocrystalline grain, and the monocrystalline grain occupies 50% or more of a volume of the interconnect element.

5. The electrical connecting structure of claim 1, wherein the width of the interconnect element ranges from 50 nm to 50 μm. 6, The electrical connecting structure of claim 1, wherein a thickness of the interconnect element ranges from 50 nm to 50 μm.

7. The electrical connecting structure of claim 1, wherein the interconnect element is obtained by bonding a first copper bump disposed on the first substrate and a second copper bump disposed on the second substrate.

8. The electrical connecting structure of claim 7, wherein a first insulating layer is disposed sin the first substrate, the first insulating layer comprises a first recess, and the first copper bump is disposed in the first recess; wherein the first recess has a first side wall, and an angle included between the first side wall and a surface of the first substrate is in a range from 70 degrees to 90 degrees.

9. The electrical connecting structure of claim 7, wherein a second insulating layer is disposed on the second substrate, the second insulating layer comprises a second recess, and the second copper bump is disposed in the second recess; wherein the second recess has a second side wall, and an angle included between the second side wall and a surface of the second substrate is in a range from 70 degrees to 90 degrees.

10. A method for manufacturing an electrical connecting structure, comprising the following steps: providing a first substrate and a second substrate, wherein a first nano-twinned copper bump is disposed on the first substrate, a second nano-twinned copper bump is disposed on the second substrate, and 50% or more in volume of the first nano-twinned copper bump and 50% or more in volume of the second nano-twinned copper bump respectively comprise plural twinned grains; and bonding the first nano-twinned copper bump and the second nano-twinned copper bump at a temperature ranging from 150° C. to 400° C., to form an interconnect element, wherein the interconnect element has a width, and no joint surface is present in the interconnect element in a range of 50% or more of the width.

11. The method of claim 10, wherein no joint surface is present in a range of 50% or more of the width in a cross section of the interconnect element.

12. The method of claim 11, wherein no joint surface is present in a continuous range of 50% or more of the width in the cross section of the interconnect element.

13. The method of claim 10, wherein in the step of bonding the first nano-twinned copper hump and the second nano-twinned copper bump to form the interconnect element, at least a part of the plural twinned grains in the first nano-twinned copper bump and at least a part of the plural twinned grains in the second nano-twinned copper bump are recrystallized to form the interconnect element comprising a monocrystalline grain, and the monocrystalline grain occupies 50% or more of a volume of the interconnect element.

14. The method of claim 10, wherein the width of the interconnect element ranges from 50 nm to 50 μm.

15. The method of claim 10, wherein a thickness of the interconnect element ranges from 50 nm to 50 μm.

16. The method of claim 10, wherein a first insulating layer is disposed on the first substrate, the first insulating layer comprises a first recess, and the first nano-twinned copper bump is disposed in the first recess; wherein the first recess has a first side wall, and an angle included between the first side wall and a surface of the first substrate is in a range from 70 degrees to 90 degrees.

17. The method of claim 10, wherein a second insulating layer is disposed on the second substrate, the second insulating layer comprises a second recess, and the second nano-twinned copper bump is disposed in the second recess; wherein the second recess has a second side wall, and an angle included between the second side wall and a surface of the second substrate is in a range from 70 degrees to 90 degrees.

18. The method of claim 10, wherein at least 50% of an area of a surface of the first nano-twinned copper bump and at least 50% of an area of a surface of the second nano-twinned copper bump respectively expose a (111) surface of the plural twinned grains.

19. The method of claim 10, wherein the plural twinned grains are connected with each other, and each of the plural twinned grains is thrilled by staking plural twins along a [111] crystal axis.

20. The method of claim 19, wherein an angle included between the [111] crystal axes of two adjacent twinned grains of the plural twinned grains is in a range from 0 degree to 20 degrees.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG. 1A and FIG. 1B are cross-sectional views showing the method for manufacturing an electrical connecting structure of the present disclosure.

[0036] FIG. 2 is an EBSD photo of a nano-twinned copper bump prepared in Embodiment 1 of the present disclosure.

[0037] FIG. 3 is a FIB photo of a nano-twinned copper bump prepared in Embodiment 1 of the present disclosure.

[0038] FIG. 4 is an EBSD photo of an electrical connecting structure prepared in Embodiment 1 of the present disclosure.

[0039] FIG. 5 is a FIB photo of an electrical connecting structure prepared in Embodiment 1 of the present disclosure.

[0040] FIG. 6 is an EBSD photo of an electrical connecting structure prepared in Comparative embodiment 1 of the present disclosure.

[0041] FIG. 7 is a FIB photo of an electrical connecting structure prepared in Comparative embodiment 1 of the present disclosure.

[0042] FIG. 8 is a FIB photo of an electrical connecting structure prepared in Embodiment 4 of the present disclosure.

[0043] FIG. 9 are FIB photos of nano-twinned copper bumps prepared in Embodiment 5 to Embodiment 8 of the present disclosure, wherein (a) is the FIB photo of the nano-twinned copper bump prepared in Embodiment 5, (b) is the FIB photo of the nano-twinned copper bump prepared in Embodiment 6, (c) is the FIB photo of the nano-twinned copper bump prepared in Embodiment 7, and (d) is the FIB photo of the nano-twinned copper bump prepared in Embodiment 8.

[0044] FIG. 10 are FIB photos of electrical connecting structures prepared in Embodiment 5 to Embodiment 8 of the present disclosure, wherein (a) is the FIB photo of the electrical connecting structure prepared in Embodiment 5, (b) is the FIB photo of the electrical connecting structure prepared in Embodiment 6, (c) is the FIB photo of the electrical connecting structure prepared in Embodiment 7, and (d) is the FIB photo of the electrical connecting structure prepared in Embodiment 8.

[0045] FIG. 11A and FIG. 11B are respectively FIB photos of nano-twinned copper bumps prepared in Embodiment 9 and Embodiment 10 of the present disclosure.

[0046] FIG. 12A and FIG. 12B are respectively FIB photos of electrical connecting structures prepared in Embodiment 9 and Embodiment 10 of the present disclosure.

DETAILED DESCRIPTION OF EMBODIMENT

[0047] Different embodiments of the present disclosure are provided in the following description. These embodiments are meant to explain the technical content of the present disclosure, but not meant to limit the scope of the present disclosure. A feature described in an embodiment may be applied to other embodiments by suitable modification, substitution, combination, or separation.

[0048] It should be noted that, in the present specification, when a component is described to have an element, it means that the component may have one or more of the elements, and it does not mean that the component has only one of the element, except otherwise specified.

[0049] In the present specification, except otherwise specified, the feature A “or” or “and/or” the feature B means the existence of the feature A, the existence of the feature B, or the existence of both the features A and B. The feature A “and” the feature B means the existence of both the features A and B. The term “comprise(s)”, “comprising”, “include(s)”, “including”, “have”, “has” and “having” means “comprise(s)/comprising but is/are/being not limited to”.

[0050] Moreover, in the present specification, when an element is described to be arranged “on” another element, it does not essentially means that the elements contact the other element, except otherwise specified. Such interpretation is applied to other cases similar to the case of “on”.

[0051] Moreover, in the present specification, a value may be interpreted to cover a range within ±10% of the value, and in particular, a range within ±5% of the value, except otherwise specified; a range may be interpreted to be composed of a plurality of subranges defined by a smaller endpoint, a smaller quartile, a median, a greater quartile, and a greater endpoint, except otherwise specified.

[0052] FIG. 1A and FIG. 1B are cross-sectional views showing the method for manufacturing an electrical connecting structure of the present disclosure. As shown in FIG. 1A, a first substrate 11 and a second substrate 21 are provided, wherein, a first nano-twinned copper bump 13 is disposed on the first substrate 11, and a second nano-twinned copper bump 23 is disposed on the second substrate 21. In addition, 50% or more in volume of the first nano-twinned copper bump 13 and 50% or more in volume of the second nano-twinned copper bump 23 respectively comprise plural twinned grains.

[0053] More specifically, a first insulating layer 12 is disposed on the first substrate 11, the first insulating layer 12 comprises a first recess 121, and the first nano-twinned copper bump 13 is disposed in the first recess 121; wherein the first recess 121 has a first side wall 122, and an angle θ1 included between the first side wall 122 and a surface of the first substrate 11 is in a range from 70 degrees to 90 degrees. In addition, a second insulating layer 22 is disposed on the second substrate 21, the second insulating layer 22 comprises a second recess 221, and the second nano-twinned copper bump 23 is disposed in the second recess 221; wherein the second recess 221 has a second side wall 222, and an angle θ2 included between the second side wall 222 and a surface of the second substrate 21 is in a range from 70 degrees to 90 degrees.

[0054] Next, the first nano-twinned copper bump 13 and the second nano-twinned copper bump 23 are bonded at a temperature ranging from 1150° C. to 400° C., to form an interconnect element 3, wherein the interconnect element 3 has a width W, and no joint surface 33 is present in the interconnect element 3 in a range of 50% or more of the width W.

[0055] More specifically, when the first nano-twinned copper bump 13 and the second nano-twinned copper bump 23 are bonded to form the interconnect element 3, the twinned grains in the first nano-twinned copper bump 13 and the second nano-twinned copper bump 23 are recrystallized. Thus, in the obtained electrical connecting structure, the first nano-twinned copper bump 13 is transferred into the first copper bump 31 in which the twinned boundaries are almost eliminated, and the second nano-twinned copper bump 23 is also transferred into the second copper bump 32 in which the twinned boundaries are almost eliminated. Therefore, the obtained interconnect element 3 can be considered as being formed by bonding the first copper bump 31 on the first substrate 11 and the second copper bump 32 on the second substrate 21.

[0056] After the aforesaid process, the electrical connecting structure of the present disclosure can be obtained, which comprises: a first substrate 11; a second substrate 21; and an interconnect element 3 disposed between the first substrate 11 and the second substrate 21, wherein the interconnect element 3 has a width W and no joint surface 33 is present in the interconnect element 3 in a range of 50% or more of the width W. In particular, in a cross section of the interconnect element 3, no joint surface 33 is present in a continuous range of 50% or more of the width W. In addition, the interconnect element 3 comprises a monocrystalline grain, and the monocrystalline grain occupies 50% or more of a volume of the interconnect element 3.

Embodiment 1

[0057] In the present embodiment, 8-inch silicon wafers coated with 100 nm Ti—W/200 nm Cu were used as the cathodes for electrodeposition, wherein the silicon wafers can be regarded as the first substrate 11 and the second substrate 21 shown in FIG. 1A and FIG. 1B. In addition, insulating layers were formed on the silicon wafers, the insulating layers have openings, and these openings define the regions for the sequentially formed nano-twinned copper bumps. Herein, the insulating layers can be regarded as the first insulating layer 12 and the second insulating layer 22 shown in FIG. 1A and FIG. 1B, and the openings of the insulating layers can be regarded as the first recess 121 and the second recess 221. The material of the insulating layers may be PBO, PI, SiO.sub.2, SiCN, SiN, underfill, silicon on glass (SOG) or a combination thereof. In the present embodiment, the material of the insulating layers is SiO.sub.2. The thickness of the insulating layer may be ranged from 50 nm to 50 μm, and the insulating layers can be firmed by plasma-enhanced chemical vapor deposition (PECVD) or any other coating process known in the art.

[0058] Next, the electrodeposition of the nano-twinned copper layer was performed. The plating solution used herein was formulated by CuSO.sub.4 powders, H.sub.2SO.sub.4, HCl and an additive (108C, provided by Chemleader Corporation). 196.61 g of CuSO.sub.4.5H.sub.2O was added, followed by adding 100 g of H.sub.2SO.sub.4 (96%), 0.1 ml of HCl and 35 ml of additive. Then, de-ionized water was added until the volume of the total solution was 1 L. The plating solution was stirred with a stir bar until the solution was mixed well. After mixing, the plating solution was placed into an electroplating tank, and the stir bar was stirred at 1200 rpm/min to maintain the flow of the plating solution. The electrodeposition was performed at room temperature and atmospheric pressure. The power supply (Keithley 2400) was controlled by the computer. For example, when the direct current electrodeposition was performed with a current density of 10 ASD (A/dm.sup.2) for 10 minutes, the nano-twinned copper pillar with columnar grains can be obtained, wherein the thickness of the nano-twinned copper pillar (i.e. the thickness H1 shown in FIG. 1A) was about 6 to 8 μm, and the width (i.e. the width W shown in FIG. 1A) was about 45 μm. The obtained nano-twinned copper pillar can be used as the first nano-twinned copper bump 13 and the second nano-twinned copper bump 23 shown in FIG. 1A and FIG. 1B.

[0059] FIG. 2 and FIG. 3 are respectively an EBSD photo and a FIB photo of the nano--twinned copper bump prepared in the present embodiment. In the nano-twinned copper pillar obtained in the present embodiment, almost all the volume (97% or more of the volume) of the nano-twinned copper pillar are formed by columnar twinned grains connecting with each other, the diameter of the columnar twinned grain is about 0.87 μm, and the thickness of the transition layer is about 0.3 μm. In addition, the twinned grains are formed by staking nano-twins along a [111] crystal axis, an angle included between the [111] crystal axes of two adjacent nano-twinned grains is about 0 degree, and the twin boundaries of the nano-twins are substantially parallel to the surface of the substrate (i.e. the stacking direction of the nano-twins is substantially parallel to the thickness direction (Y) of the nano-twinned copper pillar). Therefore, almost all the surface of the nano-twinned copper pillar (97% or more of the area) exposes the (111) surface of the nano-twins, indicating that the nano-twinned copper pillar of the present embodiment has a (111) preferred direction. Furthermore, the angle included between the twin direction of 95% or more of the twinned grains and the thickness (Y) direction of the nano-twinned copper pillar is about 0 degree, and the angle included between the twin direction of 95% or more of the twinned grains and the surface of the substrate is about 90 degrees. This indicates that the twin boundaries of the twin grains are substantially parallel to the surface of the substrate. In addition, 95% or more of the twinned grains of the nano-twinned copper pillar have thicknesses ranging from 1 μm to 20 μm.

[0060] Next, the backside of the silicon wafer was polished until the thickness of the silicon wafer was about 500 μm to facilitate the thermal compression bonding. An ultraviolet microscope was used to facilitate the alignment of the wafers because the UV light can penetrate through the wafers. Then, chemical-mechanical planarization (CMP) was used to reduce the roughness of the surface of the nano-twinned copper pillar into 2˜5 nm. The silicon wafer after polishing was cut into a top die (6 mm×6 mm) and a bottom die (15 mm×15 mm). The dies were cleaned with hot citric acid to remove the oxides on the surface of the dies. In an environment with a vacuum pressure of 10.sup.−3 torr, the top die and the bottom die were bonded at 250° C., under 300 Newton for 2 hours to obtain the electrical connecting structure of the present embodiment. In the obtained electrical connecting structure, the thickness of the interconnect element (i.e. the thickness H2 shown in FIG. 13) is about 12˜16 μm, and the width (i.e. the width W shown in FIG. 1B) is about 45 μm.

[0061] The structure of the interconnect element obtained by thermal compression bonding was analyzed by EBSD and FIB. FIG. 4 and FIG. 5 are respectively an EBSD photo and a FIB photo of the electrical connecting structure obtained in the present disclosure. As shown in FIG. 4, after thermal compression bonding at 250° C., the original nano-twinned copper pillar was recrystallized and grew into a larger grain, and an interconnect element with quasi-single crystal structure can be obtained, in which 80% of the bonding interface was eliminated. Similarly, as shown in FIG. 5, almost no crystal boundary was observed in the interconnect element, and 80% of the bonding interface was eliminated.

[0062] The above results indicate that the twinned grains in the nano-twinned copper pillar can be recrystallized and grow into larger grain by thermal compression process at a suitable temperature, and no crystal boundary was observed in the obtained interconnect element. In addition, the larger grain can grow across the bonding interface, so 80% or more of the bonding interface between the copper pillars can be eliminated. Therefore, no joint surface is present in the interconnect element in a continuous range of 80% or more of the width of the interconnect element, and the interconnect element with quasi-single crystal structure can be obtained.

Comparative Embodiment 1

[0063] The method for preparing the electrical connecting structure of the present comparative embodiment is similar to that illustrated in Embodiment 1, except that the temperature of the thermal compression bonding was 150° C. in the present embodiment. FIG. 6 and FIG. 7 are respectively an EBSD photo and a FIB photo of the electrical connecting structure prepared in the present comparative embodiment.

[0064] As shown in FIG. 6 and FIG. 7, when the nano-twinned copper pillars were bonded by thermal compression bonding at 150° C., although the nano-twinned copper pillars can be successfully bonded, the twin grains in the nano-twinned copper pillars still maintain in high density and the bonding interface between the nano-twinned copper pillars still exists. It is because the thickness of the transition layer is thin, but the twinned grains are not small enough to grow large grain at this temperature.

[0065] In addition, the tensile strengths of the electrical connecting structures obtained by bonding the same nano-twinned copper bumps at different temperatures, pressures and times were compared, and the results are shown in the following Table 1.

TABLE-US-00001 TABLE 1 Bonding Bonding Tensile temperature pressure Bonding strength (° C.) (MPa) time (MPa) Embodiment 250 41.5 2 hours 32.9 1 Embodiment 200 41.5 2 hours 19.89 2 Embodiment 250 41.5 60 seconds 9.78 3 Comparative 150 41.5 2 hours 0.82 embodiment 1

[0066] The results shown in Table 1 indicate that the electrical connecting structures obtained in Embodiment 1 to Embodiment 3 have larger tensile strength than that obtained in Comparative embodiment 1. It should be noted that, the tensile strength of the electrical connecting structure obtained in Embodiment 1 should be greater than 32.9 MPa. This is because the test specimen was not broken at the bonding interface, but the fracture was occurred on the silicon wafer.

Embodiment 4

[0067] The method for preparing the electrical connecting structure of the present embodiment is similar to that illustrated in Embodiment 1, except for the following differences.

[0068] First, a first insulating layer was deposited on the silicon wafer by plasma-enhanced chemical vapor deposition (PECVD), and the material of the first insulating layer may be, for example, SiO.sub.2, SiCN, SiN or a combination thereof. In the present embodiment, the material of the first insulating layer was SiO.sub.2. Next, a second insulating layer was formed, and the material of the second insulating layer may be positive resin or negative resin. The first insulating layer was patterned by the etching process to define a region having a width ranging from 50 nm to 100 μm. Next, the second insulating layer was removed. The same process for electrodeposition illustrated in Embodiment 1 was performed to obtain the nano-twinned copper pillar of the present embodiment, which has similar structure of the nano-twinned copper pillar obtained in Embodiment 1. In addition, in the present embodiment, except for the joint surface, the peripheral surface of the nano-twinned copper pillar is surrounded by the first insulating layer.

[0069] After the surface of the nano-twinned copper pillar was planarized with CMP, the same thermal compression bonding of Embodiment 1 was performed herein to obtain the electrical connecting structure of the present embodiment. FIG. 8 is a FIB photo of the electrical connecting structure prepared in the present embodiment, which indicates that 50% or more of the bonding interface in the interconnect element was eliminated.

Embodiment 5 to Embodiment 10

[0070] The method for preparing the nano-twinned copper bump of the present embodiments is similar to that illustrated in Embodiment 1. Herein, the same current density was used, but different temperatures for the electrodeposition (from 0° C. to 100° C.) were used to control the grain size and the thickness of the transition layer. In addition, by using the similar thermal compression bonding illustrated in Embodiment 1, the electrical connecting structures of the present embodiments can be obtained. In Embodiments 5 to 8, the bonding temperature was 250° C. and the bonding time was 2 hours. In Embodiment 9, the bonding temperature was 175° C. and the bonding time was 90 minutes. In Embodiment 10, the bonding temperature was 150° C. and the bonding time was 90 minutes.

[0071] FIG. 9 are FIB photos of nano-twinned copper bumps prepared in Embodiment 5 to Embodiment 8 of the present disclosure, wherein (a) to (d) are respectively the FIB photos of the nano-twinned copper bumps prepared in Embodiment 5 to Embodiment 8. Herein, the nano-twinned copper bump comprises a transition layer 311 (i.e. the region below the dotted line) and a nano-twinned copper layer 312 (i.e. the region above the dotted line). As shown in FIG. 9(a), the average thickness of the transition layer of the nano-twinned copper bump prepared in Embodiment 5 was about 0.23 μm, and the diameter of the columnar nano-twinned grains was about 1.2˜1.5 μm. As shown in FIG. 9(b), the average thickness of the transition layer of the nano-twinned copper bump prepared in Embodiment 6 was about 0.45 μm, and the diameter of the columnar nano-twinned grains was about 1.2˜1.5 μm. As shown in FIG. 9(c), the average thickness of the transition layer of the nano-twinned copper bump prepared in Embodiment 7 was about 1.1 μm, and the diameter of the columnar nano-twinned grains was about 1.2˜1.5 μm. As shown in FIG. 9(d), the average thickness of the transition layer of the nano-twinned copper bump prepared in Embodiment 8 was about 0.33 μm, and the diameter of the columnar nano-twinned grains was about 0.71 μm.

[0072] FIG. 10 are FIB photos of electrical connecting structures prepared in Embodiment 5 to Embodiment 8 of the present disclosure, wherein (a) to (d) are respectively the FIB photos of the electrical connecting structure prepared in Embodiment 5 to Embodiment 8.

[0073] As shown in FIG. 9(a) and FIG. 10(a), when the transition layer is too thin, most of the grains cannot grow across the joint surface, and the electrical connecting structure that the joint surface is eliminated cannot be obtained. As shown in FIG. 9(b) and FIG. 10(b), when the transition layer has a suitable thickness, all the transition layer is almost eliminated, and most of the grains can be recrystallized and grow across the joint surface. Thus, the electrical connecting structure that the joint surface is eliminated can be obtained, and a large crystal grain can be obtained. However, as shown in FIG. 9(c) and FIG. 10(c), when the transition layer is too thick, even though the grains can be recrystallized, most of the grains cannot grow across the joint surface, and the electrical connecting structure that the joint surface is eliminated cannot be obtained. In addition, as shown in FIG. 9(d) and FIG. 10(d), the transition layer is thin (the thickness of the transition layer shown in FIG. 9(d) is similar to that shown in FIG. 9(a)), and the size of the twinned grains is small. Thus, during the bonding process, the internal system energy increases due to the finer grains and the more grain boundaries, which can cause large grains to grow and grow across the joint surface to obtain the electrical connecting structure that the joint surface is almost eliminated.

[0074] FIG. 11A and FIG. 11B are respectively FIB photos of nano-twinned copper bumps prepared in Embodiment 9 and Embodiment 10 of the present disclosure. Herein, the nano-twinned copper bump of Embodiment 9 has the transition layer with the average thickness of about 0.33 μm, and the diameter of the columnar nano-twinned grains is about 0.74 μm. The nano-twinned copper bump of Embodiment 10 has the transition layer with the average thickness of about 0.45 μm, and the diameter of the columnar nano-twinned grains is about 0.52 μm.

[0075] FIG. 12A and FIG. 12B are FIB photos of electrical connecting structures prepared in Embodiment 9 and Embodiment 10 of the present disclosure. As shown in FIG. 12A and FIG. 12B, when the twinned grains has small size, the internal system energy increases during the bonding process due to the finer grains and the more grain boundaries, which can cause large grains to grow and grow across the joint surface to obtain the electrical connecting structure that the joint surface is almost eliminated.

[0076] The aforementioned results indicate that when the transition layer is too thin, the nano-twinned copper grains cannot be recrystallized and cannot grow across the joint surface, so the electrical connecting structure that the joint surface is almost eliminated cannot be obtained. When the transition layer is too thick, the twinned copper grains can be recrystallized to grow larger crystal grain, but most of the growth crystal grains cannot grow across the joint surface, so the electrical connecting structure that the joint surface is almost eliminated cannot be obtained. When the transition layer has suitable thickness, if it is desirable to obtain the electrical connecting structure that the joint surface is almost eliminated at low bonding temperature, the thickness of the transition layer has to be thin (but still in the suitable thickness range) and the grain size of the twinned grains has to be small. If the thickness of the transition layer is relatively thin (but still in the suitable thickness range) and the grain size of the twinned grain is relative large, the electrical connecting structure that the joint surface is almost eliminated can be obtained at higher bonding temperature.

[0077] In the present disclosure, the nano-twinned copper bumps with (111) preferred direction are bonded at specific temperature (150° C. to 400° C.), the twinned grains in the nano-twinned copper bumps are recrystallized to grow the large grain, and the growth large grain can grow across the joint surface. In addition, by controlling the transition layer in the nano-twinned copper bump having suitable thickness or reducing the size of the twinned grains in the nano-twinned copper bump, the twinned grains in the nano-twinned copper bump can be recrystallized to grow large grain, and the growth large grain can grow across the joint surface. Thus, in the electrical connecting structure provided by the present disclosure, almost all the original grain boundaries of the nano-twinned grains are not observed, and almost all the joint surface of the interconnect element is eliminated. Thus, the electrical connecting structure of the present disclosure has high strength, high electrical conductivity, high thermal conductivity or high electromigration life, and the manufacturing cost of the electrical connecting structure is also low. Therefore, the electrical connecting structure of the present disclosure has potential to be applied to microelectronics 3D-IC package.

[0078] Although the present disclosure has been explained in relation to its embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the disclosure as hereinafter claimed.