Control method for an active pixel image sensor

Abstract

In an active pixel sensor comprising a photodiode Dp, a memory node MN and a readout node SN, the memory node being provided to contain the charge generated by the photodiode at the end of an integration period allowing an integration in global shutter mode and a correlated double sampling, it is envisaged to carry out, in each integration period, at least one transfer {circle around (2)} of charge from the photodiode to the memory node followed by clipping {circle around (3)} of the amount of charge contained in the memory node at an intermediate voltage t.sub.1 after the start of the integration period but before a last transfer of charge {circle around (4)} to the memory node at the end of the integration period. The pixels are subsequently read out, row by row, by correlated double sampling CDS. The one or more intermediate transfers, with clipping, to the memory node during the integration period allow the dynamic range of the sensor to be extended to high levels of ambient light while retaining good sensitivity to low levels of ambient light.

Claims

1. An image capture method in an active pixel image sensor, applying an integration period common to all of the pixels before a phase of reading out the pixels, row by row, each pixel comprising a memory node between a photosensitive element and a readout node of the pixel, with a first charge transfer transistor placed between the photosensitive element and the memory node and a second charge transfer transistor placed between the memory node and the readout node, wherein in each new integration period, the method comprises the following control steps, across all of the pixels simultaneously: applying, to the gate of all of the first transfer transistors: at least one first voltage pulse at an intermediate voltage between the start and the end of the integration period, controlling a transfer of charge from the photodiode to the memory node; and a final voltage pulse at the end of the integration period, controlling a final transfer of charge from the photodiode to the memory node, the end of the pulse marking the end of the current integration period; applying, to the gate of all of the second transfer transistors, a second voltage pulse after each first voltage pulse and before the final voltage pulse, the second voltage pulse setting a potential barrier height under the gate of said second transistors in relation to the potential of the memory node, allowing the charge in said memory node beyond a maximum amount of charge that can be held in said memory node to be clipped.

2. The method of claim 1, further comprising the application of N first and second pulses per integration period, N being an integer at least equal to 1, and the N first voltage pulses applied during an integration period divide said integration period into N+1 successive integration durations of increasingly smaller length, and the N second associated voltage pulses define N clipping thresholds in the memory node which keep increasing over the integration period.

3. The method of claim 2, in which N=2.

4. The method of claim 2, in which N is set according to a measurement of the ambient light, preferably at a value chosen between 1 and 2.

5. The method according to claim 1, in which the time of application of each first pulse and/or the clipping threshold associated with each second pulse are determined according to a measurement of the ambient light.

6. The method according to claim 1, in which the phase of reading out each of the pixels of one row applies a correlated double sampling for each pixel, with a first sampling of a reference level, corresponding to an initialization of the readout node, then a second sampling of a signal level corresponding to the charge which is contained in the memory node at the end of the integration period and which has been transferred to said readout node for readout.

7. An active pixel image sensor comprising at least one row of active pixels, in which each active pixel comprises a memory node between a photosensitive element and a readout node of the pixel, with a first charge transfer transistor placed between the photosensitive element and the memory node and a second charge transfer transistor placed between the memory node and the readout node, and a sequencing circuit for sequencing the signals required for image capture comprising an integration period common to all of the pixels, and a phase of successively reading out the pixels of each row, wherein the sequencing circuit is configured to implement a control method according to claim 1.

8. The method according to claim 2, in which the time of application of each first pulse and/or the clipping threshold associated with each second pulse are determined according to a measurement of the ambient light.

9. The method according to claim 3, in which the time of application of each first pulse and/or the clipping threshold associated with each second pulse are determined according to a measurement of the ambient light.

10. The method according to claim 4, in which the time of application of each first pulse and/or the clipping threshold associated with each second pulse are determined according to a measurement of the ambient light.

11. The method according to claim 2, in which the phase of reading out each of the pixels of one row applies a correlated double sampling for each pixel, with a first sampling of a reference level, corresponding to an initialization of the readout node, then a second sampling of a signal level corresponding to the charge which is contained in the memory node at the end of the integration period and which has been transferred to said readout node for readout.

12. The method according to claim 3, in which the phase of reading out each of the pixels of one row applies a correlated double sampling for each pixel, with a first sampling of a reference level, corresponding to an initialization of the readout node, then a second sampling of a signal level corresponding to the charge which is contained in the memory node at the end of the integration period and which has been transferred to said readout node for readout.

13. The method according to claim 4, in which the phase of reading out each of the pixels of one row applies a correlated double sampling for each pixel, with a first sampling of a reference level, corresponding to an initialization of the readout node, then a second sampling of a signal level corresponding to the charge which is contained in the memory node at the end of the integration period and which has been transferred to said readout node for readout.

14. The method according to claim 5, in which the phase of reading out each of the pixels of one row applies a correlated double sampling for each pixel, with a first sampling of a reference level, corresponding to an initialization of the readout node, then a second sampling of a signal level corresponding to the charge which is contained in the memory node at the end of the integration period and which has been transferred to said readout node for readout.

15. An active pixel image sensor comprising at least one row of active pixels, in which each active pixel comprises a memory node between a photosensitive element and a readout node of the pixel, with a first charge transfer transistor placed between the photosensitive element and the memory node and a second charge transfer transistor placed between the memory node and the readout node, and a sequencing circuit for sequencing the signals required for image capture comprising an integration period common to all of the pixels, and a phase of successively reading out the pixels of each row, wherein the sequencing circuit is configured to implement a control method according to claim 2.

16. An active pixel image sensor comprising at least one row of active pixels, in which each active pixel comprises a memory node between a photosensitive element and a readout node of the pixel, with a first charge transfer transistor placed between the photosensitive element and the memory node and a second charge transfer transistor placed between the memory node and the readout node, and a sequencing circuit for sequencing the signals required for image capture comprising an integration period common to all of the pixels, and a phase of successively reading out the pixels of each row, wherein the sequencing circuit is configured to implement a control method according to claim 3.

17. An active pixel image sensor comprising at least one row of active pixels, in which each active pixel comprises a memory node between a photosensitive element and a readout node of the pixel, with a first charge transfer transistor placed between the photosensitive element and the memory node and a second charge transfer transistor placed between the memory node and the readout node, and a sequencing circuit for sequencing the signals required for image capture comprising an integration period common to all of the pixels, and a phase of successively reading out the pixels of each row, wherein the sequencing circuit is configured to implement a control method according to claim 4.

18. An active pixel image sensor comprising at least one row of active pixels, in which each active pixel comprises a memory node between a photosensitive element and a readout node of the pixel, with a first charge transfer transistor placed between the photosensitive element and the memory node and a second charge transfer transistor placed between the memory node and the readout node, and a sequencing circuit for sequencing the signals required for image capture comprising an integration period common to all of the pixels, and a phase of successively reading out the pixels of each row, wherein the sequencing circuit is configured to implement a control method according to claim 5.

19. An active pixel image sensor comprising at least one row of active pixels, in which each active pixel comprises a memory node between a photosensitive element and a readout node of the pixel, with a first charge transfer transistor placed between the photosensitive element and the memory node and a second charge transfer transistor placed between the memory node and the readout node, and a sequencing circuit for sequencing the signals required for image capture comprising an integration period common to all of the pixels, and a phase of successively reading out the pixels of each row, wherein the sequencing circuit is configured to implement a control method according to claim 6.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other features and advantages of the invention are presented in the following description, given with reference to the appended drawings in which:

(2) FIG. 1 illustrates a general structure of an active pixel to which the invention may be applied;

(3) FIG. 2 is a timing diagram of the control signals for controlling a pixel in an image capture cycle, in a first exemplary implementation of the invention carrying out one (1) transfer/clipping operation per cycle;

(4) FIGS. 3a to 3h show, for each of phases 1 to 8 of the integration period of the cycle, the diagrams of the corresponding potentials in the structure of the pixel; and

(5) FIG. 4, the corresponding response curve of a pixel, showing the amount of charge at the readout node as a function of the luminous flux;

(6) FIGS. 5a to 5c show, for each of phases 9 to 11 of the CDS readout sequence of a pixel, the diagrams of the corresponding potentials in the structure of the pixel;

(7) FIGS. 6 and 7 show the signal timing diagram and the corresponding response curve for the pixel, for another exemplary implementation carrying out two transfer/clipping operations per image capture cycle.

DETAILED DESCRIPTION

(8) The invention pertains to an image capture method by an active pixel image sensor, with a pixel structure that comprises a memory node between the photodiode and the readout node. It is also necessary to provide a detailed description of such a structure, in order to facilitate the subsequent description of the method of the invention.

(9) Structure of the Pixels

(10) Active pixels are produced using CMOS technology in a doped (for example p-doped) active semiconductor layer and in addition comprise photodiodes, which are in principle what are referred to as pinned photodiodes, capacitive storage nodes and transistors. Embodiments thereof employ various CMOS technologies well known to those skilled in the art. The context is that of a substrate with a p-doped active semiconductor layer, which substrate is biased to a zero reference potential and the circuits of which are supplied with a positive supply voltage denoted by Vdd. The various transistors of the pixels are NMOS transistors, with source and drain regions that are n-type diffusions on either side of a p-type channel under the gate. Those skilled in the art will be capable of carrying out the necessary adaptations in the context of a substrate with an n-doped active semiconductor layer.

(11) FIG. 1 is a circuit diagram of an exemplary structure of an active pixel with a memory node between a photosensitive element and a readout node: the pixel PIX comprises a photodiode Dp, a memory node MN which is a capacitive storage node, a readout node SN which is also a capacitive storage node, and a first transfer transistor TR1 between the photodiode Dp and the memory node MN and a second transfer transistor TR2 between the memory node MN and the readout node SN.

(12) The pixel also comprises, in a conventional manner, a reset transistor RST for resetting the readout node SN, the source of which is electrically connected to the readout node and the drain of which is connected to the positive supply voltage Vdd; a follower transistor SF, the gate of which is electrically connected to the readout node SN, and the drain of which is biased to the supply voltage Vdd. In the example, the pixel comprises a selection transistor SEL, the gate of which is connected to a row conductor CL allowing the row of the pixel to be selected, the drain of which is electrically connected to the source of the follower transistor and the source of which is connected to a column conductor CC of the matrix array (the pixels being arranged in the form of a matrix, in n rows of rank j equal to 1 to n, and m columns of rank k equal to 1 to m), each column conductor CC being connected, at the foot of the column, to a readout circuit CR common to all of the pixels of the column.

(13) In the example, a sixth transistor AB is also provided, which allows the photodiode to be initialized, by removing charge via its drain. When it is not provided, the photodiodes are initialized by activating (i.e. turning on), together in each pixel, the transistors TR1, TR2 and RST.

(14) In practice, these transistors are not all necessarily constructed in a conventional manner, independently of the other elements of the pixel, with a source region, a drain region, a channel region separating the source from the drain and an insulated gate above the channel, as shown in FIG. 1. Certain transistors are, in reality, essentially composed of an insulated gate to which a control potential may be applied. Thus, for example, the first transfer transistor TR1 may be composed of a simple transfer gate TR1-g, insulated from the substrate, surmounting a p-type channel region which is located between the n-type region of the photodiode Dp (source of TR1) and the n-type region of the memory node MN (drain of TR1). Likewise: the second transfer transistor TR2 may be composed of a simple transfer gate TR2-g, insulated from the substrate, surmounting a p-type channel region which is located between the n-type region of the memory node MN (source of TR2) and the n-type region of the readout node SN (drain of TR2). Additionally, the source of the initialization transistor AB may be the n-type region of the photodiode which accumulates the charge generated by the light; and the source of the RST transistor may be the n-type region of the readout node. Throughout the rest of the description, the term gate may be used to refer to these transistors.

(15) Lastly, at least some of these transistors may be common to multiple pixels. In particular, the selection transistor SEL, the follower transistor SF and/or the initialization transistor AB of the photodiodes may be common to a plurality or all of the pixels. Additionally, the initialization transistor AB may be omitted, as stated above. Lastly, the selection transistor may also not be present, the selection function then being provided by the reset transistor, via a drain bias voltage command capable of turning the follower transistor off outside of readout phases. In this case, the source of the follower transistor is directly connected to the column conductor. All of these structural variants of active pixels are known to those skilled in the art. The invention that will be described in relation to the structure of FIG. 1 is also applicable to these various variants.

(16) The photodiode Dp of the pixels is typically a pinned photodiode pinned to a voltage denoted by Vpin defined by the technology, i.e. it comprises, on the n-type diffusion region, a superficial p-type diffusion region and the superficial region is brought to the reference potential (zero) of the substrate. For a given technology, the storage capacity of the photodiode is defined by its area.

(17) The readout node SN is generally composed of a floating n-doped semiconductor region. The charge storage capacity of this readout node is determined by its dopant concentration and its geometry.

(18) The memory node must be produced in a manner different from the floating diffusion of the readout node, since it must be possible to set its potential so as to allow it to be used as an intermediate storage node for storing the charge of the photodiode at the end of the integration period, for the time to allow the prior sampling in each pixel, in the readout phase, of the reference potential level of the readout node. However, its storage capacity must be equivalent to that of the readout node. Those skilled in the art have access to various readout node technologies for this purpose. In one example, the readout node is produced by a semiconductor region surmounted by a gate, and this gate is biased to a potential which allows the semiconductor region of the memory node to be set up under the gate at a determined potential level that is intermediate between the Vpin level of the photodiode and Vdd: it is thus possible to transfer the charge from the photodiode to the memory node at the end of the integration period; and, subsequently, to transfer the charge contained in the memory node to the readout node, in the readout phase. The applied potential may vary according to the phase in question, but, in order to simplify the following description, the potential of the memory node MN will hereinafter be considered to be a determined fixed value V.sub.MN. The charge storage capacity of the memory node depends, in this example, on the gate capacity (hence on its geometry), on the dopant concentration, etc.

(19) Other memory node structures could be used, such as those described, for example, in the patent publications WO2006130443, U.S. Pat. No. 598,629, or FR2961631.

(20) Control Method

(21) A pixel structure such as that which has been described is specially adapted to an image capture method in which an image capture cycle comprises one integration period common to all of the pixels, followed by a row-by-row readout of the pixels, i.e. a correlated double sampling readout (CDS readout). It is specified that the pixels are usually arranged in a matrix of rows and columns of pixels.

(22) Integration

(23) According to the invention, it is proposed to carry out, in the common integration period of duration Ti, at least one transfer of charge from the photodiode to the memory node, at an intermediate voltage between the start and the end of the integration period, and to clip, subsequent to each of these intermediate transfers, the amount of charge contained in the memory node, in relation to a determined threshold. The photodiode starts to accumulate charge again following the first transfer. At the end of the integration period, this new charge is transferred to the memory node, and it is added to that already contained in the memory node following the one or more transfers and clipping operations carried out in the integration period. The transfer of charge to the memory node at an intermediate voltage is controlled through the application of a first voltage pulse to the first transfer gate. The clipping of the charge contained in the memory node is achieved through the application, after this first pulse, of a second voltage pulse to the second transfer gate, and the voltage of this pulse is at a determined level which sets the clipping threshold, i.e. the maximum amount of charge that can be held in the memory node, by setting the height of the potential barrier of the semiconductor region under the gate of the second transfer transistors in relation to the potential of the memory node.

(24) This will now be described in detail, using the timing diagram of FIG. 2 and the diagrams of FIG. 3. These diagrams show the potentials in the pixel structure of FIG. 1 for the various phases {circle around (1)} to {circle around (5)} of the integration period in one exemplary implementation of the invention in which, in the integration period and simultaneously in all of the pixels, N=1 transfer followed by one (1) operation of clipping the charge contained in the memory node are carried out.

(25) In these FIG. 3, the various transistor gates are represented by a rectangle, the background colour of which indicates the value of the applied gate potential: white=zero; black=Vdd; grey=an intermediate potential between zero and Vdd.

(26) An initial state (not shown) is started from, in which the transfer transistors are in the off state. During the integration period, the initialization transistor of the readout node will generally be on (gate at Vdd), connecting the readout node SN to the supply voltage Vdd.

(27) The integration cycle starts with a phase {circle around (1)} of initializing all of the photodiodes. In the example, a voltage pulse Pi is applied to the initialization gate AB-g of the photodiodes (FIGS. 2 and 3a) which turns the initialization transistors AB fully on so as to empty the photodiodes of all charge, via their drains D.sub.AB. The end of the initialization pulse Pi turns these transistors AB off again and sets the voltage t.sub.0 of the start of the integration period common to the pixels of a new image capture cycle (FIG. 3b).

(28) According to the invention, in the period of integrating charge by the photodiode, at least one sequence of a phase {circle around (2)} of transferring the charge from the photodiode to the memory node MN, at an intermediate voltage, is envisaged, followed by a phase {circle around (3)} of clipping the charge contained in the memory node MN, before a final phase {circle around (4)} of transferring the charge to the memory node.

(29) This sequence proceeds as follows: intermediate transfer phase {circle around (2)} (FIGS. 3c and 3d): at a time t.sub.1, after the start (time t.sub.0) of the integration period, a first voltage pulse P1.sub.a is applied simultaneously to the first transfer gate TR1-g of all of the pixels, and the voltage pulse lowers the potential barrier of the semiconductor region under the gate TR1-g enough to allow the charge to be transferred from the photodiode to the memory node. In practice, the voltage pulse P1.sub.a will be between Vpin and Vdd and will be determined by the technology. All of the charge which is accumulated in the photodiode from time t.sub.0 and which the photodiode continues to generate is transferred to the memory node MN (FIG. 3c). At the end of this pulse (at time t.sub.2), the photodiode is once more isolated from the memory node and once more starts to accumulate (retain) the light-generated charge (FIG. 3d) clipping phase {circle around (3)} (FIGS. 3e and 3f): after the end of the first pulse, a second voltage pulse P2.sub.a is applied to the second transfer gate TR2-g of all of the pixels, at time t.sub.3. The voltage of this pulse is an intermediate voltage V.sub.a which sets up a height h.sub.a of the potential barrier under the second gate in relation to the potential V.sub.MN of the memory node: this barrier height sets a maximum amount of charge Q0 that can be held in the memory node (represented by the pattern of oblique dashes in FIG. 3e): the excess charge is removed in the direction of the power supply source Vdd, via the readout node SN and the reset transistor, which, at least for this time of the integration period, is turned on. In practice, V.sub.a is a voltage that is preferably between 0 and V.sub.MN, defined depending on the technology so as to obtain the desired threshold Q0 (beyond V.sub.MN, there will be no significant clipping effect). At the end of the second pulse P2.sub.a, the memory node is once more completely isolated from the readout node SN and from the photodiode (FIG. 3f).
It should be noted that the readout node and the reset transistor RST of the readout node provide a natural route for the removal of excess charge from the memory node. However, other modes of implementation may envisage a specific removal structure, with a dedicated transistor, which would be turned on in the active clipping phases {circle around (3)}.

(30) After this sequence of transfer and clipping phases in the integration period, there follows the final transfer phase {circle around (4)}, marking the end of the integration period (FIGS. 3g and 3h). In this phase {circle around (4)}, a voltage pulse Pf is applied, at time t.sub.f, to the gates of the first transfer transistors, and the end (falling edge) of this final pulse marks the end of the integration period for all of the pixels, at time t.sub.0+Ti. This pulse allows the charge accumulated by the photodiode since the end of the first transfer pulse to be transferred to the memory node MN: this charge is added to that held in the memory node following the transfer and clipping phases {circle around (2)} and {circle around (3)} (FIG. 3g) in order to make up the amount of charge representative of the signal level captured by the pixel. It is this level which will subsequently be read out in the readout phase, which is carried out in a conventional manner, preferably with correlated double sampling.

(31) The transfer phase {circle around (2)} at time t.sub.1 in the integration period results in the integration period T.sub.i being divided into two successive integration durations Ti.sub.a and Ti.sub.b; and the following clipping phase {circle around (3)}, carried out at the end of the first integration duration Ti.sub.a, then allows the dynamic range of the pixel to be extended, i.e. the capacity of the pixel to avoid saturation in the event of high levels of illumination without changing its sensitivity to low levels of illumination.

(32) This is shown by the corresponding response curve of FIG. 4, which represents the amount of charge obtained at the end of one integration period, which is therefore the final amount of charge in the memory node, as a function of luminous flux F.

(33) Specifically, there are two possibilities: either the luminous flux F received by the photodiode in the first integration period is quite low, resulting in an amount of light-generated charge Q.sub.a (FIG. 2) that is smaller than or equal to the amount of charge Q0; or the luminous flux F is higher, above a threshold F0, which produces, after time Ti.sub.a, the amount of charge Q0.

(34) In the first case, the amount of charge Q.sub.a transferred to the memory node in phase {circle around (2)} remains in the memory node at the end of the clipping phase {circle around (3)}, since it is trapped by the potential barrier set up under the second gate TR2-g; this amount Q.sub.a is proportional to F and Ti.sub.a. The accumulation of charge, which is resumed at the end of the first transfer and continues for the duration Ti.sub.b, generates a charge Q.sub.b proportional to F and Ti.sub.b. In the final transfer phase {circle around (4)}, charge accumulated in the photodiode in the second integration duration Ti.sub.b is transferred to the memory node MN and it is added to the previous charge: at the end of the duration Ti.sub.b, the memory node contains the amount of charge Q.sub.a+Q.sub.b, which is proportional to the intensity F of the luminous flux and to the total integration duration Ti=Ti.sub.a+Ti.sub.b; and it is this amount of charge Q.sub.a+Q.sub.b that will be read out in the following pixel readout sequence.

(35) Thus, when the luminous flux is below the threshold F0, the amount of charge stored in the pixel, which forms the output signal of the pixel, is proportional to the intensity F and to the total integration duration Ti=Ti.sub.a+Ti.sub.b. The response curve of the total charge Q=Q.sub.a+Q.sub.b as a function of F, shown in FIG. 4, has a first, linear section (for E<E0) with a slope that is determined by the total duration Ti=Ti.sub.a+Ti.sub.b.

(36) In the second case, the amount of charge Q.sub.a photogenerated by the photodiode in the first integration duration Ti.sub.a is above the threshold Q0: then the surplus charge is emptied in the clipping phase {circle around (3)}; only the threshold value Q0 remains in the memory node at the end of this phase. In the second integration duration Ti.sub.b, the photodiode accumulates an amount Q.sub.b of new photogenerated charge which is proportional to the intensity of the flux F and duration Ti.sub.b. The result of this, at the end of the second integration duration Ti.sub.b and as the outcome of the final transfer phase {circle around (4)}, is that the memory node MN comprises an amount of charge which is the sum of Q0+Q.sub.b. Stated otherwise, the final amount of charge is proportional to F0.Math.Ti.sub.a+F.Math.Ti.sub.b, which may also be written as F0.Math.(Ti.sub.a+Ti.sub.b)+(FF0).Math.Ti.sub.b, in which F is the received luminous flux that is above F0, and F0 is the luminous flux up to the charge threshold Q0.

(37) The response curve beyond F0 is therefore a straight line, the slope of which is gentler, in terms of the ratio Ti.sub.b/(Ti.sub.a+Ti.sub.b), than the slope of the straight line below F0.

(38) Overall, the curve of the total amount of charge as a function of the illumination is a broken straight line with two successive slopes, the first slope being steeper, allowing the sensor to retain good sensitivity to low levels of luminous flux, and the second, gentler slope allowing the dynamic range of the sensor to be extended to high levels of flux: if it is assumed that the photodiode is saturated for an amount of charge Qs, it may be seen that this quantity of charge is reached for a level of luminous flux Fs1 that is higher than it would have been if the curve comprised only the first slope (in which case it is saturated for the flux Fs0 referenced in FIG. 4). The dynamic range, i.e. the capacity of the pixel to avoid saturation in the event of high levels of illumination (second portion of the curve), has therefore been increased, from Fs0 to Fs1, without decreasing sensitivity to low levels of illumination (first portion of the curve).

(39) The response curve at extended dynamic range may thus be regulated by the values V.sub.a and Ti.sub.b, for an integration period of determined duration T.sub.i (this value T.sub.i determining the slope of the first straight line): the choice of the potential V.sub.a applied to the second transfer gate TR2-g in phase {circle around (3)} determines the point at which the slope changes at a chosen value for Q0; and the second integration duration Ti.sub.b, preferably shorter than the first duration Ti.sub.a, determines the slope of the second straight line. It is typically possible to choose a second integration duration Ti.sub.b that is equal to 5 to 10% of Ti.sub.a.

(40) It is possible to generalize to N intermediate transfer/clipping operation(s). For example, FIG. 7 illustrates the change in the response curve that would occur if a second transfer/clipping operation to Q0 were carried out after the first transfer/clipping operation to Q0, and before the final transfer, according to the timing diagram of FIG. 6. Namely then, in the total duration Ti of the integration period, the sequence of the transfer and clipping phases {circle around (2)} and {circle around (3)} is repeated N=2 times before the end of the integration period. However, less will be clipped the second time in comparison with the first time, in order to retain a charge Q0, higher than the charge Q0 defined by the first clipping, in the memory node: the second pulse P2.sub.b applied to the second transfer gates TR2-g thus has a voltage level V.sub.b that is lower than the level V.sub.a applied the first time; this level V.sub.b defines a potential barrier height under these second gates that is higher than the height h.sub.a of the first sequence. The charge Q0 thus defined by the voltage V.sub.b corresponds to a second illumination threshold F0. The integration period Ti is then broken down into three successive integration durations Ti.sub.a, Ti.sub.b and Ti.sub.c, which are preferably of increasingly shorter length. Additionally, the response curve comprises not one but two break points, corresponding to the points (Q0, F0) and (Q0, F0).

(41) Beyond the level of illumination F0, and below a value Fs1 that would saturate the pixel, the total amount of charge present in the memory node MN after the second clipping operation is proportional to F0.Math.(Ti.sub.a+Ti.sub.b+Ti.sub.c)+(F0F0).Math.(Ti.sub.b+Ti.sub.c)+(FF0).Math.Ti.sub.c. The first slope is defined by the total integration duration Ti; the second slope is defined by the duration Ti.sub.b+Ti.sub.c; the third slope is defined by the duration Ti.sub.c. It may be seen from the curve of FIG. 6 that the saturation illumination value Fs1 may be higher than the preceding value Fs1, while retaining higher sensitivity in the portion between F0 and F0 only if a single direct slope between the point (F0, Q0) and the saturation point (Fs1, Qs) had been chosen.

(42) In theory, it is possible to generalize the control method to N transfer/clipping operations before the final transfer. However, in practice, the choice of N=2 transfer/clipping operations is advantageous, with optimized sensitivity over the entire range. Beyond N=2, there are substantial technological constraints on the clipping thresholds that may be set.

(43) Provision may also be made for the value of N to be set according to a measurement of the ambient light, preferably between the values 1 and 2. For example, it is possible to make provision for N to be chosen to be equal to 1 in a context of average ambient light and to be equal to 2 if more extreme levels of ambient light may be measured.

(44) Readout

(45) Once the integration period has ended, the phase of reading out the pixels may start. The readout is performed sequentially, row by row, in the usual manner of the prior art. Preferably, the readout is of correlated double sampling type. It is performed in the following manner, as illustrated by FIGS. 2 and 5: each row of pixels of rank j (j=1 to n) is selected one at a time, by a respective selection control pulse SEL<j> which, in the example, is applied to the gate SEL-g of the selection transistor SEL. The effect of this selection for each pixel of the row is to electrically connect the source of the follower transistor SF to the associated column conductor CC<k>, and therefore to the readout circuit CR at the foot of the column (FIG. 1). The CDS readout of the pixels is carried out during this selection time, while isolating the readout node from the supply voltage Vdd (the potential of the gate RST-g of the pixels of the selected row is brought to 0), and comprises the series of following phases {circle around (5)} to {circle around (7)}: phase {circle around (5)}: the reference potential of the readout node SN is sampled in the readout circuit at the foot of the column. This sampling is represented in FIGS. 2 and 5a by the command SHR. phase {circle around (6)}: the second transfer transistor TRA.sub.2 of the pixels of the selected row is turned fully on by a voltage pulse of level Vdd, applied to their gate TRA.sub.2-g, allowing all of the charge held in the memory node MN to be transferred to the readout node SN (SHS, FIGS. 2, 5b and 5c). phase {circle around (7)}: At the end of this transfer pulse, the potential of the column conductor CC<k> is set at a signal level representative of the amount of charge in the readout node and this signal level is sampled in the readout circuit at the foot of the column.

(46) This readout sequence is applied simultaneously to all of the pixels of the selected row, then repeated for each of the rows of pixels of the sensor, successively, until the last row.

(47) A new integration period of a new integration cycle and subsequent readout may start with a new photodiode reset phase {circle around (1)}. In practice, the new cycle may start as soon as the last final transfer defined by phase {circle around (4)} has ended.

(48) The various control signals of the various sequences are delivered, in the conventional manner, by a sequencing circuit SQ for sequencing the pixels of the matrix (FIG. 1) on the basis of supply and clock signals of the sensor.

(49) The invention that has been described is particularly advantageous for miniaturized sensors if it is additionally envisaged to implement it with memory node technologies offering a capacity per unit area that is intrinsically higher than that permitted by pinned photodiode technologies.