Electronic device providing a temperature sensor or a current source delivering a temperature independent current

Abstract

An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.

Claims

1. An electronic device, comprising: a circuit module having a first output terminal that is configured to deliver a positive temperature coefficient output voltage; wherein the circuit module comprises: a thermistor having a first MOS transistor configured to operate in weak inversion mode and have a negative temperature coefficient drain-source resistance and whose source is coupled to said first output terminal, and a current source having a control terminal coupled to the first output terminal and configured to impose a drain-source current of the first MOS transistor.

2. The device according to claim 1, wherein the current source comprises a second MOS transistor having a gate that is coupled to the first output terminal, the second MOS transistor being configured to operate in strong inversion mode and have a gate leakage current configured to impose the drain-source current of the first MOS transistor.

3. The device according to claim 2, wherein the first and second MOS transistors are NMOS transistors.

4. The device according to claim 2, wherein the gate leakage current of the second MOS transistor has a same order of magnitude as the drain-source current of the first MOS transistor.

5. The device according to claim 4, wherein a thickness of a gate oxide of the second MOS transistor is less than 2 nm.

6. The device according to claim 2, further comprising: a negative temperature coefficient MOS transistor having a gate that is coupled to a drain of the first MOS transistor, a source that is coupled to a source of the second MOS transistor of the circuit module, and a drain that is coupled to a drain of the second MOS transistor, wherein the sources of the second MOS transistor and the negative temperature coefficient MOS transistor form a second output.

7. The device according to claim 6, wherein the negative temperature coefficient MOS transistor is an NMOS transistor.

8. The device according to claim 6, wherein said second output generates a substantially temperature-independent output current.

9. The device according to claim 6, produced on a silicon-on-insulator substrate, wherein each of the first MOS transistor, the second MOS transistor and the negative temperature coefficient MOS transistor has a back gate, and the back gates are coupled together to receive a common voltage.

10. The device according to claim 9, wherein the silicon-on-insulator substrate is a fully or partly depleted silicon-on-insulator substrate.

11. The device according to claim 6, wherein the device is a component of an electronic appliance selected from the group consisting of a cellular mobile telephone, a tablet and a laptop computer.

12. The device according to claim 1, wherein said circuit module forms a temperature sensor with an output voltage at said first output terminal varying proportionally to temperature.

13. The device according to claim 1, produced in an integrated manner.

14. The device according to claim 13, produced on a silicon-on-insulator substrate.

15. The device according to claim 14, wherein the silicon-on-insulator substrate is a fully or partly depleted silicon-on-insulator substrate.

16. The device according to claim 1, produced on a silicon-on-insulator substrate, wherein each of the first MOS transistor and the second MOS transistor has a back gate, and the back gates are coupled together to receive a common voltage.

17. The device according to claim 1, wherein the device is a component of an electronic appliance selected from the group consisting of a cellular mobile telephone, a tablet and a laptop computer.

18. An electronic device, comprising: a first MOS transistor configured as a thermistor and having a source coupled to a first output terminal, a drain coupled to a supply voltage node and a gate coupled to the drain such that the first MOS transistor operates in a weak inversion mode with a negative temperature coefficient drain-source resistance; and a second MOS transistor configured as a current source and having a gate coupled to the first output terminal to impose a drain-source current of the first MOS transistor, a drain and a source.

19. The device according to claim 18, wherein the second MOS transistor operates in strong inversion mode and has a gate leakage current which imposes the drain-source current of the first MOS transistor.

20. The device according to claim 18, wherein the first and second MOS transistors are NMOS transistors.

21. The device according to claim 18, wherein an output voltage at said first output terminal varies proportionally to temperature.

22. The device according to claim 18, produced on a silicon-on-insulator substrate, wherein each of the first MOS transistor and the second MOS transistor has a back gate, and the back gates are coupled together to receive a common voltage.

23. An electronic device, comprising: a first MOS transistor configured as a thermistor and having a source coupled to a first node, a drain coupled to a control node and a gate coupled to a supply voltage node; a second MOS transistor configured as a current source and having a gate coupled to the first node to impose a drain-source current of the first MOS transistor, a drain coupled to the supply voltage node and a source coupled to an output node; and a third MOS transistor having a gate coupled to the control node, a drain coupled to the supply voltage node and a source coupled to the output node.

24. The device according to claim 23, wherein the first, second and third MOS transistors are NMOS transistors.

25. The device according to claim 23, wherein the output node generates a current which is substantially temperature-independent.

26. The device according to claim 23, produced on a silicon-on-insulator substrate, wherein each of the first MOS transistor, the second MOS transistor and the third MOS transistor has a back gate, and the back gates are coupled together to receive a common voltage.

27. The device according to claim 26, wherein the silicon-on-insulator substrate is a fully or partly depleted silicon-on-insulator substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantages and features of the invention will become apparent upon examining the detailed description of completely non-limiting embodiments and the appended drawings, in which:

(2) FIG. 1 illustrates an electronic appliance with a temperature sensing circuit module;

(3) FIG. 2 is a circuit diagram for an embodiment of the temperature sensing circuit module;

(4) FIG. 3 illustrates a SPICE simulation of the temperature sensing circuit module of FIG. 2;

(5) FIG. 4 is a circuit diagram for an embodiment of a temperature insensitive current source circuit; and

(6) FIG. 5 illustrates a SPICE simulation of the temperature insensitive current source circuit of FIG. 4.

DETAILED DESCRIPTION

(7) Reference 1 in FIG. 1 denotes an electronic appliance, in this case for example a cellular mobile telephone designed to withstand extreme environmental conditions, such as a significant temperature variation.

(8) The electronic appliance 1 includes an electronic device 2 intended to be used to minimize the influence of the ambient temperature variation.

(9) The electronic device 2 in this case includes a circuit module 3 operating as a temperature sensor and produced in an integrated manner, preferably on a fully depleted silicon-on-insulator substrate, commonly known to those skilled in the art under the acronym FDSOI.

(10) It should be noted that the electronic device 2 may also be produced on a partly depleted silicon-on-insulator substrate, commonly known to those skilled in the art under the acronym PDSOI, whose silicon film covering the buried insulating layer (BOX: buried oxide) preferably has a thickness that is not too great so as to avoid memory effects, for example a thickness close to that of the semiconductor film of a fully depleted silicon-on-insulator (FDSOI) substrate.

(11) Reference is now made to FIG. 2 in order to illustrate in more detail one exemplary embodiment of the circuit module 3, which includes: a thermistor 4 including a first MOS transistor T1, in this case for example an NMOS transistor, whose source S1 is coupled to an output terminal BS of the circuit module, and whose drain D1 and gate G1 are jointly coupled to a supply voltage VDD, and a current source 5 including a second MOS transistor T2, in this case for example an NMOS transistor, whose gate G2 is coupled to the output terminal BS, and whose drain D2 and source S2 are jointly coupled to ground GND.

(12) Said supply voltage VDD may, for example, be 1 V, so that the first transistor T1 is in weak inversion mode, that is to say having a gate-source voltage lower than its threshold voltage.

(13) In this case, the output voltage Vout at the output terminal BS, in other words the gate voltage Vg2 of the second transistor T2, is variable between 0.6 V and 0.95 V, thereby allowing operation of the second transistor T2 in strong inversion mode, that is to say having a gate-source voltage higher than its threshold voltage.

(14) It should be noted that the drain D2 of the second transistor T2 may also be coupled to a supply voltage, for example of 1 V, at the expense of an increase in the power consumption of the second transistor T2.

(15) As the second transistor T2 operates in strong inversion mode, there is a gate leakage current Ig2 of the second transistor T2 that imposes the drain-source current Ids1 of the first transistor T1. The orders of magnitude of the gate leakage current Ig2 and of the drain-source current Ids1 of the first transistor T1 are substantially equal. By way of indication, these leakage currents are of the order of about one hundred picoamperes.

(16) To this end, the thickness of the gate oxide of the second transistor T2 is preferably less than 2 nm.

(17) It should be noted that the back gates GA1, GA2 of the first and second transistors T1 and T2 are coupled to ground GND and are not used to control the first and second transistors T1 and T2.

(18) FIG. 3 illustrates a SPICE (Simulation Program with Integrated Circuit Emphasis) simulation of the module 3 as a function of the temperature, within a range between 150 C. and 200 C.

(19) As is seen from the curve CB1 of FIG. 3, the output voltage Vout varies proportionally to the temperature. The output voltage Vout varies substantially linearly between 0.6 V and 0.95 V.

(20) Due to this, said module 3 forms a temperature sensor that makes it possible to detect the temperature on the basis of the measured output voltage Vout.

(21) The electronic device 2 may further or alternatively include a circuit module 10 operating as a temperature insensitive circuit and produced in an integrated manner, preferably on an FDSOI substrate. The electronic device 2 may be used for other purposes than a cellular mobile telephone.

(22) In this variant embodiment, the circuit module 10, that will be seen hereinafter to be temperature-insensitive, is capable of delivering, on its output, a substantially temperature-independent current.

(23) The electronic device 2 illustrated here in FIG. 4 is produced, for example, in the same way in terms of technology as that illustrated in FIG. 2.

(24) Said circuit 10 includes: the circuit module 3 as illustrated in FIG. 2, and a third MOS transistor T3, in this case for example also an NMOS transistor, whose gate G3 is coupled to the drain D1 of the first transistor T1, whose source S3 is coupled to the source S2 of the second transistor T2, and whose drain D3 is coupled to the drain D2 of the second transistor T2.

(25) The sources S2, S3 of the second and third transistors T2, T3 form an output OUT delivering an output current Tout.

(26) This output OUT could possibly be coupled to ground GND by way or not by way of a load.

(27) The drains D2, D3 of the second and third transistors T2, T3 are jointly coupled to a supply voltage VDD, for example of 1 V.

(28) The gate G1 of the first transistor T1 of the module 3 is also coupled to the supply voltage VDD.

(29) The third transistor T3 is a conventional negative temperature coefficient transistor.

(30) The gate G3 of the third transistor T3 and the drain D1 of the first transistor T1 are coupled and form a control terminal BC.

(31) When the control terminal BC is coupled to a supply voltage, for example the supply voltage VDD, the third transistor T3 operates in strong inversion mode, in other words its gate-source voltage is greater than its threshold voltage.

(32) When the third transistor T3 operates in strong inversion mode, the drain-source current Ids3 of the third transistor T3 varies in a manner inversely proportional to the ambient temperature.

(33) At the same time, the gate voltage Vg2 of the second transistor T2 varies proportionally to the ambient temperature, as illustrated in FIG. 3.

(34) As a result, the drain-source current Ids2 of the second transistor T2, being controlled by the gate voltage Vg2, varies proportionally to the ambient temperature. In other words, the second transistor T2 operating in strong inversion mode has a positive temperature coefficient.

(35) By appropriately choosing the dimensions of the second and third transistors T2, T3 in such a way as to adjust the values of the currents Ids2 and Ids3, the output current Tout, which is the sum of these two currents, is able to be temperature-independent.

(36) In other words, in this case, the output current Tout remains stable regardless of the ambient temperature.

(37) It should be noted that said circuit 10 advantageously requires only one control voltage at the control terminal BC so as to control the operation of the current source, this being different from a conventional solution that generally requires two precise control voltages to be applied to the gates G2, G3 of the second and third transistors T2, T3, respectively.

(38) In this exemplary embodiment, the back gates GA1, GA2, GA3 of the first, second and third transistors T1, T2, T3 are jointly coupled to ground GND and are not used to control the operation of the current source, this also being different from a conventional solution that requires control operations for the back gates of the transistors.

(39) That being said, as a variant, the back gates GA1, GA2, GA3 of the first, second and third transistors T1, T2, T3 could be individually biased in order for example to allow additional channel control operations for these transistors.

(40) In addition, the thermistor 4 may include an additional transistor, for example diode-connected and coupled between the source S1 of the first transistor T1 and the gate G2 of the second transistor T2, so as to increase the equivalent resistance of the thermistor 4.

(41) Reference is now made to FIG. 5 in order to illustrate a SPICE simulation of a circuit 10 when the control terminal BC of said circuit 10 is coupled to a supply voltage VDD of 1 V.

(42) By way of non-limiting example, the length of the channel of the first transistor T1 is 500 nm and the lengths of the channels of the second and third transistors are equal to 30 nm. The widths of the channels of the first, second and third transistors T1, T2, T3 are 500 nm, 1 m, 3.75 m, respectively.

(43) FIG. 5 also illustrates a SPICE simulation using a reference transistor that is equivalent to the combination of the second and third transistors T2, T3. The length of the channel of the reference transistor is identical to those of the second and third transistors T2, T3, and the width of the channel of the reference transistor is equal to the sum of those of the second and third transistors T2, T3, i.e. 4.75 m.

(44) Specifically, a person skilled in the art knows to use such a conventional negative temperature coefficient reference transistor in order to compare its drain-source current with the output current of an equivalent temperature-insensitive current source. A large offset between its drain-source currents may generally be observed with temperature-insensitive current sources from the prior art.

(45) FIG. 5 shows that the variation in the drain-source current Ids2 of the second transistor T2 is proportional to the temperature variation. The variations in the drain-source currents Ids3 and Idsref of the third transistor T3 and of the reference transistor are inversely proportional to the temperature variation.

(46) The output current Tout, which is the sum of the currents Ids2 and Ids3, is substantially constant regardless of the temperature.

(47) Advantageously in comparison with the case of a conventional temperature-insensitive current source, there is very little offset between the output current Tout and the drain-source current Idsref of the reference transistor.

(48) Due to this, degradation in terms of the output current in comparison with the reference transistor is reduced, and the performance of the circuit 10 forming a temperature-independent current source is advantageously greater than that of a conventional temperature-insensitive current source.

(49) What is thus obtained is an electronic device that makes it possible to detect the temperature and to deliver a temperature-independent current with a single control supply voltage, while at the same time using a circuit that is unobtrusive, not complex, has lower power consumption and exhibits better performance.