Abstract
A method for producing thin MEMS wafers including: (A) providing an SOI wafer having an upper silicon layer, a first SiO2 layer and a lower silicon layer, the first SiO2 layer being situated between the upper silicon layer and the lower silicon layer, (B) producing a second SiO2 layer on the upper silicon layer, (C) producing a MEMS structure on the second SiO2 layer, (D) introducing clearances into the lower silicon layer down to the first SiO2 layer, (E) etching the first SiO2 layer and thus removing the lower silicon layer.
Claims
1. A method for producing thin MEMS wafers, comprising: (A) providing an SOI wafer having an upper silicon layer, a first SiO2 layer and a lower silicon layer, the first SiO2 layer being situated between the upper silicon layer and the lower silicon layer; (B) producing a second SiO2 layer on the upper silicon layer; (C) producing a MEMS structure on the second SiO2 layer; (D) introducing clearances into the lower silicon layer that extend to the first SiO2 layer; and (E) etching the first SiO2 layer and thus removing the lower silicon layer, wherein, following step (A) and prior to step (B), trenches are etched into the upper silicon layer, which extend to the first SiO2 layer and which surround at least one partial area of the upper silicon layer, wherein the trenches are filled with an SiO2 filling and in step (B) the second SiO2 layer is produced at least on the partial area of the upper silicon layer.
2. The method for producing thin MEMS wafers as recited in claim 1, wherein, following step (D), the first SiO2 layer is etched away in the clearances and subsequently the clearances are driven onward to the second SiO2 layer by etching the upper silicon layer.
3. The method for producing thin MEMS wafers as recited in claim 2, wherein the second SiO2 layer is also etched in step (E).
4. The method for producing thin MEMS wafers as recited in claim 1, wherein in step (C) the MEMS structure is produced at least partially above the partial area of the upper silicon layer, at least one access channel to the partial area being created.
5. The method for producing thin MEMS wafers as recited in claim 4, wherein after step (C) and prior to step (D) the upper silicon layer is etched in the partial area, etching medium being introduced through the access channel and thus a cavity being created from the partial area.
6. The method for producing thin MEMS wafers as recited in claim 5, wherein subsequently SiO2 , which bounds the cavity, is etched, whereby SiO2 filling as well as areas of the first SiO2 layer and of the second SiO2 layer that border the cavity are removed.
7. The method for producing thin MEMS wafers as recited in claim 6, wherein in step (D) the clearances are introduced extending to the first SiO2 layer and to the cavity.
Description
BRIEF DESCRIPTION OF EXAMPLE EMBODIMENTS
(1) FIGS. 1a-f show a first specific example embodiment of the method of the present invention for producing thin MEMS wafers.
(2) FIGS. 2a-I show a second specific example embodiment of the method of the present invention for producing thin MEMS wafers.
(3) FIG. 3 shows schematically an example method of the present invention for producing thin MEMS wafers.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
(4) FIGS. 1a-f show a first specific embodiment of an example method of the present invention for producing thin MEMS wafers.
(5) FIG. 1a shows an SOI wafer that is provided for the example method of the present invention. The SOI wafer 10 has a standard thickness of 725 m+25 m, for example. An upper silicon layer 20 has a thickness of approx. 200 m. Below it is a first SiO2 layer 30 in the form of a buried oxide layer having a thickness of approx. 1 m. Below it is a lower silicon layer 40 having a thickness of approx. 525 m.
(6) FIG. 1b shows the SOI wafer having MEMS structures on the front side. SOI wafer 10 has a second SiO2 layer 60 on a front side, i.e., on an upper side of upper silicon layer 20. A MEMS structure 50 is produced on it. On a back side of the wafer, i.e. on a bottom side of lower silicon layer 40, an etching mask 70 (lithography mask) is situated for a subsequent etching process. Beforehand, it is possible to back-thin the wafer using standard grinding technology such as CMP, for example. The wafer is back-thinned for example to a thickness of 400-500 m (not illustrated).
(7) FIG. 1c shows the SOI wafer after half of the trench step. Clearances 80 are etched into lower silicon layer 40 from the back side through mask 70. The buried first SiO2 layer 30 is used as a stop layer in this instance.
(8) Subsequently, the first SiO2 layer 30 is etched away in clearances 80. FIG. 1d shows SOI wafer 10 after the buried first SiO2 layer 30 has been etched.
(9) Subsequently, clearances 80 are driven onward to second SiO2 layer 60 in that upper silicon layer 20 is etched. Etching mask 70 is subsequently removed. FIG. 1e shows the SOI wafer after [completion of] the second half of the trench step and the removal of the lithography mask. Second SiO2 layer 60 below MEMS structure 50 is used as a stop layer.
(10) FIG. 1f shows the finished thin MEMS wafer at the end of the method of the present invention in the first specific embodiment. For this purpose, first SiO2 layer 30 and second SiO2 layer 60 are etched from the back side. Etching first SiO2 layer 30 underetches the lower silicon layer 40, detaches it from the MEMS wafer and thus removes it. The silicon portions outside the desired thickness of 20-200 m are removed in this etching operation. A thin MEMS wafer is thereby produced. It is optionally possible to preserve an edge region of the wafer so that the entire structure remains stiff.
(11) FIGS. 2a-i show a second specific embodiment of the method of the present invention for producing thin MEMS wafers.
(12) FIG. 2a shows a provided SOI wafer 10 as in FIG. 1a. The SOI wafer 10 has a standard thickness of 725 m+25 m, for example. An upper silicon layer 20 has a thickness of approx. 200 m. Below it is a first SiO2 layer 30 in the form of a buried oxide layer having a thickness of approx. 1 m. Below it is a lower silicon layer 40 having a thickness of approx. 525 m.
(13) FIG. 2b shows that trenches 90 are etched into upper silicon layer 20, which extend to first SiO2 layer 30 and which surround partial areas 115 of upper silicon layer 20.
(14) FIG. 2c shows that trenches 90 are filled with an SiO2 filling 100. The purpose of filling the shafts with SiO2 is to smooth the topography on the front side and to provide a future boundary for exposing functional structures by etching. At the same time, in the same process step, a second SiO2 layer 60 is produced at least on the partial areas 115 of upper silicon layer 20. The second SiO2 layer 60 is subsequently structured in such a way that is has at least one access to partial area 115.
(15) FIG. 2d shows the production of MEMS structures on second SiO2 layer 60. MEMS structures 50 are shown schematically, which are produced at least partially above partial area 115 of upper silicon layer 20, at least one access channel 110 being created to partial area 115. The access channel may additionally also have a separate function for the MEMS structure, for example for microphones.
(16) FIG. 2e shows the production of cavities below the MEMS structures. The upper silicon layer 20 is etched in partial areas 115, the etching medium being respectively introduced through access channel 110. A cavity 120 is thus produced from the partial area 115. XeF2 may be used for etching, for example, or another isotropic dry etching process.
(17) FIG. 2f shows the removal of SiO2 from the walls of the cavity. Following the production of the cavity itself, the SiO2 that bounds cavity 120 is etched, whereby in particular the SiO2 filling 100 as well as areas of the first SiO2 layer 30 and of the second SiO2 layer 60 that border the cavity are removed. Thus, SiO2 is etched everywhere around the created cavities through the channels of the functional structures.
(18) FIG. 2g shows the lithography of access shafts to the buried first SiO2 layer on the back side. For this purpose, an etching mask 70, the lithography mask, is applied on lower silicon layer 40. The mask is independent of the functional structures, in particular the MEMS structure 50. Hence it may be optimized relatively freely in a desired shape.
(19) FIG. 2h shows the wafer after trench etching and stripping of the mask. Through etching mask 70, clearances 80 are etched into lower silicon layer 40, which extend to first SiO2 layer 30 and to cavity 120. First SiO2 layer 30 is used as an etching stop layer in this instance. Etching mask 70 is subsequently removed.
(20) FIG. 2i shows the finished thin MEMS wafer at the end of the method of the present invention in the second specific embodiment. First SiO2 layer 30 is etched from the back side. Etching first SiO2 layer 30 underetches the lower silicon layer 40, detaches it from the MEMS wafer and thus removes it. The result is a thin MEMS wafer, whose thickness is essentially determined by the height of the MEMS structure 50 and by the thickness of upper silicon layer 20. The silicon portions outside the desired thickness of 20-200 m are removed in this etching operation. It is optionally possible to preserve an edge region of the wafer so that the entire structure remains stiff.
(21) FIG. 3 shows schematically the example method of the present invention for producing thin MEMS wafers. The method includes the following steps: (A) providing an SOI wafer having an upper silicon layer, a first SiO2 layer and a lower silicon layer, the first SiO2 layer being situated between the upper silicon layer and the lower silicon layer, (B) producing a second SiO2 layer on the upper silicon layer (C) producing a MEMS structure on the second SiO2 layer, and (D) introducing clearances into the lower silicon layer down to the first SiO2 layer, (E) etching the first SiO2 layer and thus removing the lower silicon layer.
LIST OF REFERENCE SYMBOLS
(22) 10 SOI wafer 20 upper silicon layer 30 first SiO2 layer 40 lower silicon layer 50 MEMS structures 60 second SiO2 layer 70 etching mask 80 clearance 90 trench 100 SiO2 filling 110 access channel 115 partial areas of the upper silicon layer 120 cavity
