Input/output (I/O) circuit with dynamic full-gate boosting of pull-up and pull-down transistors

Abstract

An aspect of the disclosure relates to an apparatus including an output driver, including: a first p-channel metal oxide semiconductor field effect transistor (PMOS FET); a second PMOS FET coupled in series with the first PMOS FET between an upper voltage rail and an output; a first n-channel metal oxide semiconductor field effect transistor (NMOS FET); and a second NMOS FET coupled in series with the first NMOS FET between the output and a lower voltage rail; a first predriver coupled to gates of the first and second PMOS FETs and first and second NMOS FETs; and a second predriver coupled to the gates of the first and second PMOS FETs and first and second NMOS FETs.

Claims

1. An apparatus, comprising: an output driver, comprising: a first p-channel metal oxide semiconductor field effect transistor (PMOS FET); a second PMOS FET coupled in series with the first PMOS FET between a first voltage rail and an output; a first n-channel metal oxide semiconductor field effect transistor (NMOS FET); and a second NMOS FET coupled in series with the first NMOS FET between the output and a second voltage rail; a first predriver coupled to gates of the first and second PMOS FETs and to gates of the first and second NMOS FETs; and a second predriver coupled to the gates of the first and second PMOS FETs and to gates of the first and second NMOS FETs.

2. The apparatus of claim 1, wherein the first predriver comprises a pull-up predriver coupled to the gate of the first PMOS FET.

3. The apparatus of claim 2, wherein the pull-up predriver comprises: an inverter including an input configured to receive an input signal, and an output coupled to the gate of the first PMOS FET; and a third PMOS FET coupled in series with the inverter between the first voltage rail and a third voltage rail, wherein the third PMOS FET is configured to receive a pull-up gate boosting enable signal.

4. The apparatus of claim 1, wherein the second predriver comprises a pull-up predriver coupled to the gate of the first PMOS FET.

5. The apparatus of claim 4, wherein the pull-up predriver comprises: a third NMOS FET coupled between the first voltage rail and the gate of the first PMOS FET, wherein the third NMOS FET includes a gate configured to receive a first bias voltage; a diode-connected NMOS FET; a fourth NMOS FET including a gate configured to receive a second bias voltage; and a fifth NMOS FET coupled in series with the diode-connected NMOS FET and the fourth NMOS FET between the gate of the first PMOS FET and the second voltage rail, wherein the fifth NMOS FET includes a gate configured to receive a pull-up gate boosting enable signal.

6. The apparatus of claim 1, wherein the first predriver comprises a pull-up predriver coupled to the gate of the second PMOS FET.

7. The apparatus of claim 6, wherein the pull-up predriver comprises a third PMOS FET including a source configured to receive a bias voltage, a gate configured to receive a pull-up gate boosting enable signal, and a drain coupled to the gate of the second PMOS FET.

8. The apparatus of claim 1, wherein the second predriver comprises a pull-up predriver coupled to the gate of the second PMOS FET.

9. The apparatus of claim 8, wherein the pull-up predriver comprises: a third NMOS FET coupled between the first voltage rail and the gate of the second PMOS FET, wherein the third NMOS FET includes a gate configured to receive a bias voltage; a diode-connected NMOS FET; and a fourth NMOS FET coupled in series with the diode-connected NMOS FET between the gate of the second PMOS FET and the second voltage rail, wherein the fourth NMOS FET includes a gate configured to receive a pull-up gate boosting enable signal.

10. The apparatus of claim 1, wherein the first predriver comprises a pull-down predriver coupled to the gate of the second NMOS FET.

11. The apparatus of claim 10, wherein the pull-down predriver comprises: a third NMOS FET including a gate configured to receive a pull-down gate boosting enable signal; and an inverter coupled in series with the third NMOS FET between a third voltage rail and the second voltage rail, wherein the inverter includes an input configured to receive an input signal, and an output coupled to the gate of the second NMOS FET.

12. The apparatus of claim 1, wherein the second predriver comprises a pull-down predriver coupled to the gate of the second NMOS FET.

13. The apparatus of claim 12, wherein the pull-down predriver comprises: a third PMOS FET including a gate configured to receive a pull-down gate boosting enable signal; a fourth PMOS FET including a gate configured to receive a first bias voltage; a diode-connected PMOS FET coupled in series between the first voltage rail and the gate of the second NMOS FET; and a fourth PMOS FET including a gate configured to receive a second bias voltage.

14. The apparatus of claim 1, wherein the first predriver comprises a pull-down predriver coupled to the gate of the first NMOS FET.

15. The apparatus of claim 14, wherein the pull-down predriver comprises a third NMOS FET including a drain configured to receive a bias voltage, a gate configured to receive a pull-down gate boosting enable signal, and a drain coupled to the gate of the first NMOS FET.

16. The apparatus of claim 1, wherein the second predriver comprises a pull-down predriver coupled to the gate of the first NMOS FET.

17. The apparatus of claim 16, wherein the pull-down predriver comprises: a third PMOS FET including a gate configured to receive a pull-down gate boosting enable signal; a diode-connected PMOS FET coupled in series with the third PMOS FET between the first voltage rail and the gate of the first NMOS FET; and a fourth PMOS FET coupled between the gate of the first NMOS FET and the second voltage rail, wherein the fourth PMOS FET includes a gate configured to receive a bias voltage.

18. The apparatus of claim 1, further comprising a gate boost control circuit coupled to the first predriver and the second predriver.

19. The apparatus of claim 18, wherein the gate boost control circuit comprises a pull-up gate boost control circuit.

20. The apparatus of claim 19, wherein the pull-up gate boost control circuit comprises: a first multi-domain logic circuit including first and second inputs configured to receive an input signal in a first voltage domain and a complementary input signal in a second voltage domain, respectively, and a first output configured to generate a pull-up gate boosting initiating signal in the second voltage domain; a second multi-domain logic circuit including third and fourth inputs configured to receive a complementary output signal in the first voltage domain and an output signal in the second voltage domain, respectively, and a second output configured to generate a pull-up gate boosting terminating signal in the second voltage domain; and a logic gate including fifth and sixth inputs configured to receive the pull-up gate boosting initiating signal and the pull-up gate terminating signal, respectively, and a third output configured to generate a pull-up gate boosting enable signal in the second voltage domain, wherein the third output is coupled to the first predriver and the second predriver.

21. The apparatus of claim 20, wherein the first multi-domain logic circuit comprises: a third NMOS FET including a gate configured to receive the input signal; and an inverter coupled in series with the third NMOS FET between a third voltage rail and the second voltage rail, wherein the inverter includes an input configured to receive the complementary input signal, and an output configured to produce the pull-up gate boosting initiating signal.

22. The apparatus of claim 20, wherein the second multi-domain logic circuit comprises: a third NMOS FET including a gate configured to receive the complementary output signal; and an inverter coupled in series with the third NMOS FET between a third voltage rail and the second voltage rail, wherein the inverter includes an input configured to receive the input signal, and an output configured to produce the pull-up gate boosting terminating signal.

23. The apparatus of claim 18, wherein the gate boost control circuit comprises a pull-down gate boost control circuit.

24. The apparatus of claim 23, wherein the pull-down gate boost control circuit comprises: a first multi-domain logic circuit including first and second inputs configured to receive an input signal in a first voltage domain and a complementary input signal in a second voltage domain, respectively, and a first output configured to generate a pull-down gate boosting initiating signal in the first voltage domain; a second multi-domain logic circuit including third and fourth inputs configured to receive a complementary output signal in the first voltage domain and an output signal in the second voltage domain, respectively, and a second output configured to generate a pull-down gate boosting terminating signal in the first voltage domain; and a logic gate including fifth and sixth inputs configured to receive the pull-down gate boosting initiating signal and the pull-down gate terminating signal, respectively, and a third output configured to generate a pull-down gate boosting enable signal in the first voltage domain, wherein the third output is coupled to the first predriver and the second predriver.

25. The apparatus of claim 24, wherein the first multi-domain logic circuit comprises: an inverter including an input configured to receive the input signal and an output configured to generate the pull-down gate boosting initiating signal; and a third PMOS FET coupled in series with the inverter between the first voltage rail and a third voltage rail, wherein the third PMOS FET includes a gate configured to receive the complementary input signal.

26. The apparatus of claim 24, wherein the second multi-domain logic circuit comprises: an inverter including an input configured to receive the complementary output signal and an output configured to generate the pull-down gate boosting terminating signal; and a third PMOS FET coupled in series with the inverter between the first voltage rail and a third voltage rail, wherein the third PMOS FET includes a gate configured to receive the output signal.

27. A method, comprising: applying a first control signal to a gate of a first p-channel metal oxide semiconductor field effect transistor (PMOS FET); applying a second control signal to a gate of a second PMOS FET coupled in series with the first PMOS FET between a first voltage rail and an output, wherein the first and second control signals are at high logic voltages when an output signal at the output is at a low logic state, wherein the first and second control signals are at low logic voltages when the output signal is at a high logic state, and wherein the first and second control signals are at a first set of boosted voltages when the output signal is transitioning from the low logic state to the high logic state, respectively; applying a third control signal to a gate of a first n-channel metal oxide semiconductor field effect transistor (NMOS FET); and applying a fourth control signal to a gate of a second NMOS FET coupled in series with the first NMOS FET between the output and a second voltage rail, wherein the third and fourth control signals are at low logic voltages when the output signal is at the high logic state, wherein the third and fourth control signals are at high logic voltages when the output signal is at the low logic state, and wherein the third and fourth control signals are at a second set of boosted voltages when the output signal is transitioning from the high logic state to the low logic state, respectively.

28. The method of claim 27, further comprising: initiating the first and second sets of boosted voltages based on an input signal; and terminating the first and second sets of boosted voltages based on the output signal.

29. An apparatus, comprising: means for applying a first control signal to a gate of a first p-channel metal oxide semiconductor field effect transistor (PMOS FET); means for applying a second control signal to a gate of a second PMOS FET coupled in series with the first PMOS FET between a first voltage rail and an output, wherein the first and second control signals are at high logic voltages when an output signal at the output is at a low logic state, wherein the first and second control signals are at low logic voltages when the output signal is at a high logic state, and wherein the first and second control signals are at a first set of boosted voltages when the output signal is transitioning from the low logic state to the high logic state, respectively; means for applying a third control signal to a gate of a first n-channel metal oxide semiconductor field effect transistor (NMOS FET); and means for applying a fourth control signal to a gate of a second NMOS FET coupled in series with the first NMOS FET between the output and a second voltage rail, wherein the third and fourth control signals are at low logic voltages when the output signal is at the high logic state, wherein the third and fourth control signals are at high logic voltages when the output signal is at the low logic state, and wherein the third and fourth control signals are at a second set of boosted voltages when the output signal is transitioning from the high logic state to the low logic state, respectively.

30. A wireless communication device, comprising: at least one antenna; a transceiver coupled to the at least one antenna; and an integrated circuit (IC) coupled to the transceiver, wherein the IC includes one or more input/output (I/O) circuits, comprising: an output driver, comprising: a first p-channel metal oxide semiconductor field effect transistor (PMOS FET); a second PMOS FET coupled in series with the first PMOS FET between an upper voltage rail and an output; a first n-channel metal oxide semiconductor field effect transistor (NMOS FET); and a second NMOS FET coupled in series with the first NMOS FET between the output and a lower voltage rail; a first predriver coupled to gates of the first and second PMOS FETs and to gates of the first and second NMOS FETs; and a second predriver coupled to the gates of the first and second PMOS FETs and to gates of the first and second NMOS FETs.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A illustrates a schematic diagram of an example input/output (I/O) driver in accordance with an aspect of the disclosure.

(2) FIG. 1B illustrates a timing diagram of example signals relevant to the operation of the I/O driver of FIG. 1A in accordance with another aspect of the disclosure.

(3) FIG. 2A illustrates a block/schematic diagram of an example input/output (I/O) circuit in accordance with another aspect of the disclosure.

(4) FIG. 2B illustrates a timing diagram of example signals relevant to the operation of the I/O circuit of FIG. 2A in accordance with another aspect of the disclosure.

(5) FIG. 3A illustrates a schematic diagram of another example input/output (I/O) circuit in accordance with another aspect of the disclosure.

(6) FIG. 3B illustrates a timing diagram of example signals relevant to the operation of the I/O circuit of FIG. 3A in accordance with another aspect of the disclosure.

(7) FIG. 4 illustrates a block diagram of an example pull-down gate boost control circuit in accordance with another aspect of the disclosure.

(8) FIG. 5 illustrates a schematic diagram of an example multi-domain logic circuit of the pull-down gate boosting control circuit of FIG. 4 in accordance with another aspect of the disclosure.

(9) FIG. 6 illustrates a block diagram of an example pull-up gate boost control circuit in accordance with another aspect of the disclosure.

(10) FIG. 7 illustrates a schematic diagram of an example multi-domain logic circuit of the pull-up gate boost control circuit of FIG. 6 in accordance with another aspect of the disclosure.

(11) FIG. 8 illustrates a schematic diagram of an example first pull-up predriver in accordance with another aspect of the disclosure.

(12) FIG. 9 illustrates a schematic diagram of an example second pull-up predriver in accordance with another aspect of the disclosure.

(13) FIG. 10 illustrates a schematic diagram of an example first pull-down predriver in accordance with another aspect of the disclosure.

(14) FIG. 11 illustrates a schematic diagram of an example second pull-down predriver in accordance with another aspect of the disclosure.

(15) FIG. 12 illustrates a flow diagram of an example method of voltage level shifting an input signal to generate an output signal in accordance with another aspect of the disclosure.

(16) FIG. 13 illustrates a block diagram of an example wireless communication device in accordance with another aspect of the disclosure.

DETAILED DESCRIPTION

(17) The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

(18) FIG. 1A illustrates a schematic diagram of an example input/output (I/O) driver 100 in accordance with an aspect of the disclosure. The I/O driver 100 is configured to receive an input signal V.sub.IN from, for example, a core circuit of an integrated circuit (IC) or system on chip (SOC). The input signal V.sub.IN may swing between a high logic voltage (e.g., 1.1V) and a low logic voltage (e.g., 0.5V) according to a first or core voltage domain.

(19) In response to the high and low logic voltages of the input signal V.sub.IN, the I/O driver 100 generates an output signal V.sub.OUT at an output (e.g., an I/O pad, represented as an X inside a square) that swings between a high logic voltage (e.g., 1.8V) and a low logic voltage (e.g., 0V) according to a second or PX voltage domain, respectively. As discussed in more detail below, the high and low logic voltages of the PX voltage domain may swing substantially between supply voltage VDDPX (applied to a first voltage rail) and supply voltage VSSX (applied to a second voltage rail). The I/O driver 100 provides the output signal V.sub.OUT to a load coupled between the output and the second voltage rail VSSX. The load may have a capacitance C.sub.LOAD. As used herein, a voltage rail and the supply voltage provided to the voltage rail may be referred to by the same label for ease of description. Similarly, a node and a voltage at the node may be referred to by the same label for ease of description.

(20) In this example, the I/O driver 100 includes a pull-up circuit situated between the first voltage rail VDDPX and the output V.sub.OUT. The pull-up circuit is configured to couple the first voltage rail VDDPX to the output V.sub.OUT to cause the output signal V.sub.OUT to transition to and settle at a high logic voltage, such as substantially the supply voltage VDDPX at the first rail voltage (e.g., 1.8V). The pull-up circuit is also configured to isolate or decouple the first voltage rail VDDPX from the output V.sub.OUT to allow the output signal V.sub.OUT to transition to and settle at a low logic voltage, such as substantially VSSX at the second rail voltage (e.g., 0V or ground). In this example, the pull-up circuit includes a pair of p-channel metal oxide semiconductor (PMOS) field effect transistors (FETs) (hereinafter “PMOS FETs”) M.sub.11 and M.sub.12, and a resistor R.sub.P. The PMOS FET M.sub.11 is responsive to a control signal V.sub.PCTL_HV for turning on and off the PMOS FET M.sub.11 in order to couple and isolate the output V.sub.OUT to and from the first rail voltage VDDPX, respectively.

(21) The PMOS FET M.sub.12 of the pull-up circuit may be biased with a substantially constant gate voltage V.sub.PBIAS, which may be set to VDDPX/2 (e.g., 0.9V). Configured as such, the PMOS FET M.sub.12 turns on and off responsive to the turning on and off of the PMOS FET M.sub.11, respectively. For instance, when the control signal V.sub.PCTL_HV is substantially at a low logic voltage, such as VDDPX/2 (e.g., 0.9V), the PMOS FET M.sub.11 turns on because its gate-to-source voltage (V.sub.GS) (e.g., 1.8V−0.9V=0.9V) is greater than its threshold voltage V.sub.T (e.g., 0.4V). The turning on of the PMOS FET M.sub.11 causes substantially VDDPX to be applied to the source of the PMOS FET M.sub.12. Accordingly, the PMOS FET M.sub.12 turns on because its V.sub.GS (e.g., 1.8V−0.9V=0.9V) is greater than its threshold voltage V.sub.T (e.g., 0.4V). Both PMOS FETs M.sub.11 and M.sub.12 being turned on causes VDDPX to be applied substantially to the output V.sub.OUT of the I/O driver 100 by way of resistor R.sub.P, which causes the output signal V.sub.OUT to transition to and settle substantially at VDDPX (e.g., ˜1.8V). The resistor R.sub.P limits the current flow through the PMOS FETs M.sub.11 and M.sub.12 to prevent overstressing or damaging of these devices.

(22) Similarly, when the control signal V.sub.PCTL_HV is at a high logic voltage, such as substantially at VDDPX (e.g., 1.8V), the PMOS FET M.sub.11 turns off because its V.sub.GS (e.g., 1.8V−1.8V=0V) is less than its threshold voltage V.sub.T (e.g., 0.4V). The PMOS FET M.sub.11 being turned off isolates VDDPX from the source of PMOS FET M.sub.12, which causes the voltage at the source of PMOS FET M.sub.12 to decrease and settle at a voltage V.sub.PI less than a threshold voltage above V.sub.PBIAS (e.g., <1.3V). Thus, the PMOS FET M.sub.12 turns off because its V.sub.GS does not exceed its threshold voltage V.sub.T. With both PMOS FETS M.sub.11 and M.sub.12 turned off, the output V.sub.OUT is substantially isolated from VDDPX, allowing a pull-down circuit of the I/O driver 100 to pull-down the output signal V.sub.OUT so that it transitions to and settles at substantially VSSX (e.g., 0V).

(23) When the output signal V.sub.OUT is substantially at VSSX, the PMOS FET M.sub.12 prevents the entire voltage difference between VDDPX and VSSX from being applied across PMOS FET M.sub.11, thereby preventing overstressing of or damage to device M.sub.11. Instead, the voltage difference (VDDPX−VSSX) is split, maybe albeit unequally, across both PMOS FETs M.sub.11 and M.sub.12. Thus, the PMOS FET M.sub.12 acts as a buffering device for PMOS FET M.sub.11.

(24) The I/O driver 100 further includes a pull-down circuit situated between the output V.sub.OUT and the second voltage rail VSSX. The pull-down circuit is configured to couple the output V.sub.OUT to the second voltage rail VSSX to cause the output signal V.sub.OUT to transition to and settle at a low logic voltage, such as substantially the steady-state second rail voltage VSSX (e.g., 0V or ground). The pull-down circuit is also configured to isolate or decouple the output V.sub.OUT from the second voltage rail VSSX to allow the output signal V.sub.OUT to transition to and settle at a high logic voltage, such as substantially the first rail voltage VDDPX. In this example, the pull-down circuit includes a pair of n-channel MOS FETs (hereinafter “NMOS FETs”) M.sub.13 and M.sub.14, and resistor R.sub.N. The NMOS M.sub.14 is responsive to a control signal V.sub.NCTL_LV for turning on and off the NMOS FET M.sub.14 in order to couple and isolate the output V.sub.OUT to and from the second voltage rail VSSX, respectively.

(25) The NMOS FET M.sub.13 of the pull-down circuit may be biased with a substantially constant gate voltage V.sub.NBIAS, which may be set to VDDPX/2 (e.g., 0.9V). Configured as such, the NMOS FET M.sub.13 turns on and off responsive to the turning on and off of NMOS FET M.sub.14, respectively. For instance, when the control signal V.sub.NCTL_LV is at a high logic voltage, such as VDDPX/2 (e.g., 0.9V), the NMOS FET M.sub.14 is turned on because its V.sub.GS (e.g., 0.9V-0V=0.9V) is greater than its threshold voltage V.sub.T (e.g., 0.4V). The turning on of NMOS FET M.sub.14 causes VSSX to be substantially applied to the source of NMOS FET M.sub.13. In response, NMOS FET M.sub.11 turns on because its V.sub.GS (e.g., 0.9V−0V=0.9V) is greater than its threshold voltage V.sub.T (e.g., 0.4V). Both NMOS FETs M.sub.13 and M.sub.14 being turned on causes VSSX to be applied substantially to the output V.sub.OUT by way of resistor R.sub.N, which results in the output signal V.sub.OUT to transition to and settle substantially at the second rail voltage VSSX (e.g., 0V). The resistor R.sub.N limits the current flow through the devices M.sub.11 and M.sub.14 to prevent overstressing of or damage to the devices.

(26) Similarly, when control signal V.sub.NCTL_LV is at a low logic voltage, such as VSSX (e.g., 0V), the NMOS FET M.sub.4 is turned off because its V.sub.GS(e.g., 0V−0V=0V) is less than its threshold voltage V.sub.T (e.g., 0.4V). The device NMOS FET M.sub.14 being turned off isolates VSSX from the source of NMOS FET M.sub.13, which causes the source of NMOS FET M.sub.3 to decrease and settle to less than a threshold voltage below V.sub.NBIAS (e.g., >0.7V). Accordingly, NMOS FET M.sub.13 is turned off because its V.sub.GS does not exceed its threshold voltage V.sub.T. Both NMOS FETs M.sub.13 and M.sub.14 being turned off decouple the output V.sub.OUT from the second voltage rail VSSX; thereby allowing the pull-up circuit to cause the output signal V.sub.OUT to transition to and settle at the high logic voltage, such as substantially at the first rail voltage VDDPX (e.g., 1.8V).

(27) When the output signal V.sub.OUT is at VDDPX, the NMOS FET M.sub.13 prevents the entire voltage difference between VDDPX and VSSX from being applied across NMOS FET M.sub.14, thereby preventing overstressing of or damage to device M.sub.14. Instead, the voltage difference (VDDPX−VSSX) is split, maybe albeit unequally, across both NMOS FETs M.sub.13 and M.sub.14. Thus, NMOS FET M.sub.13 acts as a buffering device for NMOS FET M.sub.14.

(28) Note that the respective logic voltages pertaining to the output signal V.sub.OUT, the control signal V.sub.PCTL_HV, and the control signal V.sub.NCTL_HV are in different voltage domains. For instance, the high and low logic voltages pertaining to the V.sub.OUT voltage domain vary between substantially VDDPX (e.g., 1.8V) and VSSX (e.g., 0V) (which may be referred to herein as the PX voltage domain). The high and low logic voltages pertaining to the V.sub.PCTL_HV voltage domain vary between substantially VDDPX (e.g., 1.8V) and VSSIX (e.g., 0.9V) (which may be referred to herein as the HV voltage domain). And, the high and low logic voltages pertaining to the V.sub.NCTL_LV voltage domain vary between substantially VDDIX (e.g., 0.9V) and VSSX (e.g., 0V) (which may be referred to herein as the LV voltage domain).

(29) FIG. 1B illustrates a timing diagram of example signals relevant to the operation of the example I/O driver 100 in accordance with another aspect of the disclosure. The horizontal axis of the timing diagram represents time, and is divided into four states or time intervals: (1) when the output signal V.sub.OUT is at a steady-state high logic voltage VDDPX, which is indicated in the left-most and right-most columns of the timing diagram; (2) when the output signal V.sub.OUT is transitioning from the high logic voltage VDDPX to a low logic voltage VSSX, which is indicated in the second column from the left; (3) when the output signal V.sub.OUT is at a steady-state low logic voltage VSSX, which is indicated in the third column from the left; and (4) when the output signal V.sub.OUT is transitioning from the low logic voltage VSSX to the high logic voltage VDDPX, which is indicated in the fourth column from the left.

(30) The vertical axis of the timing diagram represents the various signals of the I/O driver 100. For instance, from top to bottom, the signals are: (1) the control signal V.sub.PCTL_HV for PMOS FET M.sub.11; (2) the gate bias voltage V.sub.BIAS for PMOS FET M.sub.12; (3) the voltage V.sub.PI at the source of PMOS FET M.sub.12; (4) the output signal V.sub.OUT of the I/O driver 100; (5) the gate bias voltage V.sub.NBIAS for NMOS FET M.sub.13; (6) the voltage V.sub.NI at the source of NMOS FET M.sub.13; and (7) the control signal V.sub.NCTL_LV for NMOS FET M.sub.14.

(31) In operation, during the state or time interval where the output signal V.sub.OUT is at a steady-state high logic voltage VDDPX as indicated in the left-most column of the timing diagram, the control signal V.sub.PCTL_HV is at a low logic voltage VSSIX (e.g., 0.9V) and the gate bias voltage V.sub.PBIAS is at a constant VDDPX/2 voltage (e.g., 0.9V) in order to turn on both PMOS FETs M.sub.11 and M.sub.12, respectively. The turning on of both PMOS FETs M.sub.11 and M.sub.12 results in substantially applying VDDPX to the output V.sub.OUT, thereby maintaining the output signal V.sub.OUT steady at the high logic voltage VDDPX (e.g., 1.8V). Also, the voltage V.sub.PI at the source of PMOS FET M.sub.12 is substantially at VDDPX (e.g., 1.8V). Further, during this state or time interval, the control signal V.sub.NCTL_LV is at a low logic voltage VSSX (e.g., 0V) to turn off NMOS FET M.sub.14. The gate bias voltage V.sub.NBIAS for NMOS FET M.sub.13 is at the constant VDDPX/2 voltage (e.g., 0.9V). With NMOS FET M.sub.14 being turned off, the voltage V.sub.NI at the source of NMOS FET M.sub.13 settles to less than a threshold voltage below V.sub.NBIAS, for example, to >V.sub.NBIAS-V.sub.T (e.g., >0.5V). Thus, both NMOS FETs M.sub.13 and M.sub.14 are turned off to isolate or decouple the output V.sub.OUT from VSSX.

(32) During the state or time interval where the output signal V.sub.OUT is transitioning from the high logic voltage VDDPX to the low logic voltage VSSX as indicated in the second column from the left, the control signal V.sub.PCTL_HV for PMOS FET M.sub.11 is raised to the high logic voltage VDDPX (e.g., 1.8V) to turn off PMOS FET M.sub.11. The gate bias voltage V.sub.BIAS of PMOS FET M.sub.12 remains at the constant VDDPX/2 (e.g., 0.9V). Thus, the voltage V.sub.PI at the source of PMOS FET M.sub.12 decreases and settles to less than a threshold voltage above V.sub.PBIAS, for example, to <V.sub.PBIAS+V.sub.T (e.g., <1.3V). Thus, both PMOS FETs M.sub.11 and M.sub.12 are turned off to isolate or decouple the output V.sub.OUT from VDDPX. Also, during this state or time interval, the control signal V.sub.NCTL_LV is raised to a high logic voltage VDDIX (e.g., 0.9V) to turn on NMOS FET M.sub.14. The turning on of NMOS FET M.sub.14 causes the voltage V.sub.NI at the source of NMOS FET M.sub.13 to decrease to substantially VSSX (e.g., 0V). The gate bias voltage V.sub.NBIAS of NMOS FET M.sub.13 remains at VDDPX/2 (e.g., 0.9V). Thus, the gate-to-source voltage V.sub.GS of NMOS FET M.sub.13 is greater than its threshold voltage V.sub.T, thereby causing NMOS FET M.sub.13 to turn on. Both NMOS FETs M.sub.13 and M.sub.14 being turned on causes the output signal V.sub.OUT to transition to and settle substantially at VSSX (e.g., 0V).

(33) Once the voltages have transitioned, they will remain substantially constant during the state or time interval where the output signal V.sub.OUT is at substantially VSSX, as indicated in the third column from the left. That is, the control signal V.sub.PCTL_HV is at the high logic voltage V.sub.DDPX and the bias voltage V.sub.PBIAS is at VDDPX/2 to keep devices M.sub.11 and M.sub.12 turned off to isolate or decouple the output V.sub.OUT from the first voltage rail (V.sub.DDPX). The voltage V.sub.PI at the source of PMOS FET M.sub.12 remains substantially constant less than a threshold voltage V.sub.T above V.sub.PBIAS (e.g., <1.3V). The control signal V.sub.NCTL_LV is at the high logic voltage VDDIX and the bias voltage V.sub.NBIAS is at the constant VDDPX/2 to keep both devices M.sub.14 and M.sub.13 turned on to cause the output signal V.sub.OUT to be at the low logic voltage VSSX. Both devices M.sub.13 and M.sub.14 being turned on causes the voltage V.sub.NI at the source of NMOS FET M.sub.13 to be at VSSX (e.g., 0V).

(34) During the state or time interval where the output signal V.sub.OUT is transitioning from the low logic voltage VSSX to the high logic voltage VDDPX as indicated in the fourth column from the left, the control signal V.sub.PCTL_HV for PMOS FET M.sub.11 is lowered to the low logic voltage VSSIX (e.g., 0.9V) to turn on PMOS FET MW. The gate bias voltage V.sub.PBIAS for PMOS FET M.sub.12 remains at the constant VDDPX/2 (e.g., 0.9V). Thus, both PMOS FETs M.sub.11 and M.sub.12 turn on. Accordingly, the voltage V.sub.PI at the source of PMOS FET M.sub.12 as well as the output signal V.sub.OUT transition to the high logic voltage VDDPX (e.g., 1.8V). Also, during this state or time interval, the control signal V.sub.NCTL_LV is lowered to the low logic voltage VSSX (e.g., 0V) to turn off NMOS FET M.sub.14. The gate bias voltage V.sub.NBIAS of NMOS FET M.sub.13 remains at the constant VDDPX/2 (e.g., 0.9V). Accordingly, the voltage V.sub.NI at the source of NMOS FET M.sub.13 increases to more than a threshold voltage below V.sub.NBIAS, to, for example, >0.5V. Thus, the gate-to-source voltage V.sub.GS of NMOS FET M.sub.13 does not exceed its threshold voltage V.sub.T, thereby causing NMOS FET M.sub.13 to turn off. Both NMOS FETs M.sub.13 and M.sub.14 being turned off isolate or decouple the output signal V.sub.OUT from VSSX (e.g., 0V). Once the voltages have transitioned, they will remain substantially constant during the state or time interval where the output signal V.sub.OUT is at the high logic voltage V.sub.DDPX, as indicated in the right-most column.

(35) There are several issues with the I/O driver 100. For instance, if the devices M.sub.11, M.sub.12, M.sub.14, and M.sub.13 are manufactured in accordance with a certain technology node (e.g., to use the same technology node for all other non-I/O devices (e.g., core devices) in an IC or SOC), the maximum reliability voltage across any terminals (V.sub.GS, V.sub.GD, and V.sub.DS) of these devices may be about 1.3V. If the devices are exposed to voltages above the reliable limit of 1.3V and for an extended period of time (e.g., a few picoseconds (ps) or more), recoverable or unrecoverable damage to these devices may result. Such damage may be due to negative bias temperature instability (NBTI) or hot carrier injection (HCI). As a consequence, the performance and functionality of the devices may degrade or completely fail.

(36) With reference again to FIG. 1B, when the output signal V.sub.OUT is at the high logic voltage VDDPX as indicated in the left-most and right-most columns of the timing diagram, the voltage at the drain of NMOS FET M.sub.13 is substantially at VDDPX (e.g., 1.8V) and the voltage at the source of NMOS FET M.sub.13 is at 0.5V. Thus, the voltage difference (e.g., VDs) across the drain and source of NMOS FET M.sub.13 is 1.3V. As previously discussed, this voltage differential of 1.3V across NMOS FET M.sub.13 is close to exceeding the reliability limit of 1.3V if this device is manufactured in accordance with a particular implementation.

(37) Further, during the state or time interval where the output signal V.sub.OUT is transitioning from VDDPX to VSSX as indicated in the second column from the left, the voltage V.sub.NI at the source of NMOS FET M.sub.13 decreases from 0.5V to 0V at a rate much faster than the output signal V.sub.OUT decreases from 1.8V to 0V, due to generally a larger capacitive load C.sub.LOAD present at the output V.sub.OUT of the I/O driver 100. As a result, the voltage difference V.sub.DS across the drain and source of NMOS FET M.sub.13 may increase up to about 1.5V during the transition of the output signal V.sub.OUT from VDDPX to VSSX, again exceeding the reliability limit of 1.3V if the device is manufactured in accordance with a particular implementation.

(38) Similarly, when the output signal V.sub.OUT is at the low logic voltage VSSX as indicated in the third column from the left, the voltage at the drain of the PMOS FET M.sub.12 is substantially at VSSX (e.g., 0V) and the voltage at the source of the PMOS FET M.sub.12 is at 1.3V. Thus, the voltage difference (e.g., V.sub.GS) across the drain and source of PMOS FET M.sub.12 is 1.3V. As previously discussed, this voltage differential of 1.3V across PMOS FET M.sub.12 is close to exceeding the reliability limit of 1.3V if this device is manufactured in accordance with a particular implementation.

(39) Also, similarly, during the state or time interval where the output signal V.sub.OUT is transitioning from VSSX to VDDPX as indicated in the fourth column from the left, the voltage V.sub.PI at the source of PMOS FET M.sub.12 increases from 1.3V to 1.8V at a rate much faster than the output signal V.sub.OUT increases from 0V to 1.8V due to generally the larger capacitive load C.sub.LOAD present at the output V.sub.OUT of the I/O driver 100. As a result, the voltage differential V.sub.GS across the drain and source of PMOS FET M.sub.12 increases up to about 1.5V during the transition of the output signal V.sub.OUT from VSSX to VDDPX, again exceeding the reliability limit of 1.3V if the device is manufactured in accordance with a particular implementation. The resistors R.sub.P and R.sub.N are provided to absorb some of the overshoot of the V.sub.DS of PMOS FET M.sub.12 and NMOS FET M.sub.13. However, resistors R.sub.P and R.sub.N may be undesirable due to occupying significant IC footprint and producing unwanted electromagnetic (EM) energy.

(40) FIG. 2A illustrates a schematic diagram of an input/output (I/O) circuit 200 in accordance with another aspect of the disclosure. One of the differences between I/O circuit 200 and I/O driver 100 is that the gate voltages applied to the PMOS FET M.sub.22 and NMOS FET M.sub.23 are not constant, but change or are boosted during transitions of the output signal V.sub.OUT from high-to-low logic voltages and from low-to-high logic voltages, respectively. This is done to reduce the maximum voltages across the buffer devices M.sub.22 and M.sub.23 to below their reliability limits during transitions of the output signal V.sub.OUT, respectively. Additionally, the I/O circuit 200 applies bias voltages to the sources of M.sub.22 and M.sub.23 to prevent over-voltage of such devices when the output signal V.sub.OUT is at steady-state high and low logic voltages, respectively.

(41) As an overview, the I/O circuit 200 is configured to receive an input voltage V.sub.IN from, for example, a core circuit of an IC or SOC. The input voltage V.sub.IN may swing between high and low logic voltages according to a first (e.g., core) voltage domain. In response to the high and low voltages of the input voltage V.sub.IN, the I/O circuit 200 generates an output signal V.sub.OUT that swings between high and low logic voltages according to a second (e.g., PX) voltage domain, respectively. The high and low logic voltages of the second voltage domain may coincide substantially with VDDPX and VSSX. The I/O circuit 200 provides the output signal V.sub.OUT to a load having a capacitance C.sub.LOAD.

(42) More specifically, the I/O circuit 200 includes an output driver including a pull-up circuit including PMOS FETs M.sub.21 and M.sub.22 coupled in series between a first voltage rail VDDPX and the output V.sub.OUT of the I/O circuit 200. Similarly, the output driver includes a pull-down circuit including NMOS FETs M.sub.23 and M.sub.24 coupled in series between the output V.sub.OUT and a second voltage rail VSSX.

(43) The I/O circuit 200 further includes a first PMOS predriver 210 configured to generate the control signal V.sub.PCTL_HV in response to an input signal V.sub.IN. As previously discussed, the HV voltage domain for V.sub.PCTL_HV varies between a low logic voltage VSSIX (e.g., VDDPX/2) and a high logic voltage VDDPX. The I/O circuit 200 further includes a second PMOS predriver 211 configured to generate a control signal V.sub.LV in response to the input signal V.sub.IN. The LV voltage domain for V.sub.LV varies between a low logic voltage VSSX and a high logic voltage VDDIX. Thus, when the input voltage V.sub.IN is low, V.sub.PCTL_HV is at VDDPX and V.sub.LV is at VDDIX. When the input voltage V.sub.IN is high, V.sub.PCTL_HV is at VSSIX and V.sub.LV is at VSSX.

(44) Similarly, the I/O circuit 200 further includes a first NMOS predriver 220 configured to generate the control signal V.sub.NCTL_LV in response to the input signal V.sub.IN. The LV voltage domain for N.sub.NCTL_LV varies between a low logic voltage VSSX and a high logic voltage VDDIX. The I/O circuit 200 further includes a second NMOS predriver 221 configured to generate a control signal V.sub.HV in response to the input signal V.sub.IN. The HV voltage domain for V.sub.HV varies between a low logic voltage VSSIX and a high logic voltage VDDPX. Thus, when the input voltage V.sub.IN is low, V.sub.NCTL_LV is at VDDIX and V.sub.HV is at VDDPX. When the input voltage V.sub.IN is high, V.sub.NCTL_LV is at VSSX and V.sub.NCTL_HV is at VSSIX.

(45) The control signal V.sub.PCTL_HV generated by the first PMOS predriver 210 is applied to the gate of PMOS FET M.sub.21 and to a V.sub.PI voltage generator 214. The control signal V.sub.LV generated by the second PMOS predriver 211 is applied to a V.sub.PCTL_LV predriver 212. Similarly, the control signal V.sub.NCTL_LV generated by the first NMOS predriver 220 is applied to the gate of NMOS FET M.sub.24 and to a V.sub.NI voltage generator 224. The control signal V.sub.HV generated by the second NMOS predriver 221 is applied to a V.sub.NCTL_HV predriver 222. The V.sub.PCTL_LV predriver 212 is configured to generate a control signal V.sub.PCTL_LV based on V.sub.LV and V.sub.OUT. The control signal V.sub.PCTL_LV is applied to the gate of PMOS FET M.sub.22. Similarly, the V.sub.NCTL_HV predriver 222 is configured to generate a control signal V.sub.NCTL_HV based on V.sub.HV and V.sub.OUT. The control signal V.sub.NCTL_HV is applied to the gate of NMOS FET M.sub.2.

(46) The V.sub.PI voltage generator 214 is configured to generate a voltage V.sub.PI based on V.sub.PCTL_HV and V.sub.OUT. The voltage V.sub.PI is applied to the source of PMOS FET M.sub.22. The voltage V.sub.PI protects the PMOS FET M.sub.22 from over-voltage when the output signal V.sub.OUT is at a steady-state low logic voltage VSSX. For example, when the output signal V.sub.OUT is at the steady-state low logic voltage VSSX (e.g., 0V), the voltage V.sub.PI is substantially at VDDIX (e.g., 0.9V). Due to the voltage V.sub.PI, the drain-to-source voltage V.sub.DS of PMOS FET M.sub.22 is, for example, 0.9V, below a reliability maximum voltage of, for example, 1.3V of the device.

(47) Similarly, the V.sub.NI voltage generator 224 is configured to generate a voltage V.sub.NI based on V.sub.NCTL_LV and V.sub.OUT. The voltage V.sub.NI is applied to the source of NMOS FET M.sub.2. The voltage V.sub.NI protects the NMOS FET M.sub.23 from over-voltage when the output signal V.sub.OUT is at a steady-state high logic voltage VDDPX. For example, when the output signal V.sub.OUT is at the steady-state high logic voltage VDDPX (e.g., 1.8V), the voltage V.sub.NI is substantially at VDDIX (e.g., 0.9V). Due to the voltage V.sub.NI, the drain-to-source voltage V.sub.DS of NMOS FET M.sub.23 is, for example, 0.9V, below a reliability maximum voltage of, for example, 1.3V for the device.

(48) FIG. 2B illustrates a timing diagram associated with an example operation of the I/O circuit 200 in accordance with another aspect of the disclosure. For explanation purposes, VDDPX is 1.8V, VDDIX/VSSIX is 0.9V, and VSSX is 0V. Also, for explanation purposes, the maximum reliability voltage for V.sub.DS, V.sub.GS, and V.sub.DG of devices M.sub.21, M.sub.22, M.sub.22, and M.sub.21 is 1.3V, as previously discussed. It shall be understood that such voltages and maximum reliability voltage may be different in various implementations based on the type of devices and applications used for the I/O circuit 200.

(49) Similar to the graph of FIG. 1B, the horizontal axis of the timing diagram represents time, and is divided into four states or time intervals: (1) when the output signal V.sub.OUT is at a steady-state high logic voltage VDDPX, which is indicated in the left-most and right-most columns of the timing diagram; (2) when the output signal V.sub.OUT is transitioning from the high logic voltage VDDPX to a low logic voltage VSSX, which is indicated in the second column from the left; (3) when the output signal V.sub.OUT is at a steady-state low logic voltage VSSX, which is indicated in the third column from the left; and (4) when the output signal V.sub.OUT is transitioning from the low logic voltage VSSX to the high logic voltage VDDPX, which is indicated in the fourth column from the left.

(50) The vertical axis of the timing diagram represents the various signals of the I/O circuit 200. For instance, from top to bottom, the signals are: (1) the control signal V.sub.PCTL_HV for PMOS FET M.sub.21; (2) the gate bias voltage V.sub.PCTL_LV for PMOS FET M.sub.22; (3) the output signal V.sub.OUT; (4) the gate bias voltage V.sub.NCTL_HV for NMOS FET M.sub.23; and (5) the control signal V.sub.NCTL_LV for NMOS FET M.sub.24.

(51) When the output signal V.sub.OUT is at a high logic voltage VDDPX (e.g., 1.8V) as indicated by the left-most and right-most columns, the control signal V.sub.PCTL_HV is at a low logic voltage VSSIX (e.g., 0.9V) to turn on PMOS FET M.sub.21, the voltage V.sub.PI at the source of PMOS FET M.sub.22 is at VDDPX (e.g., 1.8V), and the control signal V.sub.PCTL_LV is at a non-boosted voltage (e.g., 0.9V), which causes PMOS FET M.sub.22 to turn on in response to PMOS FET M.sub.2 turning on. Accordingly, the output signal V.sub.OUT is at a high logic voltage VDDPX (e.g., 1.8V) due to the first voltage rail VDDPX being coupled to the output V.sub.OUT via the turned-on PMOS FETs M.sub.21 and M.sub.22. Also, when the output signal V.sub.OUT is at the high logic voltage VDDPX (e.g., 1.8V), the control signal V.sub.NCTL_LV is at a low logic voltage VSSX (e.g., 0V) to turn off NMOS FET M.sub.24, the voltage V.sub.NI is at VDDIX (e.g., 0.9V) to maintain the VDS of NMOS FET M.sub.23 below its reliability limit, and the control signal V.sub.NCTL_HV is at a non-boosted voltage VSSIX (e.g., 0.9V), which turns off NMOS FET M.sub.23. Accordingly, the output V.sub.OUT is decoupled from the second voltage rail VSSX due to the turned-off NMOS FETs M.sub.23 and M.sub.24.

(52) To transition the output signal V.sub.OUT from the high logic voltage VDDPX (1.8V) to the low logic voltage VSSX (0V) as indicated in the second column from the left, the control signal V.sub.NCTL_LV is changed from the low logic voltage VSSX (e.g., 0V) to the high logic voltage VDDIX (e.g., 0.9V) to turn on NMOS FET M.sub.24. Simultaneous with V.sub.NCTL_LV changing from low to high, the bias voltage V.sub.NCTL_HV is boosted from a non-boosted voltage (e.g., ˜VSSIX (e.g., 0.9V)) to boosted voltage (e.g., VSSIX+˜0.5V=˜1.4V). The boost voltage configures the respective turn-on resistances of NMOS FETs M.sub.23 and M.sub.24 to be more equalized (e.g., substantially the same) when the output signal V.sub.OUT initially transitions from high-to-low. In this example, this produces a 1.8V voltage drop between V.sub.OUT and VSSX to be equally divided among NMOS FETs M.sub.23 and M.sub.24; thus, causing the devices to each see a voltage drop of substantially 0.9V, which is below the 1.3V reliability limit.

(53) When the output signal V.sub.OUT has decreased to a certain voltage level, the control signal V.sub.NCTL_HV is brought back to the non-boosted voltage (e.g., ˜VSSIX (0.9V)). The time interval in which the V.sub.NCTL_HV is at the boosted voltage (e.g., ˜1.4V) should be controlled to prevent over-voltage of NMOS FET M.sub.23. For instance, if the time interval is too short, then NMOS FET M.sub.23 may be subjected to over-voltage due to its V.sub.DS being above the reliability limit. If, on the other hand, the time interval is too long, then the device M.sub.23 may be subjected to over-voltage due to its gate-to-source voltage (V.sub.GS) and/or gate-to-drain voltage (V.sub.GD) being above the reliability limit.

(54) The time interval depends on the rate at which the output signal V.sub.OUT decreases from VDDPX to VSSX. Such rate depends on the capacitive load C.sub.LOAD coupled to the output of the I/O circuit 200. If the capacitance C.sub.LOAD of the load is relatively small, then the time interval should be relatively short because the rate at which output signal V.sub.OUT is decreasing is relatively high. If the capacitance C.sub.LOAD of the load is relatively large, then the time interval should be relatively long because the rate at which output signal V.sub.OUT is decreasing is relatively low. Accordingly, the V.sub.NCTL_HV predriver 222 generates the boosted V.sub.NCTL_HV voltage based on the rate at which output signal V.sub.OUT transitions from high-to-low.

(55) Further, to facilitate the transition of the output signal V.sub.OUT from the high logic voltage VDDPX (e.g., 1.8V) to the low logic voltage VSSX (0V), the control signal V.sub.PCTL_HV is changed from the low logic voltage VSSIX (e.g., 0.9V) to the high logic voltage VDDPX (e.g., 1.8V) to turn off PMOS FET M.sub.21. In response to the output signal V.sub.OUT decreasing to a certain voltage level, the V.sub.PI voltage generator 214 generates the voltage V.sub.PI substantially at VDDPX (e.g., 0.9V). As the control signal V.sub.PCTL_LV applied to gate of PMOS FET M.sub.22 is maintained constant at VDDIX (e.g., 0.9V) during the transition of the output signal V.sub.OUT from high-to-low, PMOS FET M.sub.22 turns off because its V.sub.GS is substantially at 0V. Accordingly, during the transition of the output signal V.sub.OUT from high-to-low, the pull-up circuit decouples the output from the first voltage rail VDDPX due to the turned off PMOS FETs M.sub.21 and M.sub.22.

(56) When the output signal V.sub.OUT is at a steady-state low logic voltage VSSX (0V) as indicated in the third column from the left, the control signal V.sub.NCTL_LV is at the high logic voltage VDDIX (e.g., 0.9V) to maintain NMOS FET M.sub.24 turned on, the control signal V.sub.NCTL_HV is at the non-boosted voltage VDDIX (e.g., 0.9V), which maintains NMOS FET M.sub.23 turned on. Thus, output signal V.sub.OUT receives VSSX (0V) from the second voltage rail via the turned-on NMOS FETs M.sub.23 and M.sub.24. It follows that the voltage V.sub.NI is also at VSSX (0V). Also, when the output signal V.sub.OUT is at the steady-state low logic voltage VSSX (0V), the control signal V.sub.PCTL_HV is at a high logic voltage VDDPX (e.g., 1.8V) to maintain PMOS FET M.sub.21 turned off, the voltage V.sub.PI is at VSSIX (e.g., 0.9V) to protect PMOS FET M.sub.22 from over-voltage as discussed, and the control signal V.sub.PCTL_HV is at the non-boosted voltage VDDIX (e.g., 0.9V), which maintains PMOS FET M.sub.2 turned off. Thus, the output of the I/O circuit 200 is decoupled from the first voltage rail VDDPX via the turned-off PMOS FETs M.sub.21 and M.sub.22.

(57) To transition the output signal V.sub.OUT from the low logic voltage VSSX (e.g., 0V) towards the high logic voltage VDDPX (e.g., 1.8V) as indicated in the fourth column from the left, the control signal V.sub.PCTL_HV is changed from the high logic voltage VDDPX (e.g., 1.8V) to the low logic voltage VSSIX (e.g., 0.9V) to turn on PMOS FET M.sub.21. Simultaneous with V.sub.PCTL_HV changing from high to low, the control signal V.sub.PCTL_LV is changed from the non-boosted voltage (e.g., 0.9V) to the boosted voltage (e.g., ˜0.4V). This is done to configure the respective turn-on resistances of PMOS FETs M.sub.21 and M.sub.22 to be more equalized (e.g., substantially the same) when the output signal V.sub.OUT initially transitions from low-to-high. In this example, this causes the 1.8V voltage drop between VDDPX and V.sub.OUT to be divided equally among PMOS FETs M.sub.21 and M.sub.22, thus, causing the devices to each see a voltage drop of substantially 0.9V, which is below the 1.3V reliability limit.

(58) When the output signal V.sub.OUT has increased to a certain voltage level, the control signal V.sub.PCTL_LV is brought back to the non-boosted voltage (e.g., VDDIX (e.g., 0.9V)). The time interval in which the V.sub.PCTL_LV is at the boosted voltage (e.g., ˜0.4V) should be controlled to prevent over-voltage of PMOS FET M.sub.2. For instance, if the time interval is too short, then PMOS FET M.sub.22 may be subjected to over-voltage due to its V.sub.GS being above the reliability limit. If, on the other hand, the time interval is too long, then the device M.sub.22 may be subjected to over-voltage due to its gate-to-source voltage (V.sub.GS) and/or gate-to-drain (V.sub.GD) being above the reliability limit.

(59) The time interval depends on the rate at which the output signal V.sub.OUT increases from VSSX to VDDPX. Such rate depends on the capacitive load C.sub.LOAD coupled to the output of the I/O circuit 200. If the capacitance C.sub.LOAD of the load is relatively small, then the time interval should be relatively short because the rate at which output signal V.sub.OUT is increasing is relatively high. If the capacitance C.sub.LOAD of the load is relatively large, then the time interval should be relatively long because the rate at which output signal V.sub.OUT is increasing is relatively low. Accordingly, the V.sub.PCTL_LV predriver 212 generates the boosted V.sub.PCTL_LV voltage based on the rate at which output signal V.sub.OUT transitions from low-to-high.

(60) Further, to facilitate the transition the output signal V.sub.OUT from the low logic voltage VSSX (e.g., 0V) towards the high logic voltage VDDPX (e.g., 1.8V), the control signal V.sub.NCTL_LV is changed from the high logic voltage VDDIX (e.g., 0.9V) to the low logic voltage VSSX (e.g., 0V) to turn off NMOS FET M.sub.24. In response to the output signal V.sub.OUT increasing to a certain voltage level, the V.sub.NI voltage generator 224 generates the voltage V.sub.NI substantially at VDDIX (e.g., 0.9V). As the control signal V.sub.NCTL_HV applied to gate of NMOS FET M.sub.23 is maintained constant at VSSIX (e.g., 0.9V) during the transition of the output signal V.sub.OUT from low-to-high, NMOS FET M.sub.23 turns off because its V.sub.GS is substantially at 0V. Accordingly, during the transition of the output signal V.sub.OUT from low-to-high, the pull-down circuit decouples the output from the second voltage rail VSSX due to the turned off NMOS FETs M.sub.21 and M.sub.22.

(61) There are several issues with the I/O circuit 200. First, there is just one gate boosting during each transition of the output signal V.sub.OUT. For example, NMOS FET M.sub.23 is the only device boosted during a high-to-low transition of the output signal V.sub.OUT, and PMOS FET M.sub.22 is the only device boosted during a low-to-high transition of the output signal V.sub.OUT. Boosting more than just one FET during a transition would produce faster transitions, thereby allowing the I/O driver to operate much faster.

(62) Secondly, as illustrated in FIG. 2B, the gate boosting in I/O circuit 200 is only about 30 percent (%) of the duration of the transition. Providing a greater percentage boosting interval during each transition would also expedite transitions, again, allowing an I/O driver to operate much faster. An additional drawback of the relatively small boosting duration (e.g., 30%) is that the output impedance changes during each transition. For example, during a boosting interval, the output impedance is significantly less than during the remaining or non-boosting interval of a transition. The change in output impedance during each transition may cause signal integrity (SI) issues in the output signal V.sub.OUT.

(63) Third, the pull-up circuit (e.g., PMOS FETs M.sub.21 and M.sub.22) and the pull-down circuit (e.g., NMOS FETs M.sub.23 and M.sub.24) are driven by different domain signals. For example, the PMOS FETs M.sub.21 and M.sub.22 of the pull-up circuit are driven by control signals V.sub.PCTL_HV and V.sub.PCTL_LV, which are in the HV and LV voltage domains, respectively. Similarly, the NMOS FETs M.sub.23 and M.sub.24 of the pull-down circuit are driven by control signals V.sub.NCTL_HV and V.sub.NCTL_LV, which are in the HV and LV voltage domains, respectively. Since the HV and LV domain signals propagate via different transmission paths, there could be delay mismatch between these signals, which may adversely affect the operation (e.g., produce duty cycle distortion in the output signal V.sub.OUT) and reliability (e.g., subject the FETs to over-voltage stress or damage). As an example, if during a low-to-high transition, the rising edge of the V.sub.PCTL_HV arrives before falling edge of the V.sub.PCTL_LV, PMOS FET M.sub.22 may be stressed or damaged due to over-voltage, or if the rising edge of V.sub.PCTL_HV arrives after the falling edge of the V.sub.PCTL_LV, PMOS FET M.sub.21 may be stressed or damaged due to over-voltage. The same adverse effects apply to NMOS FETs M.sub.23 and M.sub.24 during a high-to-low transition.

(64) FIG. 3A illustrates a schematic diagram of another example input/output (I/O) circuit 300 in accordance with another aspect of the disclosure. In summary, the I/O circuit 300 employs one or more predrivers that boosts both or all FETs of pull-up and pull-down circuits of the I/O circuit 300 during rising and falling transitions, respectively. This allows for faster transitions, which improves the speed of the I/O circuit 300.

(65) Further, the one or more predrivers boosts both or all FETs of the pull-up and pull-down circuits for a longer percentage (e.g., 80%) of the transition interval. Again, this also allows for faster transitions and higher speed performance of the I/O circuit 300. Additionally, the longer boosting interval during a transition reduces the effects of output impedance change, thereby reducing signal integrity (SI) degradation of the output signal V.sub.OUT.

(66) Additionally, the generation of the control signals V.sub.PCTL_HV and V.sub.PCTL_LV for the pull-up circuit or the control signals V.sub.NCTL_HV and V.sub.NCTL_LV for the pull-down circuit are responsive to a single domain signal, which prevents or reduces delay mismatch between the signals which, as previously discussed, may cause duty cycle distortion in the output signal V.sub.OUT and over-voltage stress or damage to the FETs of the output driver. Further, the current load demand for the intermediate voltage rail VDDIX or VSSIX is reduced by implementing predrivers responsible for transitions to only use the VDDPX voltage rail, which may already be configured to handle higher current loads.

(67) In particular, the I/O circuit 300 includes a voltage level shifter 310, a gate boost control circuit 320, a steady-state predriver 330, a transition predriver 340, an output driver 350, and a voltage domain splitter 360. The voltage level shifter 310 is configured to receive an input signal V.sub.IN, which may be in an IC or SOC core voltage domain, which may be referred to herein as a CX domain, and where the voltage varies between a logic high of VDDCX (e.g., 1.1V) and a logic low of VSSCX (e.g., 0.5V). The voltage level shifter 310 is configured to voltage level shift the input signal V.sub.IN to generate input signals V.sub.IN_HV and V.sub.IN_LV in the HV and LV voltage domains, respectively. The input signal V.sub.IN_LV may swing between a high logic voltage VDDPX (e.g., 1.8V) and a low logic voltage VSSIX (e.g., 0.9V); and the input signal V.sub.IN_LV may swing between a high logic voltage VDDIX (e.g., 0.9V) and a low logic voltage VSSX (e.g., 0V).

(68) The gate boost control circuit 320 is configured to generate gate boosting enable signals V.sub.TR_LV and V.sub.TF_HV for enabling the gate boosting of the PMOS FETs M.sub.21 and M.sub.22 of the pull-up circuit and the NMOS FETs M.sub.23 and M.sub.24 of the pull-down circuit of the output driver 350, respectively. As indicated, the output driver 350 may be configured per output driver of I/O circuit 200. The gate boost control circuit 320 is configured to generate the gate boosting enable signals V.sub.TR_LV and V.sub.TF_HV based on the input signals V.sub.IN_HV and V.sub.IN_LV and output voltage signals V.sub.OUT_HV and V.sub.OUT_LV generated by voltage domain splitter 360 by splitting the PX voltage domain of the output signal V.sub.OUT. As indicated by the subscripts, the output signal V.sub.OUT_HV is in the HV voltage domain, and the output signal V.sub.OUT_LV is in the LV voltage domain. As discussed in more detail herein, the input signal V.sub.IN via the associated signals V.sub.IN_HV and V.sub.IN_LV initiates the start of a gate boosting interval, and the output signal V.sub.OUT via the associated signals V.sub.OUT_HV and V.sub.OUT_LV terminates the gate boosting interval.

(69) The steady-state predriver 330 is configured to generate the control signals V.sub.PCTL_HV, V.sub.PCTL_LV, V.sub.NCTL_HV, and V.sub.NCTL_LV for the PMOS FETs M.sub.21 and M.sub.22 and NMOS FETs M.sub.23 and M.sub.24 of the output driver 350 during the steady-state intervals, respectively. A steady-state interval is the time interval when the output signal V.sub.OUT is not transitioning from one logic level or state to another logic level or state. As discussed in more detail further herein, the steady-state predriver 330 generates the control signals V.sub.PCTL_HV, V.sub.PCTL_LV, V.sub.NCTL_HV, and V.sub.NCTL_LV based on the input signals V.sub.IN_HV and V.sub.IN_LV and the gate boosting enable signals V.sub.TR_LV and V.sub.TF_HV.

(70) With reference to the timing diagram of FIG. 3B, when the output signal V.sub.OUT is at a steady-state high logic voltage VDDPX (e.g., 1.8V), the steady-state predriver 330 generates the control signals V.sub.PCTL_HV, V.sub.PCTL_LV, V.sub.NCTL_HV, and V.sub.NCTL_LV at a low logic voltage VSSIX (e.g., 0.9V), a non-boosted voltage (e.g., 0.9V), a non-boosted voltage (e.g., 0.9V), and a low logic VSSX (e.g., 0V), respectively. These voltage levels turn on PMOS FETs M.sub.21 and M.sub.22 and turn off NMOS FETs M.sub.23 and M.sub.24 so that the output signal V.sub.OUT is maintained substantially steady at VDDPX (e.g., 1.8V). Note that, during the VDDPX steady-state interval, the gate boost control circuit 320 generates gate boosting enable signals V.sub.TR_LV and the V.sub.TF_HV, which are in the LV and HV voltage domains and pertain to the rising and falling transitions, in their deasserted low VSSX (e.g., 0V) and high logic states VDDPX (e.g., 1.8V), respectively.

(71) When the output signal V.sub.OUT is at a steady-state logic low voltage VSSX (e.g., 0V), the steady-state predriver 330 generates the control signals V.sub.PCTL_HV, V.sub.PCTL_LV._v, V.sub.NCTL_HV, and V.sub.NCTL_LV at a high logic voltage VDDPX (e.g., 1.8V), the non-boosted voltage (e.g., 0.9V), the non-boosted voltage (e.g., 0.9V), and a high logic voltage VDDIX (e.g., 0.9V). These voltage levels turn off PMOS FETs M.sub.21 and M.sub.22 and turn on NMOS FETs M.sub.23 and M.sub.24 so that the output signal V.sub.OUT is maintained substantially steady at VSSX (e.g., 0V). Similarly, during the VSSX steady-state interval, the gate boost control circuit 320 generates the gate boosting enable signals V.sub.TR_LV and the V.sub.TF_HV in their deasserted low VSSX (e.g., 0V) and high VDDPX (e.g., 1.8V) logic states, respectively.

(72) The transition predriver 340 is configured to generate the control signals V.sub.PCTL_HV, V.sub.PCTL_LV, V.sub.NCTL_HV, and V.sub.NCTL_LV for the PMOS FETs M.sub.21 and M.sub.22 and NMOS FETs M.sub.3 and M.sub.24 of the output driver 350 during the transition intervals, respectively. A transition interval is the time interval when the output signal V.sub.OUT is transitioning from one logic level or state to another logic level or state. As discussed in more detail further herein, the transition predriver 340 generates the control signals V.sub.PCTL_HV, V.sub.PCTL_LV, V.sub.NCTL_HV, and V.sub.NCTL_LV based on the gate boosting enable signals V.sub.TR_LV and V.sub.TF_HV.

(73) With reference to the timing diagram of FIG. 3B, when the output signal V.sub.OUT is to be transitioned from a high logic voltage VDDPX (e.g., 1.8V) to a low logic voltage VSSX (e.g., 0V) as indicated by the input signals V.sub.IN_HV and V.sub.IN_LV changing to low logic voltages, the gate boost control circuit 320 generates the gate boosting enable signal V.sub.TF_HV in its asserted low logic state VSSIX (e.g., 0.9V) and maintains the gate boosting enable signal V.sub.TR_LV in its deasserted low logic state VSSX (e.g., 0V). In response to the deasserted gate boosting enable signal V.sub.TR_LV, the steady-state predriver 330 generates the control signals V.sub.PCTL_HV V.sub.PCTL_LV at a high logic voltage VDDPX (e.g., 1.8V) and a non-boosted voltage (e.g., 0.9V), respectively. These voltage levels turn off PMOS FETs M.sub.21 and M.sub.22.

(74) In response to the asserted gate boosting enable signal V.sub.TF_HV, the transition predriver 340 generates the control signals V.sub.NCTL_HV and V.sub.NCTL_LV at the boosted voltage levels (e.g., ˜1.4V). The control signals at these voltage levels turn on NMOS FETs M.sub.23 and M.sub.24 such that their turn-on resistance is less than the turn-on resistance when the NMOS FETs M.sub.23 and M.sub.24 are driven by the 0.9V during the steady-state low logic state VSSX of the output signal V.sub.OUT. Because of the gate boosting of NMOS FETs M.sub.23 and M.sub.24, the output signal V.sub.OUT transitions quickly from VDDPX (e.g., 1.8V) to VSSX (e.g., 0V). At about 80% of the high-to-low transition of the output signal V.sub.OUT, the gate boost control circuit 320 deasserts the gate boosting enable signal V.sub.TF_HV (e.g., brings it back to VDDPX (e.g., 1.8V)). In response, the transition predriver 340 hands over control of the V.sub.NCTL_HV and V.sub.NCTL_LV signals to the steady-state predriver 330, which changes their states to the non-boosted voltage levels VDDIX and VSSIX (e.g., both 0.9V), respectively.

(75) When the output signal V.sub.OUTr is to be transitioned from a low logic voltage VSSX (e.g., 0V) to a high logic voltage VDDPX (e.g., 1.8V) as indicated by the input signals V.sub.IN_HV and V.sub.IN_LV changing to high logic voltages, the gate boost control circuit 320 generates the gate boosting enable signal V.sub.TR_LV in its asserted low logic state VDDIX (e.g., 0.9V) and maintains the gate boosting enable signal V.sub.TF_HV in its deasserted high logic state VDDPX (e.g., 1.8V). In response to the deasserted gate boosting enable signal V.sub.TF_HV, the steady-state predriver 330 generates the control signals V.sub.NCTL_HV and V.sub.NCTL_LV at the non-boosted voltage (e.g., 0.9V) and a low logic voltage VSSX (e.g., 0V), respectively. The control signals at these voltage levels turn off NMOS FETs M.sub.23 and M.sub.24.

(76) In response to the asserted gate boosting enable signal V.sub.TR_LV, the transition predriver 340 generates the control signals V.sub.PCTL_HV and V.sub.PCTL_LV at the boosted voltage levels (e.g., −0.4V). These voltage levels turn on PMOS FETs M.sub.21 and M.sub.22 such that their turn-on resistance is less than the turn-on resistance when the PMOS FETs M.sub.21 and M.sub.22 are driven by the non-boosted voltage, e.g., 0.9V, during the steady-state low logic state VSSX of the output signal V.sub.OUT. Because of the gate boosting of PMOS FETs M.sub.21 and M.sub.22, the output signal V.sub.OUT transitions quickly from VSSX (e.g., 0V) to VDDPX (e.g., 1.8V). At about 80% of the low-to-high transition of the output signal V.sub.OUT, the gate boost control circuit 320 deasserts the gate boosting enable signal V.sub.TR_LV (e.g., brings it back to VSSX (e.g., 0V)). In response, the transition predriver 340 hands over control of the V.sub.PCTL_HV and V.sub.PCTL_LV signals to the steady-state predriver 330, which changes their states to the non-boosted voltage levels VSSIX and VDDIX (e.g., both 0.9V), respectively.

(77) FIG. 4 illustrates a block diagram of an example pull-down gate boost control circuit 400 in accordance with another aspect of the disclosure. The pull-down gate boost control circuit 400 may be an example detailed implementation of the pull-down side or portion of the gate boost control circuit 320 previously discussed. That is, the gate boost control circuit 400 is configured to generate the pull-down gate boosting enable signal V.sub.TF_HV based on the input signals V.sub.IN_HV and V.sub.IN_LV, and the output signals V.sub.OUT_HV and V.sub.OUT_LV. As previously discussed, the pull-down gate boost control circuit 400 generates the gate boosting enable signal V.sub.TF_HV at an asserted low logic voltage VSSIX (e.g., 0.9V) during a falling transition interval (e.g., 80% thereof) of the output signal V.sub.OUT, and at a deasserted high logic voltage VDDPX (e.g., 1.8V) during the steady-state and rising transition intervals.

(78) In particular, the pull-down gate boost control circuit 400 includes first and second inverters 405 and 410, a hysteresis logic device 420, a first multi-domain logic circuit 430, a second multi-domain logic circuit 440, and a logic gate 450 (e.g., a NAND gate). A multi-domain logic circuit is a logic circuit that operates on signals in different voltages domains (e.g., HV and LV voltage domains). The first inverter 405 is configured to receive and invert the input signal V.sub.IN_LV in the LV voltage domain to generate a complementary input signal V.sub.IN_LV also in the LV voltage domain. The second inverter 410 is configured to receive and invert the output signal V.sub.OUT_HV in the HV voltage domain to generate a complementary output signal V.sub.OUT_HV also in the HV voltage domain.

(79) The first multi-domain logic circuit 430 is configured to receive the input signal V.sub.IN_HV in the HV voltage domain and the complementary input signal V.sub.IN_LV, and generate a pull-down gate boosting initiating signal V.sub.TF1_HV in the HV voltage domain. The second multi-domain logic circuit 440 is configured to receive the complementary output signal V.sub.OUT_HV and the output signal V.sub.OUT_LV in the LV voltage domain, and generate therefrom a pull-down gate boosting terminating signal V.sub.TF2_HV in the HV voltage domain. The second multi-domain logic circuit 440 may be configured to receive the output signal V.sub.OUT_LV via the hysteresis logic device 420. The hysteresis logic device 420 has two switching thresholds: an upper threshold where the hysteresis logic device 420 generates a high logic voltage upon the signal V.sub.OUT_LV rising above the upper threshold, and a lower threshold where the hysteresis logic device 420 generates a low logic voltage upon the signal V.sub.OUT_LV falling below the lower threshold. This is done so that the pull-down gate boosting terminating signal V.sub.TF2_HV changes in response to a lower voltage of V.sub.OUT_LV. This has the effect of delaying the termination of the gate boosting interval. The NAND gate 450 logically NANDs the gate boosting initiating and terminating signals V.sub.TF1_HV and V.sub.TF2_HV to generate the pull-down gate boosting enable signal V.sub.TF_HV in the HV voltage domain.

(80) As previously discussed, the input signal V.sub.IN initiates the pull-down gate boosting interval and the output signal V.sub.OUT terminates the pull-down gate boosting interval. Prior to the falling transition, the input and output signals V.sub.IN and V.sub.OUT are at high logic steady-states. In response to the input signal V.sub.IN being logically high, the voltage level shifter 310 generates the input signals V.sub.IN_HV and V.sub.IN_LV logically high VDDPX (e.g., 1.8V) and VDDIX (e.g., 0.9V), respectively. Similarly, in response to the output signal V.sub.OUT being logically high, the voltage domain splitter 460 generates the output signals V.sub.OUT_HV and V.sub.OUT_LV logically high VDDPX (e.g., 1.8V) and VDDIX (e.g., 0.9V).

(81) In the current implementation, the first multi-domain logic circuit 430 inverts the signal V.sub.IN_HV to generate the pull-down gate boosting initiating signal V.sub.TF1_HV. As the signal V.sub.IN_HV is logically high, the pull-down gate boosting initiating signal V.sub.TF1_HV is logically low. Similarly, the second multi-domain logic circuit 440 inverts the signal V.sub.OUT_HV to generate the pull-down gate boosting terminating signal V.sub.TF2_HV. As the signal V.sub.OUT_HV is logically low, the pull-down gate boosting terminating signal V.sub.TF2_HV is logically high. As the NAND gate 450 sees logically low and high input signals V.sub.TF1_HV and V.sub.TF2_HV, the NAND gate 450 generates the pull-down gate boosting enable signal V.sub.TF_HV in its deasserted high logic state VDDPX (e.g., 1.8V), as the output signal V.sub.OUT is at a steady-state high VDDPX.

(82) When the input signal V.sub.IN subsequently transitions to a low logic state, the voltage level shifter 310 generates the input signals V.sub.IN_HV and V.sub.IN_LV at logically low VSSIX (e.g., 0.9V) and logically high VDDIX (e.g., 0.9V) states, respectively. In response, the first multi-domain logic circuit 430 inverts the low logic signal V.sub.IN_HV to generate the pull-down gate boosting initiating signal V.sub.TF1_HV as an asserted high logic voltage VDDPX (e.g., 1.8V). As the NAND gate 450 now sees logically high input signals V.sub.TF1_HV and V.sub.TF2_HV, the NAND gate 450 generates the pull-down gate boosting enable signal V.sub.TF_HV in the asserted low logic level VSSIX (e.g., 0.9V) to initiate the pull-down gate boosting interval. As previously mentioned, the pull-down gate boosting interval is initiated in response to the input signal V.sub.IN transitioning to a low logic state.

(83) When the output signal V.sub.OUT substantially transitions to a low logic state, the voltage domain splitter 360 generates the output signals V.sub.OUT_HV and V.sub.OUT_LV at logic low states VSSIX (e.g., 0.9V) and VSSX (e.g., 0V), respectively. In response, the second multi-domain logic circuit 440 inverts the high logic signal V.sub.OUT_HV to generate the pull-down gate boosting terminating signal V.sub.TF2_HV as an asserted low logic voltage VSSIX (e.g., 0.9V). As the NAND gate 450 now sees logically high and low input signals V.sub.TF1_HV and V.sub.TF2_HV, the NAND gate 450 generates the pull-down gate boosting enable signal V.sub.TF_HV in its deasserted high logic state VDDPX (e.g., 1.8V) to terminate the pull-down gate boosting interval. As previously mentioned, the pull-down gate boosting interval is terminated in response to the output signal V.sub.OUT transitioning to a low logic state.

(84) FIG. 5 illustrates a block diagram of an example multi-domain logic circuit 500 in accordance with another aspect of the disclosure. The multi-domain logic circuit 500 includes an inverter 510 including a first FET M.sub.51 and a second FET M.sub.52. The first FET M.sub.51 may be implemented as a PMOS FET, and the second FET M.sub.52 may be implemented as an NMOS FET. The multi-domain logic circuit 500 further includes a third FET M.sub.53, which may be implemented as a PMOS FET. The inverter 510 and the PMOS FET M.sub.53 are coupled in series between an upper voltage rail VDDPX and a lower voltage rail VSSIX (e.g., associated with the HV voltage domain).

(85) The PMOS FET M.sub.53 includes a gate configured to receive a signal V2.sub.LV. With reference to the pull-down gate boost control circuit 400, the signal V2.sub.LV may be the complementary input signal V.sub.IN_LV if the multi-domain logic circuit 500 corresponds to the first multi-domain logic circuit 430, or the output signal V.sub.OUT_LV if the multi-domain logic circuit 500 corresponds to the second multi-domain logic circuit 440.

(86) The PMOS FET M.sub.51 and the NMOS FET M.sub.52 include respective gates coupled together to form an input of the inverter 510, and configured to receive the complementary signal V1.sub.HV. With reference to the pull-down gate boost control circuit 400, the complementary signal V1.sub.HV may be the input signal V.sub.IN_HV if the multi-domain logic circuit 500 corresponds to the first multi-domain logic circuit 430, or the complementary output-based signal V.sub.OUT_HV if the multi-domain logic circuit 500 corresponds to the second multi-domain logic circuit 440.

(87) The PMOS FET M.sub.51 and the NMOS FET M.sub.52 include respective drains coupled together to form an output of the inverter 510, and configured to generate the output signal V.sub.OUT_HV. With reference to the pull-down gate boost control circuit 400, the output signal V.sub.OUT_HV may be the pull-down gate boosting initiating signal V.sub.TF1_HV if the multi-domain logic circuit 500 corresponds to the first multi-domain logic circuit 430, or the pull-down gate boosting terminating signal V.sub.TF2_HV if the multi-domain logic circuit 500 corresponds to the second multi-domain logic circuit 440. The multi-domain logic circuit 500 may optionally include a latch 520 (e.g., cross-coupled inverters) configured to latch the logic state of the V.sub.OUT_HV.

(88) FIG. 6 illustrates a block diagram of an example pull-up gate boost control circuit 600 in accordance with another aspect of the disclosure. The pull-up gate boost control circuit 600 may be an example detailed implementation of the pull-up side or portion of the gate boost control circuit 320 previously discussed. That is, the pull-up gate boost control circuit 600 is configured to generate the pull-up gate boosting enable signal V.sub.TR_LV based on the input signals V.sub.IN_HV and V.sub.IN_LV, and the output signals V.sub.OUT_HV and V.sub.OUT_LV. As previously discussed, the pull-up gate boost control circuit 600 generates the gate boosting enable signal V.sub.TR_LV at an asserted high logic voltage VDDPX (e.g., 1.8V) during a rising transition interval (e.g., 80% thereof) of the output signal V.sub.OUT, and at a deasserted low logic voltage VSSIX (e.g., 0.9V) during the steady-state and falling transition intervals.

(89) In particular, the pull-up gate boost control circuit 600 includes first and second inverters 605 and 610, a hysteresis logic device 620, a first multi-domain logic circuit 630, a second multi-domain logic circuit 640, and a logic gate 650 (e.g., an AND gate). The first inverter 605 is configured to receive and invert the input signal V.sub.IN_LV to generate a complementary input signal V.sub.IN_LV. The second inverter 610 is configured to receive and invert the output signal V.sub.OUT_HV to generate a complementary output signal V.sub.OUT_HV.

(90) The first multi-domain logic circuit 630 is configured to receive the input signal V.sub.IN_HV and the complementary input signal V.sub.IN_LV, and generate a pull-up gate boosting initiating signal V.sub.TR1_LV in the LV voltage domain. The second multi-domain logic circuit 640 is configured to receive the complementary output signal V.sub.OUT_HV and the output signal V.sub.OUT_LV, and generate therefrom a pull-up gate boosting terminating signal V.sub.TR2_LV in the LV voltage domain. The second multi-domain logic circuit 640 may be configured to receive the complementary output signal V.sub.OUT_HV via the hysteresis logic device 620. Similarly, the hysteresis logic device 620 has two switching thresholds: an upper threshold where the hysteresis logic device 620 generates a high logic voltage upon the signal V.sub.OUT_HV rising above the upper threshold, and a lower threshold where the hysteresis logic device 620 generates a low logic voltage upon the signal V.sub.OUT_HV falling below the lower threshold. This is done so that the pull-up gate boosting terminating signal V.sub.TR2_LV changes in response to a higher voltage of V.sub.OUT_HV. This has the effect of delaying the termination of the gate boosting interval. The AND gate 650 logically ANDs the gate boosting initiating and terminating signals V.sub.TR1_LV and V.sub.TR2_LV to generate the pull-up gate boosting enable signal V.sub.TR_LV in the LV voltage domain.

(91) As previously discussed, the input signal V.sub.IN initiates the pull-up gate boosting interval and the output signal V.sub.OUT terminates the pull-up gate boosting interval. Prior to the rising transition, the input and output signals V.sub.IN and V.sub.OUT are at low logic steady-states. In response to the input signal V.sub.IN being logically low, the voltage level shifter 310 generates the input signals V.sub.IN_HV and V.sub.IN_LV logically low VSSIX (e.g., 0.9V) and VSSX (e.g., 0V), respectively. Similarly, in response to the output signal V.sub.OUT being logically low, the voltage domain splitter 460 generates the output signals V.sub.OUT_HV and V.sub.OUT_LV logically low VSSIX (e.g., 0.9V) and VSSX (e.g., 0V).

(92) The first multi-domain logic circuit 630 inverts the signal V.sub.IN_LV to generate the pull-up gate boosting initiating signal V.sub.TR1_LV. As the signal V.sub.IN_LV is logically high, the pull-up gate boosting initiating signal V.sub.TR1_LV is logically low. Similarly, the second multi-domain logic circuit 640 inverts the signal V.sub.OUT_LV to generate the pull-up gate boosting terminating signal V.sub.TR2_LV. As the signal V.sub.OUT_LV is logically low, the pull-up gate boosting terminating signal V.sub.TR1_LV is logically high. As the AND gate 650 sees logically low and high input signals V.sub.TR_LV and V.sub.TR2_LV, the AND gate 650 generates the pull-up gate boosting enable signal V.sub.TR_LV in its deasserted low logic state VSSX (e.g., 0V), as the output signal V.sub.OUT is at a steady-state low VSSX.

(93) When the input signal V.sub.IN subsequently transitions to a high logic state, the voltage level shifter 310 generates the input signals V.sub.IN_HV and V.sub.IN_LV at logically high VDDPX (e.g., 1.8V) and logically low VSSX (e.g., 0V) states, respectively. In response, the first multi-domain logic circuit 630 inverts the low logic signal V.sub.IN_LV to generate the pull-up gate boosting initiating signal V.sub.TR1_LV as an asserted high logic voltage VDDIX (e.g., 0.9V). As the AND gate 650 now sees logically high input signals V.sub.TR1_LV and V.sub.TR2_LV, the AND gate 650 generates the pull-up gate boosting enable signal V.sub.TR_LV in the asserted high logic level VDDIX (e.g., 0.9V) to initiate the pull-up gate boosting interval. As previously mentioned, the pull-up gate boosting interval is initiated in response to the input signal V.sub.IN transitioning to a high logic state.

(94) When the output signal V.sub.OUT substantially transitions to a high logic state, the voltage domain splitter 360 generates the output signals V.sub.OUT_HV and V.sub.OUT_LV at high logic states VDDPX (e.g., 1.8V) and VDDIX (e.g., 0.9V), respectively. In response, the second multi-domain logic circuit 640 inverts the high logic signal V.sub.OUT_LV to generate the pull-up gate boosting terminating signal V.sub.TR2_LV as an asserted high logic voltage VDDIX (e.g., 0.9V). As the AND gate 650 now sees logically high and low input signals V.sub.TR1_LV and V.sub.TR_LV, the AND gate 650 generates the pull-up gate boosting enable signal V.sub.TR_LV in its deasserted low logic state VSSX (e.g., 0V) to terminate the pull-up gate boosting interval. As previously mentioned, the pull-up gate boosting interval is terminated in response to the output signal V.sub.OUT transitioning to a high logic state.

(95) FIG. 7 illustrates a block diagram of an example multi-domain logic circuit 700 in accordance with another aspect of the disclosure. The multi-domain logic circuit 700 includes a first FET M.sub.71, which may be implemented as NMOS FET. The multi-domain logic circuit 700 further includes an inverter 710 including a second FET M.sub.72 and a third FET M.sub.73. The second FET M.sub.72 may be implemented as a PMOS FET, and the third FET M.sub.73 may be implemented as an NMOS FET. The NMOS FET M.sub.71 and the inverter 710 are coupled in series between an upper voltage rail VDDIX and a lower voltage rail VSSX (e.g., associated with the LV voltage domain).

(96) The NMOS FET M.sub.71 includes a gate configured to receive a signal V1.sub.HV. With reference to the pull-up gate boost control circuit 600, the signal V1.sub.HV may be the input signal V.sub.IN_HV if the multi-domain logic circuit 700 corresponds to the first multi-domain logic circuit 630, or the output signal V.sub.OUT_HV if the multi-domain logic circuit 700 corresponds to the second multi-domain logic circuit 640.

(97) The PMOS FET M.sub.72 and the NMOS FET M.sub.73 include respective gates coupled together to form an input of the inverter 710, and configured to receive the complementary signal V2.sub.LV. With reference to the pull-up gate boost control circuit 600, the complementary signal V2.sub.LV may be the complementary input signal V.sub.IN_LV if the multi-domain logic circuit 700 corresponds to the first multi-domain logic circuit 630, or the output signal V.sub.OUT_LV if the multi-domain logic circuit 700 corresponds to the second multi-domain logic circuit 640.

(98) The PMOS FET M.sub.72 and the NMOS FET M.sub.73 include respective drains coupled together to form an output of the inverter 710, and configured to generate the output signal V.sub.OUT_LV. With reference to the pull-up gate boost control circuit 600, the output signal V.sub.OUT_LV may be the pull-up gate boosting initiating signal V.sub.TR1_LV if the multi-domain logic circuit 700 corresponds to the first multi-domain logic circuit 630, or the pull-up gate boosting terminating signal V.sub.TR2_LV if the multi-domain logic circuit 700 corresponds to the second multi-domain logic circuit 640. The multi-domain logic circuit 700 may optionally include a latch 720 (e.g., cross-coupled inverters) configured to latch the logic state of the V.sub.OUT_LV.

(99) FIG. 8 illustrates a schematic diagram of an example first pull-up predriver 800 in accordance with another aspect of the disclosure. The first pull-up predriver 800 may be the portion of the steady-state and transition predrivers 330 and 340 that generates the control signal V.sub.PCTL_HV for the PMOS FET M.sub.21 of output driver 350. The first pull-up predriver 800 includes a first steady-state pull-up predriver 810 and a first pull-up transition predriver 830.

(100) The first steady-state pull-up predriver 810 includes an inverter 820 coupled in series with a PMOS FET M.sub.83 between the upper voltage rail VDDPX and the lower voltage rail VSSIX associated with the HV voltage domain. The inverter 820, in turn, includes a PMOS FET M.sub.81 and an NMOS FET M.sub.82. The PMOS FET M.sub.81 and the NMOS FET M.sub.82 include gates coupled together to form an input of the inverter 820. The input of the inverter 820 is configured to receive the input signal V.sub.IN_HV in the HV voltage domain. The PMOS FET M.sub.81 and the NMOS FET M.sub.82 include drains coupled together to form an output of the inverter 820, which also serves as the output of the first pull-up predriver 800, and is coupled to the gate of PMOS FET M.sub.21. During the steady-state high and low, and the falling transition of the output signal V.sub.OUT, the inverter 820 is configured to generate the control signal V.sub.PCTL_HV for the PMOS FET M.sub.21 of the output driver 350. The PMOS FET M.sub.83 includes a gate configured to receive the pull-up gate boosting enable signal V.sub.TR_LV.

(101) The first pull-up transition predriver 830 includes an NMOS FET M.sub.84 coupled between the upper voltage rail VDDPX and the output of the first pull-up predriver 800. The first pull-up transition predriver 830 further includes a diode-connected NMOS FET M.sub.85, an NMOS FET M.sub.86, and another NMOS FET M.sub.87 coupled in series between the output of the first pull-up predriver 800 and the lower voltage rail VSSX. The NMOS FET M.sub.84 includes a gate configured to receive a bias voltage VSSIX (e.g., 0.9V). The NMOS FET M.sub.85 is diode-connected because its drain and gate are coupled together. The NMOS FET M.sub.86 includes a gate configured to receive a bias voltage VDDIX (e.g., 0.9V). The NMOS FET M.sub.57 includes a gate configured to receive the pull-up gate boosting enable signal V.sub.TR_LV.

(102) With further reference to FIG. 3B, the operation of the first pull-up predriver 800 is as follows: The control signal V.sub.PCTL_HV is in a low logic state VSSIX (e.g., 0.9V) when the output signal V.sub.OUT is at a steady-state high logic state VDDPX (e.g., 1.8V). When the output signal V.sub.OUT is at the steady-state high logic state VDDPX (e.g., 1.8V), the input signal V.sub.IN_HV is at a high logic state VDDPX (e.g., 1.8V), and the pull-up gate boosting enable signal V.sub.TR_LV is in the deasserted low logic state VSSX (e.g., 0V). As such, the PMOS FET M.sub.83 is turned on to enable the inverter 820, and the inverter 820 inverts the high logic state VDDPX (e.g., 1.8V) of the input signal V.sub.IN_HV to generate the control signal V.sub.PCTL_HV at the low logic state VSSIX (e.g., 0.9V). During this steady-state, the first pull-up transition predriver 830 is disabled because the low logic state VSSX (e.g., 0V) of the pull-up gate boosting enable signal V.sub.TR_LV maintains NMOS FET M.sub.87 turned off.

(103) The control signal V.sub.PCTL_HV is in a high logic state VDDPX (e.g., 1.8V) when the output signal V.sub.OUT is at a steady-state low logic state VSSX (e.g., 0V). When the output signal V.sub.OUT is at the steady-state low logic state VSSX (e.g., 0V), the input signal V.sub.IN_HV is at a low logic state VSSX (e.g., 0V), and the pull-up gate boosting enable signal V.sub.TR_LV is in the deasserted low logic state VSSX (e.g., 0V). As such, the PMOS FET M.sub.83 is turned on to enable the inverter 820, and the inverter 820 inverts the low logic state VSSX (e.g., 0V) of the input signal V.sub.IN_HV to generate the control signal V.sub.PCTL_HV at the high logic state VDDPX (e.g., 1.8V). Similarly, during this steady-state, the first pull-up transition predriver 830 is disabled because the low logic state VSSX (e.g., 0V) of the pull-up gate boosting enable signal V.sub.TR_LV maintains NMOS FET M.sub.87 turned off.

(104) The control signal V.sub.PCTL_HV is in a high logic state VDDPX (e.g., 1.8V) when the output signal V.sub.OUT is transitioning from a high logic state VDDPX (e.g., 1.8V) to a low logic state VSSX (e.g., 0V). When the output signal V.sub.OUT is transitioning to the low logic state VSSX (e.g., 0V), the input signal V.sub.IN_HV is at a low logic state VSSX (e.g., 0.9V), and the pull-up gate boosting enable signal V.sub.TR_LV is in the deasserted low logic state VSSX (e.g., 0V). As such, the PMOS FET M.sub.83 is turned on to enable the inverter 820, the inverter 820 inverts the low logic state VSSX (e.g., 0V) of the input signal V.sub.IN_HV to generate the control signal V.sub.PCTL_HV at the high logic state VDDPX (e.g., 1.8V). During this high-to-low transition interval, the first pull-up transition predriver 830 is disabled because the low logic state VSSX (e.g., 0V) of the pull-up gate boosting enable signal V.sub.TR_LV maintains NMOS FET M.sub.87 turned off.

(105) The control signal V.sub.PCTL_HV is in a boosted state (e.g., ˜0.4V) when the output signal V.sub.OUT is transitioning from a low logic state VSSX (e.g., 0V) to a high logic state VDDPX (e.g., 1.8V). When the output signal V.sub.OUT is transitioning to the high logic state VDDPX (e.g., 1.8V), the input signal V.sub.IN_HV is at a high logic state VDDPX (e.g., 1.8V), and the pull-up gate boosting enable signal V.sub.TR_LV is in the asserted high logic state VDDIX (e.g., 0.9V). As such, the PMOS FET M.sub.83 is turned off to disable the first steady-state pull-up predriver 810. The pull-up gate boosting enable signal V.sub.TR_LV being in the enabled high logic state VDDIX (e.g., 0.9V) turns on NMOS FET M.sub.87 to produce a current path between VDDPX and VSSX. The turning on of NMOS FET M.sub.87 also causes NMOS FET M86 to turn on. Thus, the diode-connected NMOS FET M.sub.85 is coupled between the output of the first pull-up predriver 800 and the lower voltage rail VSSX; thereby generating the control signal V.sub.PCTL_HV at the boosted voltage level of about 0.4V (e.g., the voltage drop across the diode-connected NMOS FET M.sub.85). The top NMOS FET M.sub.84 is configured to limit the current between VDDPX and VSSX.

(106) FIG. 9 illustrates a schematic diagram of an example second pull-up predriver 900 in accordance with another aspect of the disclosure. The second pull-up predriver 900 may be the portion of the steady-state and transition predrivers 330 and 340 that generates the control signal V.sub.PCTL_LV for the PMOS FET M.sub.22 of output driver 350. The second pull-up predriver 900 includes a second steady-state pull-up predriver 910 and a second pull-up transition predriver 930.

(107) The second steady-state pull-up predriver 910 includes a PMOS FET M.sub.91 including a source configured to receive a bias voltage VDDIX (e.g., 0.9V), a gate configured to receive the pull-up gate boosting enable signal V.sub.TR_LV, and a drain serving as the output of the second pull-up predriver 900 to generate the control signal V.sub.PCTL_LV for the PMOS FET M.sub.22 of the output driver 350 (the output of the second pull-up predriver 900 being coupled to the gate of PMOS FET M.sub.22).

(108) The second pull-up transition predriver 930 includes an NMOS FET M.sub.92 coupled between the upper voltage rail VDDPX and the output of the second pull-up predriver 900. The second pull-up transition predriver 930 further includes a diode-connected NMOS FET M.sub.93 coupled in series with an NMOS FET M.sub.94 between the output of the second pull-up predriver 900 and the lower voltage rail VSSX. The NMOS FET M.sub.92 includes a gate configured to receive a bias voltage VSSIX (e.g., 0.9V). The NMOS FET M.sub.93 is diode-connected because its drain and gate are coupled together. The NMOS FET M.sub.94 includes a gate configured to receive the pull-up gate boosting enable signal V.sub.TR_LV.

(109) With further reference to FIG. 3B, the operation of the second pull-up predriver 900 is as follows: The control signal V.sub.PCTL_LV is in a non-boosted state (e.g., 0.9V) when the output signal V.sub.OUT, is in the steady-state high logic state VDDPX (e.g., 1.8V), the steady-state low logic state VSSX (e.g., 0V), or transitioning from high-to-low. When the output signal V.sub.OUT is at the aforementioned states, the pull-up gate boosting enable signal V.sub.TR_LV is in the deasserted low logic state VSSX (e.g., 0V). As such, the PMOS FET M.sub.91 is turned on to output its source voltage VDDIX (e.g., 0.9V) as the control signal V.sub.PCTL_LV. During these states, the second pull-up transition predriver 930 is disabled because the low logic state VSSX (e.g., 0V) of the pull-up gate boosting enable signal V.sub.TR_LV maintains NMOS FET M.sub.94 turned off.

(110) The control signal V.sub.PCTL_LV is in a boosted state (e.g., ˜0.4V) when the output signal V.sub.OUT is transitioning from a low logic state VSSX (e.g., 0V) to a high logic state VDDPX (e.g., 1.8V). When the output signal Vou-r is transitioning to the high logic state VDDPX (e.g., 1.8V), the pull-up gate boosting enable signal V.sub.TR_LV is in the asserted high logic state VDDIX (e.g., 0.9V). As such, the PMOS FET M.sub.91 is turned off to disable the second steady-state pull-up predriver 910. The pull-up gate boosting enable signal V.sub.TR_LV being in the asserted high logic state VDDIX (e.g., 0.9V) turns on NMOS FET M.sub.94 to produce a current path between VDDPX and VSSX. Thus, the diode-connected NMOS FET M.sub.93 is coupled between the output of the second pull-up predriver 900 and the lower voltage rail VSSX; thereby generating the control signal V.sub.PCTL_LV at the boosted voltage level ˜0.4V (e.g., the voltage drop across the diode-connected NMOS FET M.sub.93). The top NMOS FET M.sub.92 is configured to limit the current between VDDPX and VSSX.

(111) FIG. 10 illustrates a schematic diagram of an example first pull-down predriver 1000 in accordance with another aspect of the disclosure. The first pull-down predriver 1000 may be the portion of the steady-state and transition predrivers 330 and 340 that generates the control signal V.sub.NCTL_LV for the NMOS FET M.sub.24 of output driver 350. The first pull-down predriver 1000 includes a first steady-state pull-down predriver 1010 and a first pull-down transition predriver 1030.

(112) The first steady-state pull-down predriver 1010 includes an NMOS FET M.sub.101 coupled in series with an inverter 1020 between the upper voltage rail VDDIX and the lower voltage rail VSSX associated with the LV voltage domain. The NMOS FET M.sub.101 includes a gate configured to receive the pull-down gate boosting enable signal V.sub.TF_HV. The inverter 1020, in turn, includes a PMOS FET M.sub.102 and an NMOS FET M.sub.103. The PMOS FET M.sub.102 and the NMOS FET M.sub.103 include gates coupled together to form an input of the inverter 1020. The input of the inverter 1020 is configured to receive the input signal V.sub.IN_LV in the LV voltage domain. The PMOS FET M.sub.102 and the NMOS FET M.sub.103 include drains coupled together to form an output of the inverter 1020, which also serves as the output of the first pull-down predriver 1000, and is coupled to the gate of NMOS FET M.sub.24. During steady-state high and low, and the rising transition of the output signal V.sub.OUT, the inverter 1020 is configured to generate the control signal V.sub.NCTL_LV for the NMOS FET M.sub.24 of the output driver 350.

(113) The first pull-down transition predriver 1030 includes a first PMOS FET M.sub.104, a second PMOS FET M.sub.105, and a diode-connected PMOS FET M.sub.105 coupled in series between the upper voltage rail VDDPX and the output of the first pull-down predriver 1000. The first pull-down transition predriver 1030 further includes a third PMOS FET M.sub.107 coupled between the output of the first pull-down predriver 1000 and the lower voltage rail VSSX. The PMOS FET M.sub.104 includes a gate configured to receive the pull-down gate boosting enable signal V.sub.TF_HV. The PMOS FET M.sub.105 includes a gate configured to receive a bias voltage VSSIX (e.g., 0.9V). The PMOS FET M.sub.106 is diode-connected because its drain and gate are coupled together. The PMOS FET M.sub.107 includes a gate configured to receive a bias voltage VDDIX (e.g., 0.9V).

(114) With further reference to FIG. 3B, the operation of the first pull-down predriver 1000 is as follows: The control signal V.sub.NCTL_LV is in a high logic state VDDIX (e.g., 0.9V) when the output signal V.sub.OUT is at a steady-state low logic state VSSX (e.g., 0V). When the output signal V.sub.OUT is at the steady-state low logic state VSSX (e.g., 0V), the input signal V.sub.IN_LV is at a low logic state VSSX (e.g., 0V), and the pull-down gate boosting enable signal V.sub.TF_HV is in the deasserted high logic state VDDPX (e.g., 1.8V). As such, the NMOS FET M.sub.101 is turned on to enable the inverter 1020, and the inverter 1020 inverts the low logic state VSSX (e.g., 0V) of the input signal V.sub.IN_LV to generate the control signal V.sub.NCTL_LV at the high logic state VDDIX (e.g., 0.9V). During this steady-state, the first pull-down transition predriver 1030 is disabled because the deasserted high logic state VDDPX (e.g., 1.8V) of the pull-down gate boosting enable signal V.sub.TF_HV maintains the PMOS FET M.sub.104 turned off.

(115) The control signal V.sub.NCTL_LV is in a low logic state VSSX (e.g., 0V) when the output signal V.sub.OUT is at a steady-state high logic state VDDPX (e.g., 1.8V). When the output signal V.sub.OUT is at the steady-state high logic state VDDPX (e.g., 1.8V), the input signal V.sub.IN_LV is at a high logic state VDDIX (e.g., 0.9V), and the pull-down gate boosting enable signal V.sub.TF_HV is in the deasserted high logic state VDDPX (e.g., 1.8V). As such, the NMOS FET M.sub.101 is turned on to enable the inverter 1020, and the inverter 1020 inverts the high logic state VDDIX (e.g., 0.9V) of the input signal V.sub.IN_LV to generate the control signal V.sub.NCTL_LV at the low logic state VSSX (e.g., 0V). Similarly, during this steady-state, the first pull-down transition predriver 1030 is disabled because the deasserted high logic state VDDPX (e.g., 1.8V) of the pull-down gate boosting enable signal V.sub.TF_HV maintains PMOS FET M.sub.104 turned off.

(116) The control signal V.sub.NCTL_LV is in a low logic state VSSX (e.g., 0V) when the output signal Vou-r is transitioning from a low logic state VSSX (e.g., 0V) to a high logic state VDDPX (e.g., 1.8V). When the output signal V.sub.OUT is transitioning to the high logic state VDDPX (e.g., 1.8V), the input signal V.sub.IN_LV is at a high logic state VDDIX (e.g., 0.9V), and the pull-down gate boosting enable signal V.sub.TF_HV is in the deasserted high logic state VDDPX (e.g., 1.8V). As such, the NMOS FET M.sub.101 is turned on to enable the inverter 1020, and the inverter 1020 inverts the high logic state VDDIX (e.g., 0.9V) of the input signal V.sub.IN_LV to generate the control signal V.sub.NCTL_LV at the low logic state VSSX (e.g., 0V). During this low-to-high transition interval, the first pull-down transition predriver 1030 is disabled because the deasserted high logic state VDDPX (e.g., 1.8V) of the pull-down gate boosting enable signal V.sub.TF_HV maintains NMOS FET M.sub.104 turned off.

(117) The control signal V.sub.NCTL_LV is in a boosted state (e.g., ˜1.4V) when the output signal V.sub.OUT is transitioning from a high logic state VDDPX (e.g., 1.8V) to a low logic state VSSX (e.g., 0V). When the output signal V.sub.OUT is transitioning to the low logic state VSSX (e.g., 0V), the input signal V.sub.IN_LV is at a low logic state VSSX (e.g., 0V), and the pull-down gate boosting enable signal V.sub.TF_HV is in the asserted low logic state VSSIX (e.g., 0.9V). As such, the NMOS FET M.sub.101 is turned off to disable the first steady-state pull-down predriver 1010. The pull-down gate boosting enable signal V.sub.TF_HV being in the asserted low logic state VSSIX (e.g., 0.9V) turns on PMOS FET M.sub.104 to produce a current path between VDDPX and VSSX. The turning on of PMOS FET M.sub.104 also causes PMOS FET M.sub.105 to turn on. Thus, the diode-connected PMOS FET M.sub.106 is coupled between the upper voltage rail VDDPX and output of the first pull-down predriver 1000; thereby generating the control signal V.sub.NCTL_LV at the boosted voltage level of about ˜1.4V (e.g., a diode voltage drop below the VDDPX (e.g., 1.8V)). The bottom PMOS FET M.sub.107 is configured to limit the current between VDDPX and VSSX.

(118) FIG. 11 illustrates a schematic diagram of an example second pull-down predriver 1100 in accordance with another aspect of the disclosure. The second pull-down predriver 1100 may be the portion of the steady-state and transition predrivers 330 and 340 that generates the control signal V.sub.NCTL_HV for the NMOS FET M.sub.23 of output driver 350. The second pull-down predriver 1100 includes a second steady-state pull-down predriver 1110 and a second pull-down transition predriver 1130.

(119) The second steady-state pull-down predriver 1110 includes an NMOS FET M.sub.121 including a drain configured to receive a bias voltage VSSIX (e.g., 0.9V), a gate configured to receive the pull-down gate boosting enable signal V.sub.TF_HV, and a drain serving as the output of the second pull-down predriver 1100 to generate the control signal V.sub.NCTL_HV for the NMOS FET M.sub.23 of the output driver 350 (the output of the second pull-down predriver 1100 being coupled to the gate of NMOS FET M.sub.23).

(120) The second pull-down transition predriver 1130 includes a PMOS FET M.sub.122 coupled in series with a diode-connected PMOS FET M.sub.123 between the upper voltage rail VDDPX and the output of the second pull-down predriver 1100. The second pull-down transition predriver 1130 further includes a PMOS FET M.sub.124 coupled between the output of the second pull-down predriver 1100 and the lower voltage rail VSSX. The PMOS FET M.sub.122 includes a gate configured to receive the pull-down gate boosting enable signal V.sub.TF_HV. The PMOS FET M.sub.123 is diode-connected because its drain and gate are coupled together. The PMOS FET M.sub.124 includes a gate configured to receive the high logic voltage VDDIX (e.g., 0.9V) of the LV voltage domain.

(121) With further reference to FIG. 3B, the operation of the second pull-down predriver 1100 is as follows: The control signal V.sub.NCTL_HV is in a non-boosted state (e.g., 0.9V) when the output signal V.sub.OUT is at the high and low steady-states VDDPX (e.g., 1.8V) and VSSX (e.g., 0V) or transitioning from low-to-high. When the output signal V.sub.OUT is in the aforementioned states, the pull-down gate boosting enable signal V.sub.TF_HV is in the deasserted high logic state VDDPX (e.g., 1.8V). As such, the NMOS FET M.sub.121 is turned on to output its drain voltage VSSIX (e.g., 0.9V) as the control signal V.sub.NCTL_HV. During these states, the second pull-down transition predriver 1130 is disabled because the deasserted high logic state VDDPX (e.g., 1.8V) of the pull-down gate boosting enable signal V.sub.TF_HV maintains PMOS FET M.sub.122 turned off.

(122) The control signal V.sub.NCTL_HV is in a boosted state (e.g., ˜1.4V) when the output signal V.sub.OUT is transitioning from a high logic state VDDPX (e.g., 1.8V) to a low logic state VSSX (e.g., 0V). When the output signal Vou-r is transitioning to the low logic state VSSX (e.g., 0V), the pull-down gate boosting enable signal V.sub.TF_HV is in the asserted low logic state VSSIX (e.g., 0.9V). As such, the NMOS FET M.sub.121 is turned off to disable the second steady-state pull-down predriver 1110. The pull-down gate boosting enable signal V.sub.TF_HV being in the asserted low logic state VSSIX (e.g., 0.9V) turns on PMOS FET M.sub.122 to produce a current path between VDDPX and VSSX. Thus, the diode-connected PMOS FET M.sub.123 is coupled between the upper voltage rail VDDPX and the output of the second pull-down predriver 1100; thereby generating the control signal V.sub.NCTL_HV at the boosted voltage level ˜1.4V (e.g., a diode voltage drop below VDDPX). The bottom PMOS FET M.sub.124 is configured to limit the current between VDDPX and VSSX.

(123) FIG. 12 illustrates a flow diagram of an example method 1200 of voltage level shifting an input signal to generate an output signal in accordance with another aspect of the disclosure. The method includes applying a first control signal to a gate of a first p-channel metal oxide semiconductor field effect transistor (PMOS FET) (block 1210). Examples of means for applying a first control signal to a gate of a first p-channel metal oxide semiconductor field effect transistor (PMOS FET) include any of the pull-up steady-state or transition predrivers described herein.

(124) The method 1200 further includes applying a second control signal to a gate of a second PMOS FET coupled in series with the first PMOS FET between a first voltage rail and an output, wherein the first and second control signals are at high logic voltages when an output signal at the output is at a low logic state, wherein the first and second control signals are at low logic voltages when the output signal is at a low logic state, and wherein the first and second control signals are at a first set of boosted voltages when the output signal is transitioning from the low logic state to the high logic state, respectively (block 1220). Examples of means for applying a second control signal to a gate of a second PMOS FET include any of the pull-up steady-state or transition predrivers described herein.

(125) The method 1200 additionally includes applying a third control signal to a gate of a first n-channel metal oxide semiconductor field effect transistor (NMOS FET) (block 1230). Examples of means for applying a third control signal to a gate of a first n-channel metal oxide semiconductor field effect transistor (NMOS FET) include any of the pull-down steady-state or transition predrivers described herein.

(126) Further, the method 1200 includes applying a fourth control signal to a gate of a second NMOS FET coupled in series with the first NMOS FET between the output and a second voltage rail, wherein the third and fourth control signals are at low logic voltages when the output signal is at the high logic state, wherein the third and fourth control signals are at high logic voltages when the output signal is at the low logic state, and wherein the third and fourth control signals are at a second set of boosted voltages when the output signal is transitioning from the high logic state to the low logic state, respectively (block 1240). Examples of means for applying a fourth control signal to a gate of a second NMOS FET include any of the pull-down steady-state or transition predrivers described herein.

(127) FIG. 13 illustrates a block diagram of an example wireless communication device 1300 in accordance with another aspect of the disclosure. The wireless communication device 1300 includes at least one antenna 1360 (e.g., at least one antenna array), a transceiver 1350 coupled to the at least one antenna 1360, and an integrated circuit (IC) or system on chip (SOC) 1310 coupled to the transceiver. The IC or SOC 1310, in turn, includes one or more signal processing cores 1320 and one or more input/output (I/O) circuits 1330. The one or more I/O circuit 1330 may be implemented per any of the I/O circuits described herein.

(128) Pursuant to a signal transmission application, the one or more signal processing cores 1320 may be configured to process a transmit baseband (BB) signal in a first voltage domain (e.g., a CX voltage domain). The one or more I/O circuits 1330 may be configured to upwards voltage level shift the transmit (BB) baseband signal to a second voltage domain (e.g., a PX voltage domain). The transmit baseband (BB) signal in the second voltage domain is provided to the transceiver 1350, which is configured to generate a transmit radio frequency (RF) signal based on the transmit baseband (BB) signal. The transmit RF signal is provided to the at least one antenna 1360 for wireless transmission to one or more remote wireless devices.

(129) It shall be understood that inverters and logic gates (e.g., AND, NAND, etc.) described herein can be implemented with different configurations of transistors and/or combination of logic gates. For example, an inverter can be implemented using a NAND gate.

(130) The following provides an overview of aspects of the present disclosure:

(131) Aspect 1: An apparatus, including: an output driver, including: a first p-channel metal oxide semiconductor field effect transistor (PMOS FET); a second PMOS FET coupled in series with the first PMOS FET between a first voltage rail and an output; a first n-channel metal oxide semiconductor field effect transistor (NMOS FET); and a second NMOS FET coupled in series with the first NMOS FET between the output and a second voltage rail; a first predriver coupled to gates of the first and second PMOS FETs and first and second NMOS FETs; and a second predriver coupled to the gates of the first and second PMOS FETs and first and second NMOS FETs.

(132) Aspect 2: The apparatus of aspect 1, wherein the first predriver includes a pull-up predriver coupled to the gate of the first PMOS FET.

(133) Aspect 3: The apparatus of aspect 2, wherein the pull-up predriver includes: an inverter including an input configured to receive an input signal, and an output coupled to the gate of the first PMOS FET; and a third PMOS FET coupled in series with the inverter between the first voltage rail and a third voltage rail, wherein the third PMOS FET is configured to receive a pull-up gate boosting enable signal.

(134) Aspect 4: The apparatus of any one of aspects 1-3, wherein the second predriver includes a pull-up predriver coupled to the gate of the first PMOS FET.

(135) Aspect 5: The apparatus of aspect 4, wherein the pull-up predriver includes: a third NMOS FET coupled between the first voltage rail and the gate of the first PMOS FET, wherein the third NMOS FET includes a gate configured to receive a first bias voltage; a diode-connected NMOS FET; a fourth NMOS FET including a gate configured to receive a second bias voltage; and a fifth NMOS FET coupled in series with the diode-connected NMOS FET and the fourth NMOS FET between the gate of the first PMOS FET and the second voltage rail, wherein the fifth NMOS FET includes a gate configured to receive a pull-up gate boosting enable signal.

(136) Aspect 6: The apparatus of any one of aspect 1-5, wherein the first predriver includes a pull-up predriver coupled to the gate of the second PMOS FET.

(137) Aspect 7: The apparatus of aspect 6, wherein the pull-up predriver includes a third PMOS FET including a source configured to receive a bias voltage, a gate configured to receive a pull-up gate boosting enable signal, and a drain coupled to the gate of the second PMOS FET.

(138) Aspect 8: The apparatus of any one of aspects 1-7, wherein the second predriver includes a pull-up predriver coupled to the gate of the second PMOS FET.

(139) Aspect 9: The apparatus of aspect 8, wherein the pull-up predriver includes: a third NMOS FET coupled between the first voltage rail and the gate of the second PMOS FET, wherein the third NMOS FET includes a gate configured to receive a bias voltage; a diode-connected NMOS FET; and a fourth NMOS FET coupled in series with the diode-connected NMOS FET between the gate of the second PMOS FET and the second voltage rail, wherein the fourth NMOS FET includes a gate configured to receive a pull-up gate boosting enable signal.

(140) Aspect 10: The apparatus of any one of aspects 1-9, wherein the first predriver includes a pull-down predriver coupled to the gate of the second NMOS FET.

(141) Aspect 11: The apparatus of aspect 10, wherein the pull-down predriver includes: a third NMOS FET including a gate configured to receive a pull-down gate boosting enable signal; and an inverter coupled in series with the third NMOS FET between a third voltage rail and the second voltage rail, wherein the inverter includes an input configured to receive an input signal, and an output coupled to the gate of the second NMOS FET.

(142) Aspect 12: The apparatus of any one of aspects 1-11, wherein the second predriver includes a pull-down predriver coupled to the gate of the second NMOS FET.

(143) Aspect 13: The apparatus of aspect 12, wherein the pull-down predriver includes: a third PMOS FET including a gate configured to receive a pull-down gate boosting enable signal; a fourth PMOS FET including a gate configured to receive a first bias voltage; a diode-connected PMOS FET coupled in series between the first voltage rail and the gate of the second NMOS FET; and a fourth PMOS FET including a gate configured to receive a second bias voltage.

(144) Aspect 14: The apparatus of any one of aspects 1-13, wherein the first predriver includes a pull-down predriver coupled to the gate of the first NMOS FET.

(145) Aspect 15: The apparatus of aspect 14, wherein the pull-down predriver includes a third NMOS FET including a drain configured to receive a bias voltage, a gate configured to receive a pull-down gate boosting enable signal, and a drain coupled to the gate of the first NMOS FET.

(146) Aspect 16: The apparatus of any one of aspects 1-15, wherein the second predriver includes a pull-down predriver coupled to the gate of the first NMOS FET.

(147) Aspect 17: The apparatus of aspect 16, wherein the pull-down predriver includes: a third PMOS FET including a gate configured to receive a pull-down gate boosting enable signal; a diode-connected PMOS FET coupled in series with the third PMOS FET between the first voltage rail and the gate of the first NMOS FET; and a fourth PMOS FET coupled between the gate of the first NMOS FET and the second voltage rail, wherein the fourth PMOS FET includes a gate configured to receive a bias voltage.

(148) Aspect 18: The apparatus of any one of aspects 1-17, further including a gate boost control circuit coupled to the first predriver and the second predriver.

(149) Aspect 19: The apparatus of aspect 18, wherein the gate boost control circuit includes a pull-up gate boost control circuit.

(150) Aspect 20: The apparatus of aspect 19, wherein the pull-up gate boost control circuit includes: a first multi-domain logic circuit including first and second inputs configured to receive an input signal in a first voltage domain and a complementary input signal in a second voltage domain, respectively, and a first output configured to generate a pull-up gate boosting initiating signal in the second voltage domain; a second multi-domain logic circuit including third and fourth inputs configured to receive a complementary output signal in the first voltage domain and an output signal in the second voltage domain, respectively, and a second output configured to generate a pull-up gate boosting terminating signal in the second voltage domain; and a logic gate including fifth and sixth inputs configured to receive the pull-up gate boosting initiating signal and the pull-up gate terminating signal, respectively, and a third output configured to generate a pull-up gate boosting enable signal in the second voltage domain, wherein the third output is coupled to the first predriver and the second predriver.

(151) Aspect 21: The apparatus of aspect 20, wherein the first multi-domain logic circuit includes: a third NMOS FET including a gate configured to receive the input signal; and an inverter coupled in series with the third NMOS FET between a third voltage rail and the second voltage rail, wherein the inverter includes an input configured to receive the complementary input signal, and an output configured to produce the pull-up gate boosting initiating signal.

(152) Aspect 22: The apparatus of aspect 20 or 21, wherein the second multi-domain logic circuit includes: a third NMOS FET including a gate configured to receive the complementary output signal; and an inverter coupled in series with the third NMOS FET between a third voltage rail and the second voltage rail, wherein the inverter includes an input configured to receive the input signal, and an output configured to produce the pull-up gate boosting terminating signal.

(153) Aspect 23: The apparatus of any one of aspects 18-22, wherein the gate boost control circuit includes a pull-down gate boost control circuit.

(154) Aspect 24: The apparatus of aspect 23, wherein the pull-down gate boost control circuit includes: a first multi-domain logic circuit including first and second inputs configured to receive an input signal in a first voltage domain and a complementary input signal in a second voltage domain, respectively, and a first output configured to generate a pull-down gate boosting initiating signal in the first voltage domain; a second multi-domain logic circuit including third and fourth inputs configured to receive a complementary output signal in the first voltage domain and an output signal in the second voltage domain, respectively, and a second output configured to generate a pull-down gate boosting terminating signal in the first voltage domain; and a logic gate including fifth and sixth inputs configured to receive the pull-down gate boosting initiating signal and the pull-down gate terminating signal, respectively, and a third output configured to generate a pull-down gate boosting enable signal in the first voltage domain, wherein the third output is coupled to the first predriver and the second predriver.

(155) Aspect 25: The apparatus of aspect 24, wherein the first multi-domain logic circuit includes: an inverter including an input configured to receive the input signal and an output configured to generate the pull-down gate boosting initiating signal; and a third PMOS FET coupled in series with the inverter between the first voltage rail and a third voltage rail, wherein the third PMOS FET includes a gate configured to receive the complementary input signal.

(156) Aspect 26: The apparatus of aspect 24 or 25, wherein the second multi-domain logic circuit includes: an inverter including an input configured to receive the complementary output signal and an output configured to generate the pull-down gate boosting terminating signal; and a third PMOS FET coupled in series with the inverter between the first voltage rail and a third voltage rail, wherein the third PMOS FET includes a gate configured to receive the output signal.

(157) Aspect 27: A method, including: applying a first control signal to a gate of a first p-channel metal oxide semiconductor field effect transistor (PMOS FET); applying a second control signal to a gate of a second PMOS FET coupled in series with the first PMOS FET between a first voltage rail and an output, wherein the first and second control signals are at high logic voltages when an output signal at the output is at a low logic state, wherein the first and second control signals are at low logic voltages when the output signal is at a high logic state, and wherein the first and second control signals are at a first set of boosted voltages when the output signal is transitioning from the low logic state to the high logic state, respectively; applying a third control signal to a gate of a first n-channel metal oxide semiconductor field effect transistor (NMOS FET); and applying a fourth control signal to a gate of a second NMOS FET coupled in series with the first NMOS FET between the output and a second voltage rail, wherein the third and fourth control signals are at low logic voltages when the output signal is at the high logic state, wherein the third and fourth control signals are at high logic voltages when the output signal is at the low logic state, and wherein the third and fourth control signals are at a second set of boosted voltages when the output signal is transitioning from the high logic state to the low logic state, respectively.

(158) Aspect 28: The method of aspect 27, further including: initiating the first and second sets of boosted voltages based on an input signal; and terminating the first and second sets of boosted voltages based on the output signal.

(159) Aspect 29: An apparatus, including: means for applying a first control signal to a gate of a first p-channel metal oxide semiconductor field effect transistor (PMOS FET); means for applying a second control signal to a gate of a second PMOS FET coupled in series with the first PMOS FET between a first voltage rail and an output, wherein the first and second control signals are at high logic voltages when an output signal at the output is at a low logic state, wherein the first and second control signals are at low logic voltages when the output signal is at a high logic state, and wherein the first and second control signals are at a first set of boosted voltages when the output signal is transitioning from the low logic state to the high logic state, respectively; means for applying a third control signal to a gate of a first n-channel metal oxide semiconductor field effect transistor (NMOS FET); and means for applying a fourth control signal to a gate of a second NMOS FET coupled in series with the first NMOS FET between the output and a second voltage rail, wherein the third and fourth control signals are at low logic voltages when the output signal is at the high logic state, wherein the third and fourth control signals are at high logic voltages when the output signal is at the low logic state, and wherein the third and fourth control signals are at a second set of boosted voltages when the output signal is transitioning from the high logic state to the low logic state, respectively.

(160) Aspect 30: A wireless communication device, including: at least one antenna; a transceiver coupled to the at least one antenna; and an integrated circuit (IC) including one or more input/output (I/O) circuits, wherein at least one of the one or more I/O circuits includes: an output driver, including: a first p-channel metal oxide semiconductor field effect transistor (PMOS FET); a second PMOS FET coupled in series with the first PMOS FET between an upper voltage rail and an output; a first n-channel metal oxide semiconductor field effect transistor (NMOS FET); and a second NMOS FET coupled in series with the first NMOS FET between the output and a lower voltage rail; a first predriver coupled to gates of the first and second PMOS FETs and first and second NMOS FETs; and a second predriver coupled to the gates of the first and second PMOS FETs and first and second NMOS FETs.

(161) The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.