Method and apparatus for SOC with optimal RSMA

Abstract

A method for determining redundancy usage rate from a group of memory parameters and a memory yield of a System on a Chip (SoC), using the probabilistic redundancy usage rate and using that rate to calculate an optimal RSMA size. An SoC is then fabricated with the optimal RSMA size.

Claims

1. A method for making a system on a chip (SoC) having a repair signature memory area (RSMA), the method comprising: calculating a redundancy usage rate from plurality of memory parameters and a memory yield; using the redundancy usage rate to calculate an optimal RSMA size; and configuring an RSMA within the SoC with the optimal RSMA size; wherein the memory parameters include at least one of the following: number of columns; number of redundancy groups; and the number of elements per redundancy group and wherein using the redundancy usage rate includes using the following formula:
efuse_size=.sub.i=1.sup.Mu.sub.i*F to calculate the optimal RSMA size, wherein efuse_size is the optimal RSMA size; M is the number of memories in a redundancy group; u.sub.i is a redundancy usage rate calculated for an i-th memory within the redundancy group; F is the number of RSMA bits needed to repair one defect within a memory main array within the SoC.

2. A method for making a system on a chip (SoC) having a repair signature memory area (RSMA), the method comprising: calculating a redundancy usage rate from plurality of memory parameters and a memory yield; using the redundancy usage rate to calculate an optimal RSMA size; and configuring an RSMA within the SoC with the optimal RSMA size; wherein the memory parameters include at least one of the following: number of columns; number of redundancy groups; and the number of elements per redundancy group and wherein the memory yield is determined from the following equation: $y=\sqrt[n]{e^{-{\mathrm{ad}}_0}}.$

3. A method for making a system on a chip (SoC) having a repair signature memory area (RSMA), the method comprising: calculating a redundancy usage rate from plurality of memory parameters and a memory yield; using the redundancy usage rate to calculate an optimal RSMA size; and configuring an RSMA within the SoC with the optimal RSMA size; wherein the memory parameters include at least one of the following: number of columns; number of redundancy groups; and the number of elements per redundancy group and wherein the redundancy usage rate is calculated according to the following Equation: $u=\underset{q=1}{\overset{n}{.Math.}}\left(\left(\begin{array}{c}n\\ q\end{array}\right){y^{\left(n-q\right)}\left(1-y\right)}^q\underset{k=1}{\overset{\min \left(c,\left[\frac{n}{l}\right],q\right)}{.Math.}}\left(k\frac{\begin{array}{c}\left(\begin{array}{c}n-\mathrm{kl}+k\\ k\end{array}\right)\left(\begin{array}{c}k\left(l-1\right)\\ q-k\end{array}\right)+\\ \underset{i=1}{\overset{l-1}{.Math.}}\left(\begin{array}{c}n-\left(k-1\right)l+k-1-i\\ k-1\end{array}\right)\left(\begin{array}{c}k\left(l-1\right)-l+i\\ q-k\end{array}\right)\end{array}}{\left(\begin{array}{c}n\\ q\end{array}\right)}\right)\right)$ wherein: n is the number of columns in memory as stored in memory parameters source; c is the number of redundancy groups in memory as stored in memory parameters source; I is the number of elements per redundancy group as stored in memory parameters source; and y is the memory yield of one column in memory as stored in memory defect density source.

4. The method of claim 3, wherein the y is determined from the following equation: $y=\sqrt[n]{e^{-{\mathrm{ad}}_0}}$ wherein n is the number of columns in a memory main array; and e is the base of the natural log.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) The disclosed method and apparatus, in accordance with one or more various embodiments, is described with reference to the following figures. The drawings are provided for purposes of illustration only and merely depict examples of some embodiments of the disclosed method and apparatus. They should not be considered to limit the breadth, scope, or applicability of the claimed invention. For clarity and ease of illustration, these drawings may not be to scale.

(2) In order to easily identify the figure in which a particular element resides, the digit or digits preceding the two least significant digits in a reference number refer to the figure number in which that element is first introduced. For example, module 601, the digit 6 precedes the two least significant digits 01. Therefore, the module 601 first appears in FIG. 6.

(3) FIG. 1 illustrates a configuration of SoC modules in accordance with one embodiment of the disclosed method and apparatus.

(4) FIG. 2 shows a memory structure with Column Redundant Groups.

(5) FIG. 3 shows a memory structure with Row Redundant Groups.

(6) FIG. 4 is an illustration of a memory main array with a failed memory element in the second row of the third column within the memory main array.

(7) FIG. 5 illustrates a system 500 that can be used to design a System on a Chip (SoC) in accordance with some embodiments of a disclosed method and apparatus.

(8) FIG. 6 is a simplified block diagram of an SoC.

(9) FIG. 7 is a memory repair process in accordance with one embodiment of the disclosed method and apparatus.

(10) FIG. 8 is a flowchart for using Formula 1 to calculate a redundancy usage rate for one memory (either for row or column redundant elements) based on an expected value of a random variable in accordance with one embodiment of the disclosed method and apparatus.

(11) FIG. 9 is a flowchart for using Formula 2 to calculate an optimal RSMA size in accordance with one embodiment of the disclosed method and apparatus.

(12) It should be understood that the disclosed method and apparatus can be practiced with modification and alteration, and that the invention should be limited only by the claims and the equivalents thereof.

DETAILED DESCRIPTION

(13) FIG. 5 illustrates a system 500 that can be used to design a System on a Chip (SoC) in accordance with some embodiments of a disclosed method and apparatus. The system 500 comprises a SoC design architecture module 501, a probability engine 502, a memory parameter source 508, and a memory defect density source 514. The probability engine 502 comprises a usage rate calculator 510, and an RSMA sizer 512. The SoC design architecture module 501 is a module that uses a set of parameters that can be used to fabricate an SoC having desired specifications.

(14) FIG. 6 is a simplified block diagram of such an SoC 600. The parameters include the size of optimized RSMAs 606 fabricated in at least one module 601 of the SoC 600 as determined by the RSMA sizer 512 within the probability engine 502. In some embodiments, the RSMA is a section of non-volatile memory. In other embodiments, the RSMA can be located in any type of memory that allows repair signatures to be stored.

(15) The usage rate calculator 510 determines a redundancy usage rate based on information provided by the memory parameter source 508 and the memory defect density source 514. In some embodiments, the memory parameter source 508 provides information regarding memory main arrays 604 comprising memory elements 201 within the SoC 600, such as the number of words stored in each memory main array 604, number of bits per word within the memory main array 604, number of redundant elements within the memory main array 604, etc. The memory defect density source 514 provides information based on data provided by the foundry in which the memories 604 of the SoC 600 will be fabricated or historical data regarding the number of failures that have occurred in memories made under similar conditions. In accordance with some embodiments of the disclosed method and apparatus, one or more of the memories 604 within modules 601, 602 of the SoC 600 are organized as shown in FIG. 2, FIG. 3 or FIG. 4 and discussed above.

(16) This information is used to determine the likelihood that any particular memory element 201 will be defective. The usage rate calculator 510 uses a first formula to calculate a memory redundancy usage rate from the information provided by the two sources 508, 514. The RSMA sizer 512 uses a second formula to calculate an optimal size and number of RSMAs 606 to be fabricated within one or more modules 601 of the SoC 600 based on the redundancy usage rate calculated by the usage rate calculator 510. The output from the RSMA sizer 512 is then used to design an SoC architecture 501. More particularly, the output of the probability engine 502 is provided as input to an SoC design architecture 501. The SoC design architecture 501 uses the input from the probability engine 502 to determine the size of optimal RSMAs 606 for a particular SoC design associated with the information provided to the probability engine 502. Further details regarding the operation of the probability engine 502 are provided below.

(17) The module 601 comprises a server 603. The server 603 comprises a repair engine 607. In some embodiments, the server is coupled to each of a plurality of Built-In-Self-Test units (BISTs) 605 within one or more modules 602 of the SoC 600. The BISTs 605 each are coupled to one or more associated memories 604. The server 603 communicates with the BISTs 605 to coordinate self-tests of the associated memories 604. If faults are detected by the BISTs 605, the location of the faults is communicated to the server 603 and stored in an appropriate RSMA 606. The repair engine 607 can then access the information from the RSMAs 606 and make repairs to the memory 604 by making substitutions of redundant memory groups for those memory elements indicated by the RSMA 606 to be faulty. In some alternative embodiments, the repair engine 607 can be directly coupled to the memory main arrays 604 within each of the modules 602. In such a case, the server coordinates and controls the operation of testing the memory main arrays for faults and substituting redundancy groups for failed memory elements 401 in the memory main arrays 604.

(18) FIG. 7 is a flowchart illustrating a memory repair process 700. Initially, a redundancy usage rate is calculated from a plurality of memory parameters and from memory yield (block 702). The memory repair process 700 uses the probabilistic redundancy usage rate to calculate an optimal RSMA size (block 704). The SoC design architecture 501 is provided with an optimal RSMA size (block 706).

(19) The first formula, which is used to calculate a memory redundancy usage rate from the information provided by the two sources, is:

(20) $\begin{array}{cc}u=\underset{q=1}{\overset{n}{.Math.}}\left(\left(\begin{array}{c}n\\ q\end{array}\right){y^{\left(n-q\right)}\left(1-y\right)}^q\underset{k=1}{\overset{\min \left(c,\left[\frac{n}{l}\right],q\right)}{.Math.}}\left(k\frac{\begin{array}{c}\left(\begin{array}{c}n-\mathrm{kl}+k\\ k\end{array}\right)\left(\begin{array}{c}k\left(l-1\right)\\ q-k\end{array}\right)+\\ \underset{i=1}{\overset{l-1}{.Math.}}\left(\begin{array}{c}n-\left(k-1\right)l+k-1-i\\ k-1\end{array}\right)\left(\begin{array}{c}k\left(l-1\right)-l+i\\ q-k\end{array}\right)\end{array}}{\left(\begin{array}{c}n\\ q\end{array}\right)}\right)\right)& \mathrm{EQ}.1\end{array}$

(21) The formula is based on expected value of a random variable, wherein:

(22) n is the number of columns in memory (as stored in memory parameters source 508);

(23) c is the number of redundancy groups in memory (as stored in memory parameters source 508);

(24) I is the number of elements per redundancy group (as stored in memory parameters source 508); and

(25) y is the memory yield of one column in memory (as stored in memory defect density source 514).

(26) The value of y can be calculated either by the memory defect density source 514 or by an external device and stored within the memory defect density source 514. The value can be determined using well-known formulas based on memory die area and memory defect density (d.sub.0), e. g. according to Poisson model:

(27) $\begin{array}{cc}y=\sqrt[n]{e^{-{\mathrm{ad}}_0}}& \mathrm{EQ}.2\end{array}$

(28) wherein n is the number of columns in memory and e is the base of the natural log.

(29) The second formula, which is used by the probability engine 502 to calculate an optimal size for the RSMA 606 used with a group of M memories, is:
efus_size=.sub.i=1.sup.Mu.sub.i*FEQ. 3

(30) wherein:

(31) efuse_size is the number of bits required for the RSMA;

(32) M is the number of memories in the group;

(33) u.sub.i is the redundancy usage rate of i-th memory; and

(34) F is the number of RSMA bits needed for one redundancy, calculation of F is simple and straightforward, as well as it depends on implementation.

Example 1

(35) TABLE-US-00001 TABLE 1 Memory defect density Project # (1/cm.sup.2) Redundancy Usage Rate (%) Project 1 0.055 0.15363% Project 2 0.0279 0.078% Project 3 0.0171 0.048%

(36) Table 1 shows the result of calculations performed to determine the memory redundancy usage rate for SoC designs for three different projects. If another project was implemented at a later time, for which only 10 out of 20,000 memory instances required repair (i.e., redundancy usage rate of 0.05%), the RSMA would have approximately the same order of magnitude as project 3 based on the above disclosed formulas.

Example 2

(37) For a fifth project in which the RSMA 606 is fabricated as 32 bit32 bit sections of non-volatile memory, and in which the SoC design includes 5 modules, the chip area savings using an optimal RSMA size based on the above proposed formulas can be calculated as follows:

(38) If 100% redundancy usage rate is assumed, the number of RSMA bits is calculated to be 4519; then, 5 sections of non-volatile memory of 32 bits32 bits (1024 bits) would be needed to fabricate an RSMA large enough to store the necessary information. This would require a chip total area of 4200422.649 um.sup.2 if using 16 nm technology node.

(39) Alternatively, by implementing the disclosed method to determine an optimal RSMA size, the number of bits that the RSMA needs to be able to store can be reduced to less than 71 RSMA bits, taking into account the memory yield for the memory at issue. Therefore, only one 3232 (1024 bits) section of non-volatile memory is needed to implement an RSMA that can support the calculated usage rate. If smaller sections of non-volatile memory are used to fabricate the RSMA, such as sections of 16 bits8 bits (128 bits), then the required 71 bits would fit within an even smaller area. Accordingly, the chip total area can be reduced to 4007924.697 um.sup.2, even with non-volatile memory sections of 32 bits32 bits; resulting in a saving of approximately 4.58% in area. Using smaller sections of non-volatile memory to fabricate the RSMA 606 can reduce the chip total area, making the saving even greater than 4.58%.

(40) FIG. 8 is a flowchart for using Formula 1 to calculate a redundancy usage rate for one memory (using either for row or column redundant elements). The usage rate calculator 510 receives the number of memory rows (when memory has row redundant elements) or memory columns (when memory has column redundant elements) (block 801). In addition, the usage rate calculator 510 receives the number of redundancy groups in memory (block 803). The usage rate calculator 510 also receives the number of redundant elements per redundancy group (block 805) and the memory yield of one memory row (when memory has row redundant elements) or one memory column (when memory has column redundant elements) (block 807). The usage rate calculator 510 then uses these received values to calculate the redundancy usage rate for one memory (block 809).

(41) FIG. 9 is a flowchart illustrating the use of Formula 2 to calculate an optimal RSMA size. Initially, a variable for holding an accumulated redundancy usage rate (referred to herein as ARUR) is set to zero (block 901). Next, the number of RSMA bits needed for one redundant element is received from the memory parameters source 508 (block 903). Alternatively, the source of the number of RSMA bits could something other than the memory parameters source 508. Next, calculations regarding the first memory 604 is selected (block 905). The redundancy usage rate is calculated for this first memory using the first formula (as illustrated in FIG. 8) (block 907). In one embodiment, the number of RSMA bits required for such a calculated usage rate is determined (i.e., the usage rate is multiplied by the number of bits required for one repair) and stored in the ARUR variable (block 909). Alternatively, the usage rate itself is stored in the ARUR. Either way, a determination is made as to whether the usage rate has been determined for all of the memories 604 (block 911). If not, then the usage rate for the next memory 604 is determined in block 907. Blocks 905 through 911 are repeated until usage rates have been accumulated in the ARUR for all of the memory blocks in the SoC 600, at which time the value of the ARUR is either equal to the total number of bits required in the RSMA or the total usage rate for all of the memories 604, which can then be multiplied by the number of bits for one repair (block 913).