Semiconductor Featuring Ridged Architecture

Abstract

A semiconductor, such as crystallized silicon or germanium, features top-mounted ridges. Circuits are capable of being integrated onto the ridges using modified photolithographic processes. The ridged architecture increases the usable surface area per given footprint of semiconductors. Specifically, if the preferred embodiment is adopted, the ridges increase relative surface area by 41.42%. Such an increase in surface area has numerous advantages. One advantage is that microchip footprints can be 29.29% smaller, allowing 1.41 times more microchips to be produced per wafer. Another advantage is that solar panels can contain 1.41 times more electron-shuttling junctions, thereby increasing overall sunlight harnessing, electrical conversion, and panel efficiency by 41.42%.

Claims

1. An electronic device, said device comprising: an element or compound having semiconducting capabilities; and means for increasing the circuit-mountable area per given footprint of said semiconducting element or compound.

2. A semiconductor, said semiconductor comprising: two or more ridges, wherein said ridges are situated atop the semiconductor; wherein said ridges are capable of carrying circuits; and wherein said ridges increase the usable surface area per given footprint of the semiconductor.

3. The semiconductor of claim 2, wherein said semiconductor is constructed of crystallized silicon.

4. The semiconductor of claim 2, wherein said semiconductor is constructed of crystallized germanium.

5. The semiconductor of claim 2, wherein said ridges have side geometries of an isosceles right triangle.

6. The semiconductor of claim 2, wherein said ridges have hypotenuses measuring one millimeter or less.

7. The semiconductor of claim 2, wherein said ridges have hypotenuses measuring one micron or less.

8. The semiconductor of claim 2, wherein said ridges are composed of individual semiconducting crystals.

9. The semiconductor of claim 2, wherein said semiconductor is polycrystalline in nature.

10. The semiconductor of claim 2, wherein said semiconductor contains logic circuits.

11. The semiconductor of claim 2, wherein said semiconductor contains memory circuits.

12. The semiconductor of claim 2, wherein said semiconductor contains photovoltaic circuits.

13. A method for increasing the number of electronic circuits containable on semiconducting material, said method comprising the following steps: creating circuit-mountable ridges atop said semiconducting material; and subjecting said ridges to one or more photolithographic processes.

14. A method for increasing electrical output per given footprint of a photovoltaic cell, said method comprising the following steps: creating multiple ridges atop said photovoltaic cell to increase circuit-mountable surface area; and creating electron-shuttling junctions on the surfaces of said ridges.

15. A method for forming integrated circuits on ridged surfaces of a semiconductor, said method comprising the following steps: treating the ridged surfaces in preparation for applying circuit-creating photolithographic processes; screening the ridged surfaces using masking means; situating said masking means parallel with the surfaces of common-facing ridges; and passing radiation perpendicularly through said masking means to selectively expose the surfaces of common-facing ridges according to the circuit layout of the masking means.

16. A photolithographic system, said photolithographic system comprising: one or more radiation emitters; an element or compound having semiconducting capabilities, said element or compound featuring ridged surfaces; and masking means for selectively exposing said ridged surfaces to radiation.

17. The photolithographic system of claim 16, wherein said masking means comprises an angled unitary mask assigned to the surfaces of multiple common-facing ridges.

18. The photolithographic system of claim 16, wherein said masking means comprises multiple sectional masks situated parallel with the surfaces of common-facing ridges.

19. The photolithographic system of claim 18, wherein said sectional masks are positioned at substantially uniform distances from the surfaces of common-facing ridges.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Eighteen drawings are supplied. Four drawings depict prior art and are supplied for context purposes. The remaining drawings inclusively illustrate various aspects of the invention in connection with the preferred embodiments and best modes of implementation. Those drawings, as such, are intended to complement the disclosure without limitation.

[0029] FIG. 1 (Prior Art), FIG. 2 (Prior Art), and FIG. 3 (Prior Art) depict, in perspective and side views, an ordinary semiconducting wafer and an ordinary microchip.

[0030] FIG. 4 and FIG. 5 depict, in perspective and overhead views, the ridged semiconducting wafer as invented.

[0031] FIG. 6, FIG. 7, and FIG. 8 depict, in perspective, overhead, and side views, the ridged microchip as invented.

[0032] FIG. 9 and FIG. 10 depict, in perspective and side views, an individual ridge under the preferred embodiment.

[0033] FIG. 11 (Prior Art) depicts, in side view, the photolithographic process applicable to ordinary wafers.

[0034] FIG. 12, FIG. 13, FIG. 14, and FIG. 15 depict, in side view, modifications to the ordinary photolithographic process stemming from the ridged architecture of the invention.

[0035] FIG. 16 and FIG. 17 depict, in perspective view (as illustrated from the perspective of radiation travel during the photolithographic process), the ridged wafer as invented.

[0036] FIG. 18 depicts, in side view, an additional photolithographic process applicable to ridged wafers.

[0037] Included within the foregoing drawings are various elements, namely, planar surface 1, ridge surfaces 1a and 1b, ridge base 1c, ridge peak 2, ridge valley 3, planar mask 4, angled sectional masks 4a and 4b, and radiation beam 5.

[0038] The foregoing drawings and elements are thoroughly and comprehensively discussed in the below disclosure.

DETAILED DESCRIPTION OF THE INVENTION

[0039] The invention, as noted above, is directed at increasing the usable surface area per given footprint of semiconductors. The invention accomplishes that objective via top-mounted ridges upon which circuits can be mounted. Because the ridges increase relative surface area, the invention, in essence, decouples the perceived unbreakable correspondence between fixed footprint and fixed usable surface area.

[0040] A detailed description is provided concerning ridge placement, ridge geometry, ridge utilization, and ridge ramifications. Also discussed are various modes for implementing and practicing the invention as claimed herein.

[0041] Before addressing the foregoing subjects, however, current wafer and microchip technology must be briefly discussed. That discussion will enable the invention to be fully delineated, contrasted, compared, and understood.

[0042] FIG. 1 (Prior Art) depicts an ordinary semiconducting wafer. FIG. 2 (Prior Art) and FIG. 3 (Prior Art) depict an ordinary microchip. FIG. 1 (Prior Art) and FIG. 2 (Prior Art) show the perspective view of the wafer and microchip, respectively, while FIG. 3 (Prior Art) shows the side view of the microchip in two-dimensional format.

[0043] As discussed previously, and as shown in FIG. 1 (Prior Art), FIG. 2 (Prior Art), and FIG. 3 (Prior Art), ordinary wafers and microchips have planar top faces. Those planar top faces are represented as surface 1 in the aforementioned prior-art illustrations. As shown therein, surface 1 (which is circuit-mountable) is substantially flat, featuring no raised or angled elements whatsoever.

[0044] The invention modifies, and improves upon, prior art through architectural and other innovations. First and foremost, the invention encompasses top-mounted ridges. Those ridges are composed of semiconducting material (crystallized silicon or germanium, for example). The ridges have conductive and insulative properties and, accordingly, serve as the substrate upon which integrated circuits can be formed.

[0045] The circuit-mountable ridged architecture at issue is depicted in the next series of drawings, namely, FIGS. 4 through 8. In particular, FIG. 4 and FIG. 5 depict (in perspective and overhead views, respectively) the ridged semiconducting wafer as invented. FIG. 6, FIG. 7, and FIG. 8 depict (in perspective, overhead, and side views, respectively) the ridged microchip as invented. As shown in the aforementioned illustrations, the wafer and microchip feature top-mounted ridges. The ridges comprise five elements. Such elements consist of surface 1a, surface 1b, surface/base 1c (not visible in FIG. 5 and FIG. 7), peak 2, and valley 3.

[0046] Delving more deeply, FIG. 9 depicts an individual ridge. It can be seen that the ridge is prism-shaped, as all sides of the ridge are parallel and terminate identically. A triangular shape, in turn, outlines the side of the ridge.

[0047] FIG. 10 depicts the ridge from the previous illustration. In contrast to FIG. 9, however, FIG. 10 depicts the ridge from its side, making the view two-dimensional. Also, in contrast to FIG. 9, FIG. 10 features generally accepted geometric indicators. Those indicators consist of an angle symbol, hash lines, leg and hypotenuse labels, and other markings. The side-viewed triangular geometry represented in FIG. 10 constitutes the preferred ridge embodiment.

[0048] Applying geometric principles to the indicators in FIG. 10, it can be discerned that the inside angle of surfaces 1a and 1b is 90 degrees. It can also be discerned that the inside angles of surfaces 1a and 1c and surfaces 1b and 1c are identical, namely, 45 degrees. The ridge, as such, features side dimensions of an isosceles right triangle, as the ridge has one right angle and two equal-length (and equal-angled) legs.

[0049] In terms of function and use, surfaces 1a and 1b (as shown in FIGS. 4 through 10, among others) constitute working surfaces. Surfaces 1a and 1b, in other words, are circuit-mountable semiconducting substrates. On the other hand, surface 1c (not shown in FIG. 5 and FIG. 7) functions as the base of the wafer and microchip. Consequently, unlike surfaces 1a and 1b, surface/base 1c is nonworking in nature.

[0050] A key aspect of the invention is an increase in the usable surface area per given footprint of semiconductors. The ridged architecture, as invented, described, and claimed, accomplishes such intended surface-area increases.

[0051] To calculate the precise surface-area increase resulting from the preferred embodiment of the invention, trigonometric principles must first be applied. As geometrically depicted in FIG. 10, surfaces 1a and 1b serve as the legs of the triangular ridge, while surface 1c serves as the hypotenuse thereof. With knowledge of the inner angles of the triangular ridge (45, 90, and 45 degrees), hypotenuse ratios can be calculated via trigonometry. It can be determined, in particular, that the hypotenuse ratio of the hypotenuse (surface 1c) is 1.000. It can further be determined that the hypotenuse ratio of each leg (surface 1a and surface 1b) is 0.7071. All such ratios are denoted parenthetically in FIG. 10.

[0052] Arithmetic now comes into play to calculate the exact surface-area increase. The combined hypotenuse ratios of surface 1a (0.7071) and surface 1b (0.7071) is 1.4142. That value signifies that surfaces 1a and 1b, collectively, are 1.4142 times longer than surface 1c. It follows, mathematically, that the ridged architecture, as structured, increases surface area by 41.42% relative to surface 1c.

[0053] At this point, it must be mentioned that the ridges may feature side geometries other than isosceles right triangles. Any triangular shape is technically possible. A change in ridge angle, however, will alter the hypotenuse ratios and thereby alter surface-area increases. A change in ridge angle will also impact the photolithographic process, as will be discussed shortly. It is therefore suggested that the ridges feature the angles and side geometries proposed.

[0054] It bears mentioning, as well, that the ridges in the accompanying illustrations are not drawn to scale in relation to the wafer or microchip. The size of the ridges in those drawings has been exaggerated solely to promote comprehensibility. Unlike the scenario depicted, the ridges are intended to be sized at the millimeter or micron scale.

[0055] By way of example, ridges can be manufactured with one-millimeter hypotenuses, in which event standard wafers (which measure 30 centimeters in diameter) will contain 300 ridges. Ridges can also be manufactured with one-micron hypotenuses, in which event standard wafers will contain 300,000 ridges. Any other ridge size can be employed, including ridge sizes falling outside the millimeter or micron scales. Precise sizing decisions, of course, belong to the manufacturer.

[0056] Regardless of the ridge size employed, the percentage of surface-area increase (namely, 41.42%) will remain. This is because increases in surface area are governed by ridge geometry, not ridge size. Thus, identical ridge angles will produce identical hypotenuse ratios and surface-area increases, regardless of the ridge size employed.

[0057] With that said, it should not be concluded that ridge size is irrelevant or inconsequential. Larger ridges will have greater volumes, requiring use of more semiconducting material. The opposite is true for smaller ridges, although the reduced-volume benefits of smaller ridges may be offset by increased implementation difficulties. These considerations, among others, should be weighed by the manufacturer in choosing whether to employ millimeter-scale or micron-scale ridges.

[0058] Once ridge geometry and size are chosen, the semiconducting wafer must be contoured accordingly. Methods of ridge creation may differ depending on ridge measurement. Where millimeter-scale ridges are employed, mechanical slicing or grinding of the wafer surface is possible. Where micron-scale ridges are employed, laser cutting/vaporization may be necessary. Other contouring methods can be utilized, whether such methods are additive or subtractive in nature.

[0059] Where necessary or feasible, ridges can also be constructed using separate crystallized semiconductors. That is, individual ridges may be composed of individual crystals, making the ridged semiconductor polycrystalline. If individual ridge crystals are employed, those crystals need not share adjoining grain boundaries. The individual crystals, instead, may be interfaced superficially (without molecular bonding), thereby preventing grain boundaries from changing the electrical and semiconducting properties of individual crystals.

[0060] In short, numerous ridge embodiments exist, giving manufacturers numerous options for creating the ridged architecture as invented. Different ridge embodiments may, of course, require different ridge-creation processes. It is the prerogative of the manufacturer to choose accordingly.

[0061] During the ridge-forming process, caution should be exercised to avoid damaging the crystalline structure of the semiconductor. Semiconducting substances such as silicon are crystallized to form specially arranged atomic bonds. The crystalline structure enables conduction and insulation, defining the character of the semiconductor. Crystal damage will therefore impact functionality and performance.

[0062] Where the crystalline structure of the semiconductor is damaged during the ridge-forming process, compensatory doping may be performed. It is known that certain structural defects in crystals produce the same effect as valence-differing donor or acceptor impurities. It is therefore possible to counteract physical crystal damage via selective doping. To induce negative charges to the semiconductor, manufacturers can employ donor impurities (such as arsenic, antimony, or phosphorus). To induce positive charges to the semiconductor, manufacturers can employ acceptor impurities (such as aluminum, boron, indium, or gallium). This process of compensatory doping allows manufacturers to counteract crystal damage sustained during the ridge-creation process.

[0063] Whether performed for compensatory or routine purposes, all post-crystallization doping can be achieved using existing techniques. The wafer-doping process, at present, is administered directly overhead. Specifically, dopants are introduced perpendicular to the wafer base via ion implantation or, for deeper penetration, ion beam mixing. That overhead bombardment procedure remains technologically viable. However, because post-crystallization doping will now be applied to angled surfaces, doping targets may need to be modified. A modification will be necessary where the doping is performed for circuit-embedding purposes, in which event doping regions must be narrowed (by 29.29% under the preferred ridge embodiment) to account for the greater area and increased number of circuits along the elongated portion of the ridge surfaces.

[0064] Once ridges are created and conditioned, integrated circuits must be formed onto their surfaces. The photolithographic process is used for that purpose. Given the ridged architecture, however, certain modifications to the normal photolithographic process will be necessary.

[0065] For reference purposes, FIG. 11 (Prior Art) depicts photolithographic procedures applicable to ordinary planar wafers. In that drawing, mask 4 is laterally positioned over surface 1, which represents the circuit-mountable portion of the planar wafer. The planar wafer is coated with photoresistive material. A photon or electron emitter (not shown) discharges radiation beam 5. Beam 5 passes through mask 4, thereby exposing surface 1 according to the layout of mask 4.

[0066] FIG. 12 and FIG. 13 depict one variation of the photolithographic process. As shown in FIG. 12, mask 4 is tilted until level with surface 1a. Radiation beam 5 passes through mask 4, exposing surface 1a. Because surface 1b is parallel with beam 5, surface 1b is shielded from exposure, thereby protecting surface 1b from beam 5. A similar scenario is depicted in FIG. 13, except that surface 1b is exposed to beam 5 while surface 1a is shielded from exposure.

[0067] FIG. 14 and FIG. 15 depict another variation of the photolithographic process. As shown in the respective drawings, mask 4a and mask 4b are divided by the number of ridges, with each subdivision being individually tilted. Mask 4a (shown in FIG. 14) is level with surface 1a, while mask 4b (shown in FIG. 15) is level with surface 1b. Unlike the prior embodiment, this embodiment has the advantage of allowing the mask to be positioned at uniform distances from surfaces 1a and 1b.

[0068] FIG. 16 and FIG. 17 further illustrate the modified photolithographic process. Each drawing depicts one circular wafer featuring five ridges. The five-ridge wafer is depicted from the perspective of the radiation beam (not shown). FIG. 16 corresponds with the photolithographic angle employed in FIGS. 12 and 14, while FIG. 17 corresponds with the photolithographic angle employed in FIGS. 13 and 15. Interpreting FIG. 16 and FIG. 17 in that context, it can be seen that surfaces 1a and 1b are either exposed or hidden, depending on the angle of the radiation beam. Specifically, because the undepicted beam in FIG. 16 is angled perpendicularly with surface 1a, only surface 1a is visible in that drawing (meaning that surface 1b is shielded). Conversely, because the undepicted beam in FIG. 17 is angled perpendicularly with surface 1b, only surface 1b is visible in that drawing (meaning that surface 1a is shielded).

[0069] At this point, the photolithographic advantages of the preferred ridge geometries should become evident. The ridges, as embodied and illustrated above, have side geometries of an isosceles right triangle. That shape orients the ridge surfaces at 90-degree angles. Given those adjacent right angles, surfaces 1a and 1b can be completely exposed or hidden, thereby streamlining the photolithographic process.

[0070] For the sake of completeness, it must be mentioned that another photolithographic step may be necessary in addition to the angled versions shown in FIGS. 12 through 15. The potential extra step stems from the ridged architecture, which features sharp-angled peaks and valleys. Circuits must be formed on those peaks and valleys to join the adjacent working surfaces. Specifically, referring to FIG. 18, peak 2 must connect with surface 1a and surface 1b, while valley 3 must connect with surface 1b and surface 1a. Any lack of connection between surface 1a and surface 1b will break the electrical continuum, preventing circuit interoperability.

[0071] FIG. 18 depicts the photolithographic process for creating joining circuits on the peaks and valleys. As shown in that drawing, mask 4 is parallel with the ridged wafer. Beam 5 passes through mask 4. Mask 4 is configured to prevent exposure of surface 1a and surface 1b. Mask 4 is also configured with the circuit layout of peak 2 and valley 3, allowing radiation beam 5 to selectively expose peak 2 and valley 3.

[0072] The procedure in FIG. 18, to reiterate, is directed at creating joining circuits on the peaks and valleys of the ridged architecture. The procedure will therefore be unnecessary if joining circuits can be created through the photolithographic modifications previously discussed.

[0073] By following the above steps, among others, skilled artisans can design and produce ridged wafers and ridged microchips according to the preferred embodiments of the invention. There are, of course, other potential embodiments and other potential manufacturing steps. For that reason, other methods and processes may be employed to implement the invention. It is believed, however, that the above steps constitute the best modes for implementing the invention.

[0074] Whatever embodiments and modes of implementation are chosen, the invention does, in fact, accomplish its primary objective. The invention, in particular, increases the usable surface area per given footprint of semiconductors. Although the amount of surface-area increase will vary depending on ridge angle and hypotenuse-to-leg ratios, it has been mathematically demonstrated that ridges having side geometries of isosceles right triangles will increase surface area by 41.42%.

[0075] The surface-area increase, as calculated, has numerous ramifications. First and foremost, an increase in surface area translates into greater heat dissipation, which is an important concern in microchip design. Aside from greater heat dissipation, however, the increase in surface area permits microchip footprints to be 29.29% smaller, allowing 1.41 times more microchips to fit on each wafer and thereby enhancing production yields. The increase in surface area also extends the life cycle of semiconductor foundries, allowing more circuits and components to be integrated per microchip using the same nanometer-resolutioned photolithographic process.

[0076] With that said, it must be emphasized that the invention and its advantages go beyond microchip-based logic and memory circuits. Ridged architecture can be applied to any semiconductor-dependent technology, including photovoltaic cells, modules, and arrays. If the invention is applied to the solar industry in accordance with the preferred embodiment, then photovoltaic devices can contain 41.42% more electron-shuttling junctions, increasing power output correspondingly.

[0077] The invention, in short, has wide-ranging impact and applies to all semiconducting devices, not just to traditional microchips. The invention also features objects, components, and advantages other than those mentioned.