Power converter counter circuit with under-regulation detector

Abstract

Circuits and methods for reducing lagging responses of a power converter to changes in circuit voltages or current, over-shoot/under-shoot when a target output voltage changes faster than the power converter's response, and open loop conditions. Embodiments include scanning a feedback voltage from a load powered by a voltage output by a power converter controlled by a PWM control signal; detecting an under-regulation condition; and, while the under-regulation condition is detected, increasing a clock signal rate to a counter outputting a count value usable to generate the PWM control signal. Embodiments include comparing a target output voltage to a signal representative of an output voltage of the power converter; indicating an under-shoot or over-shoot condition if the voltage difference exceeds a corresponding offset value; and limiting the range of values for an M-bit count value used to generate the PWM control signal to mitigate the under-shoot or over-shoot condition.

Claims

1. A controller for a power converter controlled by a pulse-width modulation (PWM) control signal, the controller including: (a) a counter having a clock signal input, inputs for receiving signals corresponding to at least one feedback voltage and signals indicating a count direction, and an output for providing an M-bit count value in response to the received signals; (b) a digital-to-analog converter coupled to the output of the counter and outputting a signal corresponding to the provided M-bit count value to generate the PWM control signal; (c) a clock signal selector, coupled to the clock signal input of the counter and configured to be coupled to a first clock signal and to a second clock signal, the second clock signal having a higher frequency than the first clock signal; and (d) an under-regulation detector circuit, configured to be coupled to the at least one feedback voltage, the under-regulation detector circuit outputting an under-regulation signal to the clock signal selector if the at least one feedback voltage is less than an under-regulation reference voltage; wherein while the under-regulation detector circuit outputs the under-regulation signal, the clock signal selector couples the second clock signal to the clock signal input of the counter, and otherwise couples the first clock signal to the clock signal input of the counter.

2. The invention of claim 1, wherein the under-regulation detector circuit includes: (a) a comparator coupled to the under-regulation reference voltage and configured to be coupled to the at least one feedback voltage; and (b) a resettable latching circuit coupled between an output of the comparator and the clock signal selector.

3. The invention of claim 1, wherein the clock signal selector is integrated within the counter.

4. The invention of claim 1, further including: (a) a first detector circuit configured to be coupled to the at least one feedback voltage, the first detector circuit outputting a first control signal to the counter if the at least one feedback voltage is greater than a first reference voltage; and (b) a second detector circuit configured to be coupled to the at least one feedback voltage, the second detector circuit outputting a second control signal to the counter if the at least one feedback voltage is less than a second reference voltage.

5. The invention of claim 4, wherein the under-regulation reference voltage is less than the first reference voltage and the second reference voltage.

6. The invention of claim 4, wherein each of the first and second detector circuits includes: (a) a corresponding comparator coupled to a corresponding one of the first or second reference voltage and configured to be coupled to the at least one feedback voltage; and (b) a resettable latching circuit coupled between an output of the corresponding comparator and one of the inputs of the counter.

7. The invention of claim 1, wherein the counter includes an increment input for receiving an increment control signal based on the at least one feedback voltage, a decrement input for receiving a decrement control signal based on the at least one feedback voltage, an under-shoot input, an over-shoot input, the invention further including: (a) a first comparator including an output coupled to the under-shoot input of the counter, a first input coupled to the output of the digital-to-analog converter, and a second input configured to be coupled to a signal representative of to an output voltage of the power converter, the first comparator outputting a first control signal indicating an under-shoot condition if the difference between the first input and second input of the first comparator exceeds a first offset value; and (b) a second comparator including an output coupled to the over-shoot input of the counter, a first input coupled to the output of the digital-to-analog converter, and a second input configured to be coupled to a signal representative of an output voltage of the power converter, the second comparator outputting a second control signal indicating an over-shoot condition if the difference between the first input and second input of the second comparator exceeds a second offset value; wherein receipt of the first control signal or the second control signal causes the counter to limit the range of values for the M-bit count value to mitigate the corresponding under-shoot condition or over-shoot condition.

8. A power converter including: (a) a DC-to-DC converter circuit having an input for receiving an input voltage, and an output for outputting an output voltage different from the input voltage in response to a pulse-width modulated (PWM) control signal; (b) a PWM duty cycle controller coupled to the DC-to-DC converter circuit and configured to generate the PWM control signal to the DC-to-DC converter circuit from an M-bit count value; (c) a counter having a clock signal input, inputs for receiving signals corresponding to at least one feedback voltage and indicating a count direction, and an output providing the M-bit count value; (d) a digital-to-analog converter configured to output to the PWM duty cycle controller a signal corresponding to the provided M-bit count value from the counter; (e) a first detector configured to be coupled to the at least one feedback voltage, the first detector circuit outputting a first control signal to the counter if the at least one feedback voltage is greater than a first reference voltage; (f) a second detector circuit configured to be coupled to the at least one feedback voltage, the second detector circuit outputting a second control signal if the at least one feedback voltage is less than a second reference voltage; (g) a clock signal selector, coupled to the clock signal input of the counter and configured to be coupled to a first clock signal and to a second clock signal, the second clock signal having a higher frequency than the first clock signal; and (h) an under-regulation detector circuit, coupled to the clock signal selector, to an under-regulation reference voltage, and configured to be coupled to the at least one feedback voltage, the under-regulation detector circuit outputting an under-regulation signal to the clock signal selector if the at least one feedback voltage is less than the under-regulation reference voltage; wherein while the under-regulation detector circuit outputs the under-regulation signal, the clock signal selector couples the second clock signal to the clock signal input of the counter, and otherwise couples the first clock signal to the clock signal input of the counter.

9. The invention of claim 8, wherein the under-regulation detector circuit includes: (a) a comparator coupled to the under-regulation reference voltage and configured to be coupled to the at least one feedback voltage; and (b) a resettable latching circuit coupled between an output of the comparator and the clock signal selector.

10. The invention of claim 8, wherein each of the first and second detector circuits includes: (a) a corresponding comparator coupled to a corresponding one of the first or second reference voltage and configured to be coupled to the at least one feedback voltage; and (b) a resettable latching circuit coupled between an output of the corresponding comparator and one of the inputs of the counter.

11. The invention of claim 8, wherein the clock signal selector is integrated within the counter.

12. The invention of claim 8, wherein the under-regulation reference voltage is less than the first reference voltage and the second reference voltage.

13. The invention of claim 8, wherein the feedback voltage is from an LED array coupled to the output voltage of the DC-to-DC converter circuit.

14. A method for minimizing a duration of an under-regulation condition of a power converter controlled by a pulse-width modulation (PWM) control signal, the method including: (a) scanning at least one feedback voltage from a load powered by the power converter; (b) generating up and down count direction signals as a function of the at least one feedback voltage; (c) providing the up and down count direction signals as inputs to a counter configured to output an M-bit digital count value in response to the provided up and down count direction signals and to a first clock signal having a first frequency; (d) converting the M-bit digital count value to an analog signal; (e) generating the PWM control signal in response to the analog signal; (f) detecting an under-regulation condition indicated by the at least one feedback voltage; (g) while the under-regulation condition is detected, coupling a second clock signal to the counter in place of the first clock signal, the second clock signal having a second frequency higher than the first frequency.

15. The method of claim 14, wherein detecting the under-regulation condition includes: (a) comparing an under-regulation reference voltage to the at least one feedback voltage; and (b) asserting the under-regulation condition if the at least one feedback voltage is less than the under-regulation reference voltage.

16. The method of claim 14, wherein the counter includes an integrated clock signal selector configured to select the first clock signal in the absence of the assertion of the under-regulation condition, and to select the second clock signal upon the assertion of the under-regulation condition.

17. The method of claim 14, wherein generating the up and down count direction signals includes: (a) outputting the up count direction signal to the counter if the at least one feedback voltage is greater than a first reference voltage; and (b) outputting the down count direction signal to the counter if the at least one feedback voltage is less than a second reference voltage.

18. The method of claim 17, wherein the under-regulation condition is detected when the at least one feedback voltage is less than an under-regulation reference voltage, and wherein the under-regulation reference voltage is less than the first reference voltage and the second reference voltage.

19. The method of claim 17, wherein: (a) outputting the first control signal includes: (1) comparing the at least one feedback voltage to the first reference voltage; and (2) setting an output of a first latch to reflect the comparison if the at least one feedback voltage is greater than the first reference voltage, wherein the output of the set first latch is the up count direction signal; and (b) outputting the second control signal includes: (1) comparing the at least one feedback voltage to the second reference voltage; and (2) setting an output of a second latch to reflect the comparison if the at least one feedback voltage is less than the second reference voltage, wherein the output of the set second latch is the down count direction signal.

20. The method of claim 14, wherein the counter includes an increment input for receiving an increment control signal based on the at least one feedback voltage, a decrement input for receiving a decrement control signal based on the at least one feedback voltage, an under-shoot input, an over-shoot input, the method further including: (a) outputting an under-shoot condition control signal to the under-shoot input of the counter if a first difference between the analog signal and a signal representative of an output voltage of the power converter exceeds a first offset value; (b) outputting an over-shoot condition control signal to the over-shoot input of the counter if a second difference between the analog signal and the signal representative of an output voltage of the power converter exceeds a second offset value; and (c) limiting the range of values for the M-bit digital count value in response to receipt of the under-shoot condition control signal or the over-shoot condition control signal.

Description

DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a block diagram showing a prior art DC-to-DC power converter.

(2) FIG. 2 is a schematic diagram of one prior art switched inductor-capacitor DC-to-DC power converter circuit.

(3) FIG. 3 is a schematic diagram of one prior art PWM duty cycle controller which may be used in the circuit of FIG. 2.

(4) FIG. 4 is a block diagram showing one prior art application that includes a switched inductor-capacitor DC-to-DC power converter, which may be of the type shown in FIG. 2.

(5) FIG. 5 is a schematic diagram of a part of a prior art power converter control circuit for the application shown in FIG. 4.

(6) FIG. 6 is a set of graphs showing V.sub.EV, the feedback voltage signal LED_FB.sub.X from an LED string, and the current I.sub.LED through the LED string, all versus time.

(7) FIG. 7 is a schematic diagram of a part of an improved power converter control circuit in accordance with the present invention.

(8) FIG. 8 is a set of graphs showing V.sub.OUT, V.sub.OUT_TARGET, the current I.sub.LED through an LED string, and the output of the clock signal selector, all versus time.

(9) FIG. 9 is a graph of V.sub.OUT_TARGET and V.sub.OUT versus time for one modeled embodiment of the LED array of FIG. 4 using a conventional switched inductor-capacitor DC-to-DC power converter and control system.

(10) FIG. 10 is a graph of V.sub.OUT_TARGET and V.sub.OUT versus time for one modeled embodiment of the LED array of FIG. 4 using an improved switched inductor-capacitor DC-to-DC power converter and control system in accordance with the present invention.

(11) FIG. 11 is a block diagram of one embodiment of an improved power converter control circuit in accordance with the present invention.

(12) FIG. 12 is a state diagram showing one combination of inputs to the up/down counter of FIG. 11 that prevent a target voltage V.sub.OUT_TARGET from deviating too far from the actual output voltage V.sub.OUT of a power converter.

(13) FIG. 13 is a process flow chart showing a first method for controlling a power converter controlled by a pulse-width modulation (PWM) control signal.

(14) FIG. 14 is a process flow chart showing a second method for controlling a power converter controlled by a PWM control signal.

(15) Like reference numbers and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION

(16) The invention encompasses circuits and methods for minimizing or eliminating both lagging responses of a switched inductor-capacitor DC-to-DC power converter to changes to V.sub.IN, V.sub.OUT, and/or I.sub.OUT, and over-shoot/under-shoot that may occur when the target output voltage changes faster than the power converter's response.

(17) Under-Regulation Control

(18) Careful consideration of certain operational conditions of an LED array 406 has lead to the understanding that the occurrence of two sequential states can lead to LED flicker. The first state is steady-state over-regulation (V.sub.OUT>V.sub.OUT_TARGET), which may occur under high V.sub.IN/low V.sub.OUT conditions. For example, in one embodiment of a DC-to-DC power converter that includes a switched inductor-capacitor boost converter followed by a charge pump (CP), if V.sub.IN is about 15V and the CP boost factor is two, then the minimum output voltage would be 30V. However, if the desired output is about 28V, then the power converter will be in an over-regulated state until V.sub.IN reduces or the desired V.sub.OUT increases above 30V. When in steady-state over-regulation, the DAC 510 continues to count down but V.sub.OUT does not follow as quickly. The DAC 510 eventually stops counting down at a lower output count M. If The second state then occurs, which is that V.sub.IN drops from a high voltage to a lower voltage, V.sub.OUT can now regulate to a lower voltage and will drop to V.sub.OUT_TARGET, which may have decremented too low for a desired LED brightness. Accordingly, noticeable screen flicker may occur due to a resultant unexpected drop in LED current and a slow update rate for the DAC 510.

(19) For example, FIG. 6 is a set of graphs 600 showing V.sub.IN, the feedback voltage signal LED_FB.sub.X from an LED string, and the current I.sub.LED through the LED string, all versus time. Graph line 602 shows V.sub.IN, initially at an elevated value, suddenly drops to a lower value at time T1, such as may occur when the power source to an LED display changes from AC to a battery (e.g., when a laptop computer is unplugged from a wall outlet). As a result, V.sub.OUT will drop and consequently the feedback voltage signal LED_FB.sub.X (which is a function of V.sub.OUT) will abruptly drop at time T1 to an under-regulated value, as shown by graph line 604. Before the DAC 510 can correct V.sub.OUT by counting to a higher value by time T2 (about 30 mS later than time T1 in this example), the LED current I.sub.LED drops between times T1 and T2, as shown by graph line 606. The drop in the LED current I.sub.LED causes noticeable dimming, seen as a flicker due to the recovery of V.sub.OUT by time T2 when the DAC 510 has counted up sufficiently to raise V.sub.OUT to a level that supplies sufficient current to the LEDs.

(20) Using a faster DAC 510 to correct for this situation can cause oscillations in the control loop, and is thus undesirable. Embodiments of the present invention provide a novel solution, which detects under-regulation of the feedback voltage signals LED_FB.sub.1-LED_FB.sub.N and temporarily increases the clock rate to the up/down counter 508 to increment the output count M more quickly to the DAC 510, thus boosting V.sub.OUT more quickly and thereby essentially eliminating LED flicker (for example, reducing the interval from time T1 to time T2 in FIG. 6 to less than about 1-2 mS generally would not be perceived as flicker by the human eye).

(21) For example, FIG. 7 is a schematic diagram of a part of an improved power converter control circuit 700 in accordance with the present invention. The improved control circuit 700 may be used, for example, to control the DC-DC power converter 402 in FIG. 4. Similar in many aspects to the circuit shown in FIG. 5, the circuit illustrated in FIG. 7 includes additional components to realize a novel solution. More specifically, the feedback voltage signals LED_FB.sub.1-LED_FB.sub.N from the circuit of FIG. 4 are also selectively coupled through corresponding switches S.sub.1-S.sub.N, functioning as a multiplexor, to an under-regulation detector circuit 701 comprising, in this example, an added analog comparator 702 having built-in hysteresis and an added resettable latching circuit, such as a set-reset (SR) flip-flop 704.

(22) In greater detail, a feedback voltage signal LED_FB.sub.X is coupled to a first input of the added analog comparator 702. An added programmable reference voltage source 706 is coupled to a second input of the added comparator 702, and generates a dynamic under-regulation threshold voltage V.sub.REF3, the value of which depends on LED programmed current and other factors, such as process/voltage/temperature (PVT) variations. The dynamic under-regulation voltage V.sub.REF3 generally correlates to LED brightness (e.g., a higher LED current means a higher threshold value for V.sub.REF3, and a lower LED current means a lower threshold value for V.sub.REF3).

(23) Notably, the relative values output by the reference voltage sources 504a, 504b, and 706 are such that V.sub.REF1>V.sub.REF2>V.sub.REF3. Accordingly, V.sub.REF3 sets a relatively low threshold, corresponding to an under-regulated voltage value, for comparison against the feedback voltage signals LED_FB.sub.1-LED_FB.sub.N in the added comparator 702. The under-regulation threshold value for V.sub.REF3 is preferably set such that the DAC 510 is always in an increment mode when an under-regulation condition exists, thus preventing fast decrementing which could lead to oscillations.

(24) The output of the added comparator 702 is coupled to the added set-reset (SR) flip-flop 704, which is reset after each feedback voltage signal LED_FB.sub.1-LED_FB.sub.N is Compared. If a feedback voltage signal LED_FB.sub.X is less than V.sub.REF3, the added flip-flop 704 is set (i.e., the Q output is “1”) and generates an UNDER_REG signal from the under-regulation detector circuit 701 indicating that an under-regulation condition exists for the corresponding LED. The under-regulation detector circuit 701 may be implemented in other circuitry without changing the functionality.

(25) The UNDER_REG signal is coupled to a clock signal selector 708, which is essentially a multiplexer. In the illustrated example, the clock signal selector 708 comprises first and second AND gates A1, A2 having outputs coupled to an OR gate. The output of the OR gate is coupled to the clock input CLK of the up/down counter 508. The UNDER_REG signal is coupled indirectly to a first input of the first AND gate A1 after inversion by an intervening inverter I, and directly to a first input of the second AND gate A2. The first AND gate A1 has a second input coupled to a first clock signal CLK1, while the second AND gate A2 has a second input coupled to a second clock signal CLK2, the second clock signal CLK2 is at a higher frequency than the first clock signal CLK1. The second clock signal CLK2 may have, for example, a frequency 2-10 times higher than the frequency of the first clock signal CLK1, but even higher frequencies for the second clock signal CLK2 may be used in some embodiments.

(26) When an under-regulation condition is absent, the UNDER_REG signal will be a “0”, and the clock signal selector 708 will pass only the first clock signal CLK1 to the clock input CLK of the up/down counter 508. However, when an under-regulation condition occurs, the UNDER_REG signal will be a “1”, and the clock signal selector 708 will pass only the second clock signal CLK2 to the clock input CLK of the up/down counter 508. As should be clear, the logic of the clock signal selector 708 may be incorporated into the up/down counter 508, which would then have at least two clock inputs, for the CLK1 and CLK2 clock signals.

(27) In alternative embodiments, rather than switch clock speeds to the up/down counter 508, the UNDER_REG signal may cause a relatively high preset value to be loaded into the up/down counter 508 (e.g., through the MISC input), thereby setting the up/down counter 508 to a higher value of the output count M than existed when the under-regulation event occurred. The higher preset value, which results in a higher value of V.sub.OUT_TARGET from the DAC 510, will thus drive V.sub.OUT more quickly to a sufficiently high value to mitigate the under-regulation event. The higher preset value for M may be just to a high pre-determined code, or may be algorithmically or heuristically determined (for example, based on a known number of LEDs in a string and the present current draw) and dynamically computed or stored in a look-up table.

(28) FIG. 8 is a set of graphs 800 showing V.sub.OUT, V.sub.OUT_TARGET, the current I.sub.LED through an LED string, and the output of the clock signal selector 708, all versus time. Before time T1′, while V.sub.OUT has a steady value, the clock signal selector 708 outputs the first clock signal CLK1 (graph line 802). At about time T1′, V.sub.OUT sags (graph line 804), causing I.sub.LED (graph line 806) to sag. However, at about time T1′, the added components in FIG. 7 (702, 704, 706) will detect that the corresponding feedback voltage signal LED_FB.sub.X (not shown in FIG. 8) is in an under-regulated condition, thus asserting the UNDER_REG signal to the clock signal selector 708, thereby selecting the second clock signal CLK2 as the clock input for the up/down counter 508. The higher-rate second clock signal CLK2 is applied from about time T1′ to about time T2′, causing the up/down counter 508 to more rapidly provide incrementing values of the output count M to be applied to the DAC 510, thus causing V.sub.OUT_TARGET (graph line 808) to begin increasing to force V.sub.OUT higher. When V.sub.OUT equals the target value V.sub.OUT_TARGET eventually reached at time T2′, the UNDER_REG signal to the clock signal selector 708 is reset, thereby selecting the first clock signal CLK1 as the clock input for the up/down counter 508 when V.sub.OUT again has a steady value.

(29) Notably, the duration of the sag in the LED current I.sub.LED in the illustrated example is less than about 1 mS in duration, which generally would not be perceived as flicker by the human eye (as should be clear, the time scale of FIG. 8 differs from the time scale of FIG. 6).

(30) To sum up, embodiments of this aspect of the present invention include circuits and methods that accomplish the following functions: (1) scanning the feedback voltage signals LED_FB.sub.1-LED_FB.sub.N from the LED array 406 to detect any under-regulation condition (e.g., the LED feedback voltage signal is too low for the current level through the LED); when an under-regulation condition is detected, switching the DAC 510 to a faster increment rate by applying a higher frequency clock signal to the up/down counter 508; and, once all feedback voltage signals LED_FB.sub.1-LED_FB.sub.N exceed the under-regulation threshold, switching back to a normal up/down counter 508 frequency (and hence a normal DAC update rate).

(31) Regulating Under-Shoot/Over-Shoot Conditions

(32) Another problem identified after careful consideration of certain operational conditions of a switched inductor-capacitor DC-to-DC power converter and control system has led to the understanding that when the target output voltage changes faster than the power converter's response time, large under-shoots/over-shoots in V.sub.OUT can occur due to open-loop conditions, making the system less efficient.

(33) For example, the feedback voltage signals LED_FB.sub.1-LED_FB.sub.N of the LED array 406 may indicate that V.sub.OUT needs to increase rapidly from a voltage V1 to a voltage V2. The feedback voltage signals thus cause V.sub.OUT_TARGET to rapidly increment in step-wise fashion by action of the control circuit shown in FIG. 5. However, if the DC-DC power converter 402 is slower than the rate of changes to V.sub.OUT_TARGET, open-loop conditions can occur. In particular, when the difference (delta) between V.sub.OUT_TARGET and V.sub.OUT is large, the output of the error amplifiers 502a, 502b is railed (i.e., has reached the maximum value possible for the error amplifier circuitry) and an open loop condition occurs. Large over-shoots/under-shoots in V.sub.OUT can be observed as the system returns to a closed loop condition.

(34) For example, FIG. 9 is a graph 900 of V.sub.OUT_TARGET and V.sub.OUT versus time for one modeled embodiment of the LED array 406 of FIG. 4 using a conventional switched inductor-capacitor DC-to-DC power converter and control system. A feedback voltage signal LED_FB.sub.X from the LED array 406 indicates that V.sub.OUT needs to increase rapidly from voltage V1 to voltage V2. In this example, the DAC 510 will output V.sub.OUT_TARGET in step-wise fashion to increment V.sub.OUT. However, it takes time for the DC-DC power converter 402 to ramp V.sub.OUT up. Accordingly, V.sub.OUT_TARGET will be further incremented, increasing the delta between V.sub.OUT_TARGET and V.sub.OUT. Eventually, V.sub.OUT_TARGET is stepped up to Level A as the error amplifiers 502a, 502b are railed. However, owing to the lag time of the DC-DC power converter 402, it will respond to values of V.sub.OUT_TARGET above V2, thus over-shooting the desired V2 voltage level to Level B. When the feedback voltage signal LED_FB.sub.X indicates that V.sub.OUT exceeds V2, V.sub.OUT_TARGET will be decremented to Level C, causing V.sub.OUT to under-shoot V2 down to Level D. As V.sub.OUT_TARGET is again corrected by the feedback voltage signal LED_FB.sub.X, V.sub.OUT settles to Level E, equal to the desired V2 voltage. Thus, V.sub.OUT “hunts” around V2 until eventually reaching the desired target voltage, which results in inefficiency for the power converter.

(35) With this understanding of the characteristics of a conventional switched inductor-capacitor DC-to-DC power converter and control system, it was realized that the power converter controller could be improved so as to hold or reverse changes to V.sub.OUT_TARGET to keep a closed loop condition for the system.

(36) For example, FIG. 10 is a graph 1000 of V.sub.OUT_TARGET and V.sub.OUT versus time for one modeled embodiment of the LED array 406 of FIG. 4 using an improved switched inductor-capacitor DC-to-DC power converter and control system in accordance with the present invention. A feedback voltage signal LED_FB.sub.X from the LED array 406 indicates that V.sub.OUT needs to increase rapidly from voltage V1 to voltage V2. The DAC 510 will output V.sub.OUT_TARGET in step-wise fashion to increment V.sub.OUT. As V.sub.OUT_TARGET is incremented, the delta between V.sub.OUT_TARGET and V.sub.OUT will increase. However, by monitoring V.sub.OUT_TARGET and V.sub.OUT to determine if the delta exceeds a desired positive threshold, increments in V.sub.OUT_TARGET can be suppressed (overridden) at points 1, 2, 3, and 4, thus reducing the delta between V.sub.OUT_TARGET and the lagging V.sub.OUT. The override of an undesired increment may be, for example, by causing a counter to decrement. Thus, in this example, V.sub.OUT over-shoots V2 only slightly to Level F, and accordingly can be quickly corrected back to Level G, which equals V2. Similarly, if the delta exceeds a desired negative threshold, decrements in V.sub.OUT_TARGET can be suppressed (overridden), thus reducing the delta between V.sub.OUT_TARGET and the lagging V.sub.OUT. The override of an undesired decrement may be, for example, by causing a counter to increment. The lessened over-shoot and under-shoot of V.sub.OUT combined with the faster correction time results in a more efficient DC-to-DC power converter and control system. More specifically, the load current I.sub.LOAD is more accurately maintained, and the entire circuit exhibits less power loss compared to conventional circuits.

(37) FIG. 11 is a block diagram of one embodiment of an improved power converter control circuit 1100 in accordance with the present invention. The improved control circuit 1100 may be used, for example, to control the DC-DC power converter 402 in FIG. 4. Similar in some aspects to the circuit shown in FIG. 3, the circuit illustrated in FIG. 11 includes additional components to realize a novel solution. More specifically, the feedback voltage V.sub.OUT_FB from the scaling circuit 302, proportional to V.sub.OUT, is coupled to a first input of first and second window comparators 1102a, 1102b. A second input of the first and second window comparators 1102a, 1102b is coupled to V.sub.OUT_TARGET (which is the desired value that V.sub.OUT should attain). A characteristic of the first and second window comparators 1102a, 1102b is that they have a programmable offset, so that a desired delta between the inputs can be programmably set for each window comparator 1102a, 1102b.

(38) In the illustrated example, the offset for the first window comparator 1102a is set so that a negative delta between V.sub.OUT_TARGET and V.sub.OUT— indicating a tendency to under-shoot—triggers a DAC_LO output to an up/down counter 1104. The offset for the second window comparator 1102b is set so that a positive delta between V.sub.OUT_TARGET and V.sub.OUT—indicating a tendency to over-shoot—triggers a DAC_HI output to the up/down counter 1104.

(39) The up/down counter 1104 accepts multiple inputs and allows logic combinations of those inputs to determine a value for an output count M. Other inputs to the up/down counter 1104 include LED_HI and LED_LO signals (e.g., from the circuit of FIG. 7), possible miscellaneous inputs MISC, and a CLK input. In some embodiments, the clock input CLK of the up/down counter 1104 may be coupled to a clock signal selector 708 controlled by an UNDER_REG signal, as in FIG. 7. The up/down counter 1104 uses the four inputs (DAC_HI, DAC_LO, LED_HI, LED_LO), and may use one or more miscellaneous inputs (e.g., fault conditions), to generate the M-bit output count.

(40) For example, FIG. 12 is a state diagram 1200 showing one combination of inputs to the up/down counter 1104 of FIG. 11 that prevent a target voltage V.sub.OUT_TARGET from deviating too far from the actual output voltage V.sub.OUT of a power converter. The symbol “+” represents a bitwise logic OR operation, the symbol “&” represents a bitwise logic AND operation, and the symbol “/” (a slash) represents a logic NOT (inversion) operation. The HOLD state indicates that V.sub.OUT_TARGET should not be incremented or decremented. The INCREMENT state indicates that V.sub.OUT_TARGET should be incremented, and the DECREMENT state indicates that V.sub.OUT_TARGET should be decremented.

(41) Under normal conditions, DAC_HI and DAC_LO will be low, and thus not affect incrementing/decrementing of V.sub.OUT_TARGET by the LED_LO and LED_HI signals. However, the new signals DAC_HI and DAC_LO are given priority over the conventional LED_LO and LED_HI signals. Thus, for example, if the up/down counter 1104 is in the HOLD state, and DAC_LO is asserted, the up/down counter 1104 will transition to the INCREMENT state regardless of the state of LED_LO, owing to the combination [DAC_LO+LED_LO & /DAC_HI]. It is possible to use combinations of DAC_HI, DAC_LO, LED_HI, and LED_LO in conjunction with other signals (e.g., enable and/or error signals) to define other states and pathways between states.

(42) Accordingly, by adding window comparators coupled to the power converter output V.sub.OUT (or to a scaled version of V.sub.OUT) and the target output V.sub.OUT_TARGET, the up/down counter 1104 of the power converter controller can hold or reverse changes to V.sub.OUT_TARGET to keep V.sub.OUT_TARGET from deviating too far from V.sub.OUT, thus maintaining a closed loop condition. Stated another way, preventing V.sub.OUT_TARGET from deviating too far from V.sub.OUT substantially prevents open loop conditions that can cause large over-shoots and/or under-shoots.

(43) Improved PWM Duty Cycle Controller

(44) Embodiments of the present invention may include an optional modification, shown in FIG. 11. As disclosed in detail in the U.S. Patent Application incorporated herein by the reference above, a current-controlled voltage source (CCVS) 1106 may be inserted between the error amplifier 304 and the comparator 310. As is known in the art, a CCVS outputs a voltage proportional to an applied current. The CCVS 1106 is preferably configured with an adjustable gain, thus allowing a selectable fraction of the current through the inductor L (see FIG. 2) to be converted to a voltage that adds to or subtracts from the integrated error signal, COMP, to generate a modified signal COMP_CM that is applied to the comparator 310. When the gain is set to zero, the PWM duty cycle controller 500 behaves like a standard Voltage Mode controller. When the gain is set to non-zero values, the PWM duty cycle controller 500 behaves like a hybrid of a Voltage Mode controller and a Current Mode controller.

(45) By adding the voltage contribution from the CCVS 1106—indicative of the current through the inductor L—to the COMP error signal, the benefits of integrating feed-forward into the Voltage Mode V.sub.RAMP comparison can be combined with the simpler dynamic of sensing the inductor current. Thus, embodiments of the present invention that include the CCVS 1106 preserve the general benefits of a Voltage Mode controller, including better load step response than a pure Current Mode controller and operation at higher frequencies than a Current Mode controller (leading to faster response times to voltage and/or load variations), while eliminating or mitigating the disadvantages of a pure Voltage Mode controller with respect to stable operation in both constant current mode and discontinuous current mode. Other benefits of including the CCVS 1106 in the improved control circuit 1100 of FIG. 11 are described in the U.S. Patent Application incorporated herein by the reference above.

(46) Methods

(47) Another aspect of the invention includes methods for controlling a power converter controlled by a PWM control signal. As one example, FIG. 13 is a process flow chart 1300 showing a first method for controlling a power converter controlled by a pulse-width modulation (PWM) control signal. The method includes: scanning at least one feedback voltage from a load powered by a voltage output by a power converter controlled by a PWM signal (Block 1302); detecting an under-regulation condition indicated by the at least one feedback voltage (Block 1304); and while the under-regulation condition is detected, increasing a clock signal rate to a counter outputting a count value usable to generate the PWM control signal to the power converter (Block 1306).

(48) As another example, FIG. 14 is a process flow chart 1400 showing a second method for controlling a power converter controlled by a PWM control signal. The method includes: comparing a target output voltage to a signal representative of an output voltage of a power converter controlled by a PWM control signal (Block 1402); indicating an under-shoot condition if the difference between the compared voltages exceeds a first offset value and indicating an over-shoot condition if the difference between the compared voltages exceeds a second offset value (Block 1404); and limiting the range of values for an M-bit count value used to generate the PWM control signal to mitigate under-shoot condition if indicated or the over-shoot condition if indicated (Block 1406).

(49) As should be clear, the above methods may be performed together in a single control for a power converter controlled by a PWM control signal.

ALTERNATIVE EMBODIMENTS, FABRICATION TECHNOLOGIES & OPTIONS

(50) While the example above have used a pulse-width modulation (PWM) closed-loop controller as an example, circuits and methods embodying the inventions described herein may be readily adapted to other types of controllers. For example, a pulse-frequency modulation (PFM) close-looped controller may be used in conjunction with circuits such as those shown in FIGS. 7 and 11. PFM is a modulation method in which the width of square-wave pulses is fixed (rather than variable, as with PWM) while varying the frequency of the pulses. In other embodiments, a hysteretic controller or any generic controller that provides a controlling signal to a DC-DC converter circuit may be further regulated by circuits such as those shown in FIGS. 7 and 11.

(51) The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and/or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.

(52) Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 50 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.

(53) Voltage levels may be adjusted, and/or voltage and/or logic signal polarities reversed, depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functionality without significantly altering the functionality of the disclosed circuits.

(54) Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and/or in modules for ease of handling, manufacture, and/or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and/or modules are then typically combined with other components, often on a printed circuit board, to form an end product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

CONCLUSION

(55) A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and/or parallel fashion.

(56) It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).