ENVELOPE TRACKING INTEGRATED CIRCUIT OPERABLE ACROSS WIDE MODULATION BANDWIDTH
20240014787 ยท 2024-01-11
Inventors
Cpc classification
International classification
Abstract
An envelope tracking (ET) integrated circuit (ETIC) operable across wide modulation bandwidth is disclosed. The ETIC includes at least two auxiliary voltage outputs coupled to a high-bandwidth power amplifier circuit that has a lower equivalent capacitance, and thus a higher impedance resonance frequency. The ETIC also includes a pair of ET voltage circuits configured to generate a pair of ET voltages, respectively. To help mitigate potential distortion in the ET voltages, a control circuit is configured to couple the ET voltage circuits exclusively to the auxiliary voltage outputs when the ETIC needs to operate with a high modulation bandwidth (e.g., 200 MHz). Given the higher impedance resonance frequency of the high-bandwidth power amplifier circuit, it is possible to increase separation between an energy spectrum of a voltage disturbance and an energy spectrum of the high modulation bandwidth, thus helping to reduce the potential distortion in the ET voltages.
Claims
1. An envelope tracking (ET) integrated circuit (ETIC) comprising: at least two primary voltage outputs each coupled to a respective one of at least two low-bandwidth power amplifier circuits each having a first equivalent capacitance; at least two auxiliary voltage outputs coupled to a high-bandwidth power amplifier circuit having a second equivalent capacitance lower than the first equivalent capacitance to thereby cause the high-bandwidth power amplifier circuit to have a higher impedance resonance frequency than each of the at least two low-bandwidth power amplifier circuits; a first ET voltage circuit configured to generate a first ET voltage based on a first target voltage; a second ET voltage circuit configured to generate a second ET voltage based on a second target voltage; and a control circuit configured to: determine whether the ETIC needs to operate with a high modulation bandwidth or a low modulation bandwidth; and couple each of the first ET voltage circuit and the second ET voltage circuit to a respective one of the at least two primary voltage outputs in response to determining that the ETIC needs to operate with the low modulation bandwidth.
2. The ETIC of claim 1, wherein the control circuit is further configured to decouple the first ET voltage circuit and the second ET voltage circuit from the at least two primary voltage outputs in response to determining that the ETIC needs to operate with the high modulation bandwidth.
3. (canceled)
4. The ETIC of claim 1, wherein the control circuit is further configured to decouple the first ET voltage circuit and the second ET voltage circuit from the at least two auxiliary voltage outputs in response to determining that the ETIC needs to operate with the low modulation bandwidth.
5. The ETIC of claim 1, wherein the control circuit is further configured to determine whether the ETIC needs to operate with the high modulation bandwidth or the low modulation bandwidth based on any one of the first target voltage and the second target voltage.
6. The ETIC of claim 5, wherein the control circuit is further configured to determine whether the ETIC needs to operate with the high modulation bandwidth or the low modulation bandwidth based on a higher one of the first target voltage and the second target voltage.
7. The ETIC of claim 1, further comprising: a first voltage equalizer circuit coupled to the first ET voltage circuit and configured to equalize the first target voltage based on a first transfer function; and a second voltage equalizer circuit coupled to the second ET voltage circuit and configured to equalize the second target voltage based on a second transfer function.
8. An envelope tracking (ET) power management circuit comprising: at least two low-bandwidth power amplifier circuits each having a first equivalent capacitance; a high-bandwidth power amplifier circuit having a second equivalent capacitance lower than the first equivalent capacitance to thereby cause the high-bandwidth power amplifier circuit to have a higher impedance resonance frequency than each of the at least two low-bandwidth power amplifier circuits; and an ET integrated circuit (ETIC) comprising: at least two primary voltage outputs each coupled to a respective one of the at least two low-bandwidth power amplifier circuits; at least two auxiliary voltage outputs coupled to the high-bandwidth power amplifier circuit; a first ET voltage circuit configured to generate a first ET voltage based on a first target voltage; a second ET voltage circuit configured to generate a second ET voltage based on a second target voltage; and a control circuit configured to: determine whether the ETIC needs to operate with a high modulation bandwidth or a low modulation bandwidth; couple each of the first ET voltage circuit and the second ET voltage circuit to a respective one of the at least two auxiliary voltage outputs in response to determining that the ETIC needs to operate with the high modulation bandwidth; and couple each of the first ET voltage circuit and the second ET voltage circuit to a respective one of the at least two primary voltage outputs in response to determining that the ETIC needs to operate with the low modulation bandwidth.
9. The ET power management circuit of claim 8, wherein the control circuit is further configured to decouple the first ET voltage circuit and the second ET voltage circuit from the at least two primary voltage outputs in response to determining that the ETIC needs to operate with the high modulation bandwidth.
10. (canceled)
11. The ET power management circuit of claim 8, wherein the control circuit is further configured to decouple the first ET voltage circuit and the second ET voltage circuit from the at least two auxiliary voltage outputs in response to determining that the ETIC needs to operate with the low modulation bandwidth.
12. The ET power management circuit of claim 8, wherein the control circuit is further configured to determine whether the ETIC needs to operate with the high modulation bandwidth or the low modulation bandwidth based on any one of the first target voltage and the second target voltage.
13. The ET power management circuit of claim 12, wherein the control circuit is further configured to determine whether the ETIC needs to operate with the high modulation bandwidth or the low modulation bandwidth based on a higher one of the first target voltage and the second target voltage.
14. The ET power management circuit of claim 8, further comprising: a first voltage equalizer circuit coupled to the first ET voltage circuit and configured to equalize the first target voltage based on a first transfer function; and a second voltage equalizer circuit coupled to the second ET voltage circuit and configured to equalize the second target voltage based on a second transfer function.
15. The ET power management circuit of claim 14, wherein the first transfer function and the second transfer function are each determined to offset a voltage disturbance caused by any one of the high-bandwidth power amplifier circuit and the at least two low-bandwidth power amplifier circuits.
16. The ET power management circuit of claim 8, wherein the high-bandwidth power amplifier circuit comprises: a plus input stage and a plus output stage each coupled to a first one of the at least two auxiliary voltage outputs; and a minus input stage and a minus output stage each coupled to a second one of the at least two auxiliary voltage outputs.
17. The ET power management circuit of claim 16, wherein the plus output stage and the minus output stage are coupled to a plus load capacitor and a minus load capacitor, respectively.
18. The ET power management circuit of claim 17, wherein the at least two low-bandwidth power amplifier circuits each comprises an input stage and an output stage coupled to a respective one of the at least two primary voltage outputs.
19. The ET power management circuit of claim 18, wherein the output stage is coupled to a load capacitor.
20. The ET power management circuit of claim 19, wherein the plus load capacitor and the minus load capacitor are configured to each have a lower capacitance than the load capacitor to thereby cause the second equivalent capacitance to be lower than the first equivalent capacitance.
Description
BRIEF DESCRIPTION OF THE DRAWING FIGURES
[0011] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.
[0012]
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DETAILED DESCRIPTION
[0018] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
[0019] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items.
[0020] It will be understood that when an element such as a layer, region, or substrate is referred to as being on or extending onto another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly on or extending directly onto another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being over or extending over another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly over or extending directly over another element, there are no intervening elements present. It will also be understood that when an element is referred to as being connected or coupled to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being directly connected or directly coupled to another element, there are no intervening elements present.
[0021] Relative terms such as below or above or upper or lower or horizontal or vertical may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms a, an, and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises, comprising, includes, and/or including when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
[0024] Embodiments are described herein with reference to an envelope tracking (ET) integrated circuit (ETIC) operable across wide modulation bandwidth. The ETIC includes a primary voltage output(s) coupled to a low-bandwidth power amplifier circuit(s) and at least two auxiliary voltage outputs coupled to a high-bandwidth power amplifier circuit. In embodiments disclosed herein, the high-bandwidth power amplifier circuit has a lower equivalent capacitance, and thus a higher impedance resonance frequency, than the low-bandwidth power amplifier circuit(s). The ETIC also includes a pair of ET voltage circuits configured to generate a pair of ET voltages, respectively. To help mitigate potential distortion in the ET voltages, a control circuit is configured to couple the ET voltage circuits exclusively to the auxiliary voltage outputs when the ETIC needs to operate with a high modulation bandwidth (e.g., 200 MHz). Given the higher impedance resonance frequency of the high-bandwidth power amplifier circuit, it is possible to increase separation between an energy spectrum of a voltage disturbance, which is inherently caused by the high-bandwidth power amplifier circuit, and an energy spectrum of the high modulation bandwidth, thus helping to reduce the potential distortion in the ET voltages.
[0025] Before discussing the ETIC incorporated therein according to the present disclosure, starting at
[0026]
[0027] The transceiver circuit 12 is configured to generate and provide an RF signal 20, which is associated with a time-variant power envelope P.sub.ENV, to the power amplifier circuit 16. The transceiver circuit 12 is also configured to generate (a.k.a. track) a target voltage V.sub.TGT in accordance with the time-variant power envelope P.sub.ENV. The ETIC 14 is configured to generate the ET voltage V.sub.CC based on the target voltage V.sub.TGT and the power amplifier circuit 16 is configured to amplify the RF signal 20 based on the ET voltage V.sub.CC.
[0028] Those skilled in the art will appreciate that the power amplifier circuit 16 may operate with improved efficiency and linearity when the ET voltage V.sub.CC accurately tracks the power envelope P.sub.ENV of the RF signal 20. This is achieved when the ET voltage V.sub.CC is temporally aligned with the target voltage V.sub.TGT at the power amplifier circuit 16. However, temporal alignment between the ET voltage V.sub.CC and the target voltage V.sub.TGT may be complicated by various impedances, capacitances, and/or inductances presenting in the conventional power management apparatus 10.
[0029] To illustrate the various impedances, capacitance, and/or inductances,
[0030] In the equivalent circuit 22, the ETIC 14 in
[0031] The power amplifier circuit 16 can be modeled as a current source with a modulated current I.sub.CC(s) and have a total equivalent capacitance C.sub.PA. Accordingly, an equivalent source impedance Z.sub.SOURCE(s) presented to the current source can be determined as in equation (Eq. 1) below.
[0032] In the equation (Eq. 1), s represents the s-transform notation, which can be expressed as s=j2f. The modulated current I.sub.CC(s) is somewhat proportional to the target voltage V.sub.TGT and can be expressed as in equation (Eq. 2) below.
[0033] In the equation (Eq. 2) above, Z.sub.ICC(s) represents an impedance at a collector (not shown) of the power amplifier circuit 16 and D represents a group delay between the V.sub.TGT and the time-variant power envelope P.sub.EVN at an output stage (not shown) of the power amplifier circuit 16.
[0034] Notably, the modulated current I.sub.CC can create a voltage disturbance across the collector of the power amplifier circuit 16. The voltage disturbance is approximately equal to Z.sub.SOURCE(s)*I.sub.CC(s). As illustrated and discussed in
[0035]
f=1/(2{square root over (L*C.sub.PA)})(Eq. 3)
[0036] In the equation (Eq. 3) above, L represents the total equivalent inductance and C.sub.PA represents the total equivalent capacitance in the equivalent circuit 22 of
[0037] In contrast, when the RF signal 20 is modulated with a high modulation bandwidth (e.g., 200 MHz), the disturbance energy spectrum 26 may be very close or even overlap with an energy spectrum 30 associated with the high modulation bandwidth. As such, it may not be possible to rely solely on the equalizer circuit to offset the voltage disturbance to avoid potential distortion in the ET voltage V.sub.CC.
[0038] However, as shown in the equation (Eq. 3), it is possible to shift the impedance resonance frequency f, and thereby the disturbance energy spectrum 26, away (e.g., rightward) from the energy spectrum 30 associated with the high modulation bandwidth by reducing the overall equivalent capacitance C.sub.PA. Thus, by pushing away the disturbance energy spectrum 26 in addition to employing the equalizer circuit to offset the voltage disturbance, it is possible to minimize potential distortion in the ET voltage V.sub.CC. In this regard,
[0039] The ET power management circuit 32 includes an ETIC 34. The ETIC 34 includes a first ET voltage circuit 36A and a second ET voltage circuit 36B. The first ET voltage circuit 36A is configured to generate a first ET voltage V.sub.CCA based on a first target voltage V.sub.TGTA. The second ET voltage circuit 36B is configured to generate a second ET voltage V.sub.CCB based on a second target voltage V.sub.TGTB. Notably, the first ET voltage V.sub.CCA can be identical to or different from the second ET voltage V.sub.CCB.
[0040] The ETIC 34 includes at least two primary voltage outputs 38A, 38B, and at least two auxiliary voltage outputs 40A, 40B. In an embodiment, the primary voltage outputs 38A, 38B are each coupled to a respective one of at least two low-bandwidth power amplifier circuits 42A, 42B (denoted as LBW PA) via a respective one of at least two primary signal lines 44A, 44B. In a non-limiting example, the low-bandwidth power amplifier circuits 42A, 42B can each amplify a respective one of at least two low-bandwidth RF signals 46A, 46B, which are modulated with a low modulation bandwidth (e.g., <100 MHz), based on a respective one of the first ET voltage V.sub.CCA and the second ET voltage V.sub.CCB.
[0041] Notably, the primary signal line 44A can have an equivalent trance inductance L.sub.TRACE-44A and the primary signal line 44B can have an equivalent trace inductance L.sub.TRACE-44B. The equivalent trance inductance L.sub.TRACE-44A and the equivalent trace inductance L.sub.TRACE-44B are equivalent to the equivalent trace inductance L.sub.TRACE in
[0042] The auxiliary voltage outputs 40A, 40B are each coupled to a high-bandwidth power amplifier circuit 48 (denoted as HBW PA) via a respective one of at least two auxiliary signal lines 50A, 50B. In a non-limiting example, the high-band power amplifier circuit 48 can amplify a high-bandwidth RF signal 52, which is modulated with a high modulation bandwidth (e.g., 200 MHz), based on both the first ET voltage V.sub.CCA and the second ET voltage V.sub.CCB.
[0043] Notably, the auxiliary signal lines 50A, 50B can each have a respective one of equivalent trance inductances L.sub.TRACE-50A, L.sub.TRACE-50B that are equivalent to the equivalent trace inductance L.sub.TRACE in
[0044] In embodiments disclosed herein, the equivalent capacitances C.sub.PA-48 of the high-bandwidth power amplifier 48 is configured to be lower than the equivalent capacitance C.sub.PA-42A of the low-bandwidth power amplifier circuit 42A and the equivalent capacitance C.sub.PA-42B of the low-bandwidth power amplifier circuit 42B. As such, if the equivalent trace inductances L.sub.TRACE-50A, L.sub.TRACE-50B, L.sub.TRACE-44A, and L.sub.TRACE-44B are substantially equal, the impedance resonance frequencies 1/(2{square root over (L.sub.TRACE-50A*C.sub.PA-48)}) and 1/(2{square root over (L.sub.TRACE-50B*C.sub.PA-48)}) will each be higher than any of the impedance resonance frequencies 1/(2{square root over (L.sub.TRACE-44A*C.sub.PA-42A)}) and 1/(2{square root over (L.sub.TRACE-44B*C.sub.PA-42B)}). Thus, by utilizing the high-bandwidth power amplifier circuit 48 to amplify the high-bandwidth RF signal 52, as opposed to using any of the low-bandwidth power amplifier circuits 42A, 42B, it is possible to shift the disturbance energy spectrum 26 in
[0045] In this regard, the ETIC 34 further includes a control circuit 54. The control circuit 54, which can be a field-programmable gate array (FPGA) as an example, is configured to determine whether the ETIC 14 needs to operate with the high modulation bandwidth or the low modulation bandwidth. In response to determining that the ETIC 14 needs to operate within the high modulation bandwidth, the control circuit 54 is configured to couple each of the first ET voltage circuit 36A and the second ET voltage circuit 36B to a respective one of the auxiliary voltage outputs 40A, 40B. Accordingly, the auxiliary voltage outputs 40B will provide the first ET voltage V.sub.CCA and the second ET voltage V.sub.CCB, respectively, to the high-bandwidth power amplifier circuit 48. The control circuit 54 may also decouple the first ET voltage circuit 36A and the second ET voltage circuit 36B from any of the primary voltage outputs 38A, 38B, either concurrent to or after coupling the first ET voltage circuit 36A and the second ET voltage circuit 36B to the auxiliary voltage outputs 40A, 40B.
[0046] The ETIC 34 may include a switch circuit 56 that includes switches S.sub.A, S.sub.B, S.sub.AA, and S.sub.AB. In a non-limiting example, the switch S.sub.A is coupled between the first ET voltage circuit 36A and the primary voltage output 38A, the switch S.sub.B is coupled between the second ET voltage circuit 36B and the primary voltage output 38B, the switch S.sub.AA is coupled between the first ET voltage circuit 36A and the auxiliary voltage output 40A, and the switch S.sub.AB is coupled between the second ET voltage circuit 36B and the auxiliary voltage output 40B. In this regard, the control circuit 54 can close switches S.sub.AA, S.sub.AB and open switches S.sub.A, S.sub.B in response to determining that the ETIC 14 needs to operate with the high modulation bandwidth.
[0047] In contrast, in response to determining that the ETIC 14 needs to operate within the low modulation bandwidth, the control circuit 54 is configured to couple at least one of the first ET voltage circuit 36A and the second ET voltage circuit 36B to at least one of the primary voltage outputs 38A, 38B. The control circuit 54 may also decouple the first ET voltage circuit 36A and the second ET voltage circuit 36B from any of the auxiliary voltage outputs 40A, 40B, either concurrent to or after coupling the first ET voltage circuit 36A and the second ET voltage circuit 36B to the primary voltage outputs 38A, 38B. To do so, the control circuit 54 can open switches S.sub.AA, S.sub.AB and close at least one of switches S.sub.A, S.sub.B in response to determining that the ETIC 14 needs to operate with the low modulation bandwidth.
[0048] The control circuit 54 may be configured to determine whether the ETIC 14 needs to operate with the high modulation bandwidth or the low modulation bandwidth based on any of following embodiments. In one embodiment, the control circuit 54 may determine whether the ETIC 14 needs to operate with the high modulation bandwidth or the low modulation bandwidth based on any of the first target voltage V.sub.TGTA and the second target voltage V.sub.TGTB. In another embodiment, the control circuit 54 may also determine whether the ETIC 14 needs to operate with the high modulation bandwidth or the low modulation bandwidth based on a higher one of the first target voltage V.sub.TGTA and the second target voltage V.sub.TGTB. In another embodiment, the control circuit 54 may determine whether the ETIC 14 needs to operate with the high modulation bandwidth or the low modulation bandwidth based on presence or absence of the high-bandwidth RF signal 52 and/or presence or absence of the low-bandwidth RF signals 46A, 46B. In another embodiment, the control circuit 54 may determine whether the ETIC 14 needs to operate with the high modulation bandwidth or the low modulation bandwidth based on activation or deactivation of the high-bandwidth power amplifier circuit 48 and/or activation or deactivation of the low-bandwidth power amplifier circuits 42A, 42B. In another embodiment, the control circuit 54 may determine whether the ETIC 14 needs to operate with the high modulation bandwidth or the low modulation bandwidth by receiving an indication 58 from a transceiver circuit (not shown) that generates the high-bandwidth RF signal 52 and/or the low-bandwidth RF signals 46A, 46B. In yet another embodiment, the control circuit 54 may determine whether the ETIC 14 needs to operate with the high modulation bandwidth or the low modulation bandwidth based on any combination of the above-described embodiments.
[0049] The ETIC 14 may also include a first voltage equalizer circuit 60A and a second voltage equalizer circuit 60B (each denoted as VEQ). The first voltage equalizer circuit 60A is coupled to the first ET voltage circuit 36A and configured to equalize the first target voltage V.sub.TGTA based on a first transfer function H.sub.1(s). The second voltage equalizer circuit 60B is coupled to the second ET voltage circuit 36B and configured to equalize the second target voltage V.sub.TGTB based on a second transfer function H.sub.2(s).
[0050] In a non-limiting example, each of the first transfer function H.sub.1(s) and the second transfer function H.sub.2(s) can include a second-order complex-zero term and a real-zero term, which can reduce the voltage disturbance caused by any of the equivalent trance inductances L.sub.TRACE-50A, L.sub.TRACE-50B, L.sub.TRACE-44A, and L.sub.TRACE-44B. For further detail as to how the first transfer function H.sub.1(s) and the second transfer function H.sub.2(s) can be implemented in the first voltage equalizer circuit 60A and the second voltage equalizer circuit 60B with the second-order complex-zero term and the real-zero term, please refer to U.S. patent application Ser. No. 17/412,823, entitled EQUALIZER CIRCUIT AND RELATED POWER MANAGEMENT CIRCUIT.
[0051] The high-bandwidth power amplifier circuit 48 can be configured according to an embodiment as shown in
[0052] The high-bandwidth power amplifier circuit 48 includes a plus input stage 62 (denoted as PA.sub.P-IN) and a plus output stage 64 (denoted as PA.sub.P-OUT) each coupled to a first one of the auxiliary voltage outputs 40A, 40B (e.g., 40A). The high-bandwidth power amplifier circuit 48 also includes a minus input stage 66 (denoted as PA.sub.M-IN) and a minus output stage 68 (denoted as PA.sub.M-OUT) each coupled to a second one of the auxiliary voltage outputs 40A, 40B (e.g., 40B). The plus output stage 64 is coupled to a plus load capacitor C.sub.LOAD-P and the minus output stage 68 is coupled to a minus load capacitor C.sub.LOAD-M. The plus load capacitor C.sub.LOAD-P and the minus load capacitor C.sub.LOAD-M are provided to provide required RF capacitance to help provide RF isolation between input and output stages as well as to improve stability under large output voltage standing wave ratio (VSWR) handling. In a non-limiting example, the plus load capacitor C.sub.LOAD-P and the minus load capacitor C.sub.LOAD-M are configured to have an equal capacitance. Notably, the plus load capacitor C.sub.LOAD-P and the minus load capacitor C.sub.LOAD-M are each considered the predominant capacitance in the equivalent capacitance C.sub.PA-48 presented at the auxiliary voltage outputs 40A, 40B.
[0053] The low-bandwidth power amplifier circuits 42A, 42B can each be configured according to an embodiment as shown in
[0054] As shown in
[0055] In a non-limiting example, the plus load capacitor C.sub.LOAD-P and the minus load capacitor C.sub.LOAD-M are each configured to have a lower capacitance than the load capacitor C.sub.LOAD (e.g., C.sub.LOAD-P=C.sub.LOAD-M= C.sub.LOAD). As a result, the equivalent capacitance C.sub.PA-48 (a.k.a. the second equivalent capacitance) can become lower than both the equivalent capacitance C.sub.PA-42A and the equivalent capacitance C.sub.PA-42B (a.k.a. the first equivalent capacitance).
[0056] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.