TECHNIQUES FOR CONTROLLING AN AUTO-ZERO AMPLIFIER

Abstract

This disclosure describes auto-zero amplifier circuit that include an additional capacitor (or other capacitive component) that can be switchably coupler to a reference voltage. The auto-zero amplifier circuit can generate an auto-zero compensation signal using a difference between the reference voltage stored on the additional capacitor and a voltage stored on another auto-zero capacitor.

Claims

1. An auto-zero amplifier circuit to compensate for offset drift, the circuit comprising: a first amplifier circuit having a first input offset voltage; a first auto-zero capacitor configured to be switchably coupled to the first amplifier circuit using a first switch, the first auto-zero capacitor configured to store the first input offset voltage; and a second auto-zero capacitor configured to be switchably coupled using a second switch to a first reference voltage to store the first reference voltage, wherein the first amplifier circuit is configured to generate a first amplifier circuit compensation signal using a difference between the first input offset voltage stored on the first auto-zero capacitor and the first reference voltage stored on the second auto-zero capacitor.

2. The auto-zero amplifier circuit of claim 1, wherein the first amplifier circuit is configured to receive a differential input signal and generate a single-ended output signal.

3. The auto-zero amplifier circuit of claim 1, wherein the first auto-zero capacitor and the second auto-zero capacitor have the same capacitance.

4. The auto-zero amplifier circuit of claim 1, further comprising: a second amplifier circuit having a second input offset voltage; a third auto-zero capacitor configured to be switchably coupled to the second amplifier circuit using a third switch, the third auto-zero capacitor configured to store the second input offset voltage; and a fourth auto-zero capacitor configured to be switchably coupled using a fourth switch to a second reference voltage to store the second reference voltage, wherein the second amplifier circuit is configured to generate a second compensation signal using a difference between the second input offset voltage stored on the third auto-zero capacitor and the second reference voltage stored on the fourth auto-zero capacitor.

5. The auto-zero amplifier circuit of claim 4, wherein the first amplifier circuit is configured to receive a differential input signal and generate a single-ended output signal.

6. The auto-zero amplifier circuit of claim 4, wherein the first reference voltage is equal to the second reference voltage.

7. The auto-zero amplifier circuit of claim 4, wherein the first auto-zero capacitor and the second auto-zero capacitor have the same capacitance, and wherein the third auto-zero capacitor and the fourth auto-zero capacitor have the same capacitance.

8. The auto-zero amplifier circuit of claim 4, further comprising: a control circuit including an oscillator and configured to control operation of the first, second, third, and fourth switches, wherein an operation of the first and second switches is complementary to an operation of the third and fourth switches.

9. The auto-zero amplifier circuit of claim 1, further comprising: a fifth switch configured to connect first and second inputs of the first amplifier circuit to generate the first offset voltage at an output of the first amplifier circuit.

10. A method of compensating an auto-zero amplifier circuit for offset drift, the method comprising: coupling, using a first switch, a first auto-zero capacitor to a first amplifier circuit to store a first input offset voltage of the first amplifier circuit; coupling, using a second switch, a second auto-zero capacitor to a first reference voltage to store the first reference voltage; and generating a first compensation signal using a difference between the first input offset voltage stored on the first auto-zero capacitor and the first reference voltage stored on the second auto-zero capacitor.

11. The method of claim 10, further comprising: receiving a differential input signal and generating a single-ended output signal.

12. The method of claim 10, further comprising: receiving a differential input signal and generating a differential output signal.

13. The method of claim 10, wherein the first auto-zero capacitor and the second auto-zero capacitor have the same capacitance.

14. The method of claim 10, further comprising: a second amplifier circuit having a second input offset voltage; coupling, using a third switch, a third auto-zero capacitor to a second amplifier circuit, the second auto-zero capacitor configured to store the second input offset voltage; and coupling, using a fourth switch, a fourth auto-zero capacitor to a second reference voltage to store the second reference voltage, generating a second compensation signal using a difference between the second input offset voltage stored on the third auto-zero capacitor and the second reference voltage stored on the fourth auto-zero capacitor.

15. The method of claim 14, further comprising: receiving a differential input signal and generating a single-ended output signal.

16. The method of claim 14, further comprising: receiving a differential input signal and generating a differential output signal.

17. The method of claim 14, wherein the first reference voltage is equal to the second reference voltage.

18. The method of claim 14, further comprising: connecting, using a fifth switch, first and second inputs of the first amplifier circuit to generate the first offset voltage at an output of the first amplifier circuit.

19. An auto-zero amplifier circuit to compensate for offset drift, the circuit comprising: a first amplifier circuit having a first input offset voltage; means for storing a first input offset voltage of the first amplifier circuit; means for storing a first reference voltage, wherein the first amplifier circuit is configured to generate a first amplifier circuit compensation signal using a difference between the stored first input offset voltage and the stored first reference voltage.

20. The auto-zero amplifier circuit of claim 19, further comprising: a second amplifier circuit having a second input offset voltage; means for storing the second input offset voltage; and means for storing a second reference voltage, wherein the second amplifier circuit is configured to generate a second compensation signal using a difference between the stored second input offset voltage and the stored second reference voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document.

[0009] FIGS. 1A and 1B are schematic diagrams of an example of auto-zero amplifier circuit.

[0010] FIG. 2 is a schematic diagram of an example of an auto-zero amplifier circuit with improved immunity to offset drift.

[0011] FIG. 3 is a schematic diagram of another example of an auto-zero amplifier circuit with improved immunity to offset drift.

[0012] FIG. 4 is a schematic diagram of another example of an auto-zero amplifier circuit with improved immunity to offset drift.

DETAILED DESCRIPTION

[0013] To compensate for the non-ideal performance of CMOS or BJT operational amplifiers, auto-zeroing features can reduce offset voltage and gain errors. Due to various factors, such as temperature variation and/or noise coupling, the offset voltage of an operational amplifier can drift over time. The present inventors have recognized a need to be able to improve the immunity of the operational amplifier to offset drift due to temperature variation and noise coupling, for example.

[0014] Using various techniques of this disclosure, an additional capacitor (or other capacitive component) can be added to an auto-zero circuit and can be switchably coupled to a reference voltage. Then, the auto-zero amplifier circuit can generate an auto-zero compensation signal using a difference between the reference voltage stored on the additional capacitor and a voltage stored on another auto-zero capacitor. The present inventors have recognized that by using an additional capacitor in the auto-zero circuit to store the reference voltage to generate the compensation signal, rather than using the reference voltage directly to generate the compensation signal, the additional capacitor can leak current at a rate and in a manner similar to the auto-zero capacitor, which can negate the effects of the leakage due to the temperature variation and/or noise coupling.

[0015] FIGS. 1A and 1B are schematic diagrams of an example of auto-zero amplifier circuit. FIG. 1A depicts the example of an auto-zero amplifier circuit 10 in a first phase and FIG. 1B depicts the example of the auto-zero amplifier circuit 10 in a second phase. The auto-zero amplifier 10 of FIGS. 1A and 1B can include a nulling amplifier circuit 12, a main amplifier circuit 14, .sub.A switches that close in a first phase (Phase A) and open in a second phase (Phase B), and complementary .sub.B switches that open in the first phase (Phase A), and close in the second phase (Phase B). A control circuit 16 can include an oscillator and can control operation of the .sub.A switches and the .sub.B switches. The nulling amplifier 12 has an offset voltage of V.sub.OSA and the main amplifier 14 has an offset voltage of V.sub.OSB. The amplifier circuit 10 can receive a differential input signal V.sub.I+ and V.sub.I and generate an output signal V.sub.O.

[0016] In the first (or nulling) phase (Phase A) shown in FIG. 1A, the .sub.A switches are closed (and the .sub.B switches are opened) and the differential input signal V.sub.I+ and V.sub.I is applied to the main amplifier 14. In the nulling phase, the inputs of the nulling amplifier 12 are shorted together and to the inverting input terminal (common mode input voltage) of the nulling amplifier 12. The nulling amplifier 12 nulls its own offset voltage V.sub.OSA by feeding back to its nulling terminal whatever opposing voltage V.sub.NA is required to make the product of that voltage and the incremental gain of the nulling input approximately equal to the input offset voltage V.sub.OSA of the nulling amplifier 12. The nulling voltage is also stored on a first auto-zero capacitor C1. The auto-zero capacitor C1 is configured to store the input offset voltage V.sub.OSA and be switchably coupled to the nulling amplifier 12 using a .sub.A switch. Meanwhile, the main amplifier 14 operates like a normal op amp. The nulling voltage of the main amplifier 14 is supplied by the voltage stored on a second auto-zero capacitor C2. The auto-zero capacitor C2 is configured to store the input offset voltage V.sub.OSB and be switchably coupled to the main amplifier 14 using a .sub.B switch.

[0017] During the second (or output) phase (Phase B) shown in FIG. 1B, the .sub.B switches are closed (and the .sub.A switches are opened) and the inputs of the nulling amplifier 12 are connected to the input terminals of the main amplifier 14, which couples the differential input signal V.sub.I+ and V.sub.I to the inputs of the nulling amplifier 12. The auto-zero capacitor C1 continues to supply the nulling amplifier's required offset correction voltage. The differential input signal V.sub.I+ and V.sub.I is amplified by the nulling amplifier 12 and is further amplified by the incremental gain of the main amplifier's nulling input circuitry. The differential input signal V.sub.I+ and V.sub.I is also directly amplified by the gain of the main amplifier 14 itself.

[0018] The op amp feedback will cause the output voltage of the nulling amplifier 12 to be whatever voltage V.sub.NB is necessary at the main amplifier's nulling input to bring the main amplifier's input difference voltage to near-null. The output of the nulling amplifier 12 is also stored on the second auto-zero capacitor C2, which can hold that required voltage during the next Phase A. In Phase B, with its nulling voltage furnished by the first auto-zero capacitor C1, the nulling amplifier 12 amplifies the differential input signal V.sub.i+ and V.sub.I applied to the main amplifier 14 and applies the amplified voltage to the nulling input of the main amplifier and the capacitor C2.

[0019] To correct its offset voltage V.sub.OSA, the nulling amplifier 12 can generate a nulling amplifier compensation signal using a difference between the voltage V.sub.NA applied at its nulling terminal and a reference voltage \TREF. Similarly, to correct its offset voltage V.sub.OSB, the main amplifier 14 can generate a main amplifier compensation signal using a difference between the voltage V.sub.NB applied at its nulling terminal and a reference voltage V.sub.REF.

[0020] Due to various factors, such as temperature variation and/or noise coupling, the offset voltage of an operational amplifier can drift over time. For example, as the temperature increases, the auto-zero capacitor C1 can leak in phase B and the auto-zero capacitor C2 can leak in phase A, which can cause offset voltage drift. The present inventors have recognized a need to be able to improve the immunity of the operational amplifier to offset drift.

[0021] As described below, the present inventors have recognized that by using one or more additional capacitors in the auto-zero circuit to store a reference voltage to generate the compensation signal, rather than using the reference voltage directly to generate the compensation signal, the additional capacitor can leak current at a rate and in a manner similar to the auto-zero capacitor, which can negate the effects of the leakage due to the temperature variation and/or noise coupling.

[0022] FIG. 2 is a schematic diagram of an example of an auto-zero amplifier circuit with improved immunity to offset drift. The auto-zero amplifier 20 of FIG. 2 can include a nulling amplifier circuit 12, a main amplifier circuit 14, .sub.A switches that close in a first phase (Phase A) and open in a second phase (Phase B), and .sub.B switches that open in the first phase (Phase A), and close in the second phase (Phase B). A control circuit 22 can include an oscillator and can control operation of the .sub.A switches and the on switches. The nulling amplifier 12 has an offset voltage of V.sub.OSA and the main amplifier 14 has an offset voltage of V.sub.OSB. The amplifier circuit 10 can receive a differential input signal V.sub.I+ and V.sub.I and generate a single-ended output signal V.sub.O, for example. Components in FIG. 2 that are similar to components in FIGS. 1A and 1B are labeled with similar reference numbers and, for purposes of conciseness, will not be described in detail again. The amplifier circuits in this disclosure can be implemented using CMOS operational amplifiers or bipolar operational amplifiers.

[0023] The circuit 20 of FIG. 2 further includes two additional auto-zero capacitors, namely capacitors C3 and. C4. The operation of the switches coupled to auto-zero capacitors C1 and C3 can be complementary to the operation of the switches coupled to auto-zero capacitors C2 and C4.

[0024] During phase A, the control circuit 22 can control the .sub.A and .sub.B switches to couple the auto-zero capacitor C3 to a first reference voltage VREF1 and decouple the auto-zero capacitor C4 from a second reference voltage VREF2. During phase A, the auto-zero capacitor C3 can be charged to the first reference voltage VREF1. In this manner, the auto-zero capacitor C3 can store the first reference voltage VREF1, e.g., like a sample and hold operation. As described above with respect to FIG. 1A, the input offset voltage for the nulling amplifier 12 is stored on the auto-zero capacitor C1.

[0025] During phase B, the control circuit 22 can control the .sub.A and .sub.B switches to decouple the auto-zero capacitor C3 from the first reference voltage VREF1 and couple the auto-zero capacitor C4 to the second reference voltage VREF2. The input offset voltage of the auto-zero capacitor C1 is applied to the nulling input of the nulling amplifier 12. In addition, the first reference voltage VREF1 that was stored on the auto-zero capacitor C3 is applied to a reference voltage input of the nulling amplifier 12. The nulling amplifier 12 is configured to generate an amplifier circuit compensation signal using a difference between the input offset voltage (stored on the auto-zero capacitor C1) and the first reference voltage VREF1 (stored on the auto-zero capacitor C3). The nulling amplifier 12 can use the compensation signal to generate an error signal that can be injected into various nodes within the nulling amplifier circuitry to correct for the offset.

[0026] During phase B, the auto-zero capacitor C4 can be charged to the second reference voltage VREF2. In this manner, the auto-zero capacitor C4 can store the second reference voltage VREF2. As described above with respect to FIG. 1A, the input offset voltage for the main amplifier 14 is stored on the auto-zero capacitor C2.

[0027] During the next phase A, the control circuit 22 can control the .sub.A and .sub.B switches to couple the auto-zero capacitor C3 to the first reference voltage VREF1 and decouple the auto-zero capacitor C4 from the second reference voltage VREF2. The input offset voltage of the auto-zero capacitor C2 is applied to the nulling input of the main amplifier 14. In addition, the second reference voltage VREF2 that was stored on the auto-zero capacitor C4 can be applied to a reference voltage input of the main amplifier 14. The main amplifier 14 is configured to generate another amplifier circuit compensation signal using a difference between the input offset voltage (stored on the auto-zero capacitor C2) and the second reference voltage VREF1 (stored on the auto-zero capacitor C4). The main amplifier 14 can use the compensation signal to generate an error signal that can be injected into various nodes within the nulling amplifier circuitry to correct for the offset.

[0028] By storing the reference voltages on the additional capacitors C3, C4 and using those stored voltages to generate the compensation signal, rather than using the reference voltage directly to generate the compensation signal, the additional capacitors C3, C4 can leak current at a rate and in a manner similar to the auto-zero capacitors C1, C2 to negate the effects of the leakage, e.g., due to the temperature variation, noise coupling, etc. In some example implementations, the capacitance of the capacitor C3 can be substantially equal to the capacitance of the capacitor C 1, and the capacitance of the capacitor C4 can be substantially equal to the capacitance of the capacitor C2.

[0029] In some example configurations, the reference voltages VREF1 and VREF2 can be the same reference voltage. In other example configurations, the reference voltages VREF1 and VREF2 can be different reference voltages.

[0030] In some examples implementations, the amplifier circuit can be a differential input and single-ended out configuration, such as shown in FIG. 2, where an output terminal is referenced to ground. The techniques of this disclosure are also applicable to a differential input and differential output configuration, such as shown in FIG. 3.

[0031] FIG. 3 is a schematic diagram of another example of an auto-zero amplifier circuit with improved immunity to offset drift. The auto-zero amplifier circuit 30 of FIG. 3 is a fully differential configuration. The auto-zero amplifier circuit 30 includes two output terminals V.sub.O+ and V.sub.O. The amplifier circuit 30 can receive a differential input signal V.sub.I+ and V.sub.I and generate an output signal V.sub.OUT between the two output terminals V.sub.O+ and V.sub.O.

[0032] Although described above with respect to FIG. 2 as including two amplifier circuits, e.g., the nulling amplifier 12 and the main amplifier 14, the techniques of this disclosure are not limited to such configurations. Rather, an auto-zero amplifier circuit having a single amplifier circuit can implement various techniques of this disclosure, as shown in FIG. 4.

[0033] FIG. 4 is a schematic diagram of another example of an auto-zero amplifier circuit with improved immunity to offset drift. The auto-zero amplifier circuit 40 includes a single amplifier circuit 42, and switches that close in a first phase (Phase A, .sub.A) and open in a second phase (Phase B, .sub.B). The auto-zero amplifier circuit 40 can include two auto-zero capacitors C5 and C6. In some example implementations, the capacitance of the capacitor C6 can be substantially equal to the capacitance of the capacitor C5.

[0034] A control circuit 44 can include an oscillator and can control operation of the switches. The auto-zero amplifier circuit 40 can receive a differential input signal V.sub.I+ and V.sub.I and generate an output signal V.sub.O in the differential input, singled-ended output configuration of FIG. 4. In some example implementations, the amplifier circuit 40 can be implemented in a differential input, differential output configuration, such as shown in FIG. 3.

[0035] During phase A, the amplifier 42 is in its nulling period and can generate an offset compensation voltage V.sub.OSOUT to compensate for the offset voltage V.sub.OS present at the input terminals. The control circuit 44 can control switches to close (.sub.A position) and the auto-zero amplifier circuit 40 can store the offset compensation voltage V.sub.OSOUT on the auto-zero capacitor C5. With the switches closed, the auto-zero capacitor C6 can be coupled to the reference voltage VREF. During phase A, the auto-zero capacitor C6 can be charged to the reference voltage VREF. In this manner, the auto-zero capacitor C6 can store the reference voltage VREF1, e.g., like a sample and hold operation. During phase A, the output signal V.sub.O is not valid.

[0036] During phase B, the control circuit 44 can control the switches to open (.sub.B position). With the switches open, the voltage on the auto-zero capacitor C5 can be applied to a first nulling terminal V.sub.OSN of the amplifier 24 and the voltage on the auto-zero capacitor C6 can be applied to a second nulling terminal V.sub.OSP of the amplifier 42. Then, the amplifier circuit 42 can generate an auto-zero compensation signal using a difference between the reference voltage stored on the auto-zero capacitor C6 and the offset compensation voltage V.sub.OSOUT stored on the auto-zero capacitor C5. The output signal V.sub.O represents the signal amplified by the differential signal (V.sub.I+ minus V.sub.I) with the offset of the amplifier circuit 42 compensated by the capacitors C5 and C6.

[0037] By storing the reference voltage on the additional capacitor C6 and using that stored voltage to generate the compensation signal, rather than using the reference voltage directly to generate the compensation signal, the additional capacitor C6 can leak current at a rate and in a manner similar to the auto-zero capacitor C5 to negate the effects of the leakage, e.g., due to the temperature variation, noise coupling, etc.

Notes

[0038] Each of the non-limiting aspects or examples described herein may stand on its own or may be combined in various permutations or combinations with one or more of the other examples.

[0039] The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as examples. Such examples may include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0040] In the event of inconsistent usages between this document and any documents so incorporated by reference, the usage in this document controls.

[0041] In this document, the terms a or an are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of at least one or one or more. in this document, the term or is used to refer to a nonexclusive or, such that A or B includes A but not B, B but not A, and A and B, unless otherwise indicated. In this document, the terms including and in which are used as the plain-English equivalents of the respective terms comprising and wherein. Also, in the following claims, the terms including and comprising are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms first, second, and third, etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

[0042] Method examples described herein may be machine or computer-implemented at least in part. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods may include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code may include computer readable instructions for performing various methods. The code may form portions of computer program products. Further, in an example, the code may be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact discs and digital video discs), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.

[0043] The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. 1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description as examples or embodiments, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments may be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.