A Second-Order All-pass Network Comprising CCIIS

Abstract

A second-order all-pass network has at least three Second Generation Current Conveyors (CCIIs). A network input is connected or connectable to a Y port of a first CCII, a Z port of the first CCII is connected to a Y port of a second CCII, an X port of the first CCII is connected to a Y port of a third CCII, and a network output is connected or connectable, directly or indirectly, to a Z port of the second CCII. The X port of the first CCII is connected via a first network element to ground, the Z port of the first CCII is connected via a second network element to ground, an X port of the third CCII is connected via a third network element to ground, and an X port of the second CCII is connected via a fourth network element to ground.

Claims

1. A second-order all-pass network comprising: at least three Second Generation Current Conveyors (CCIIs), namely a first CCII, a second CCII, and a third CCII, wherein: a network input is connected or connectable to a Y port of the first CCII; a Z port of the first CCII is connected to a Y port of the second CCII; an X port of the first CCII is connected to a Y port of the third CCII; and a network output is connected or connectable, directly or indirectly, to a Z port of the second CCII, and a plurality of network elements, wherein: the X port of the first CCII is connected via a first network element to ground; the Z port of the first CCII is connected via a second network element to ground; an X port of the third CCII is connected via a third network element to ground; and an X port of the second CCII is connected via a fourth network element to ground.

2. The second-order all-pass network as claimed in claim 1, which is inductorless.

3. The second-order all-pass network as claimed in claim 1, which has a Q-value larger than 1.

4. The second-order all-pass network as claimed in claim 1, wherein the Y port of the second CCII is connected to the Z port of the second CCII.

5. The second-order all-pass network as claimed in claim 1, wherein the Y port of the third CCII is connected to the Z port of the third CCII.

6. The second-order all-pass network as claimed in claim 1, wherein one or more of the network elements comprise an RC (Resistor-Capacitor) network.

7. The second-order all-pass network as claimed in claim 6, wherein the RC network is a parallel RC network or a series RC network.

8. The second-order all-pass network as claimed in claim 6, wherein a resistor component in the RC network is implemented by an NMOS transistor.

9. The second-order all-pass network as claimed in claim 8, wherein the NMOS transistor is operated in a triode region.

10. The second-order all-pass network as claimed in claim 9, wherein operating in the triode region provides post-production tunability.

11. The second-order all-pass network as claimed in claim 6, wherein a capacitor component in the RC network is implemented by a varactor.

12. The second-order all-pass network as claimed in claim 1, which is implemented in a CMOS process.

13. The second-order all-pass network as claimed in claim 12, wherein the network elements are on-chip.

14. The second-order all-pass network as claimed in claim 12, wherein the network elements are tunable to compensate for CMOS process tolerances.

15. The second-order all-pass network as claimed in claim 1, comprising a fourth CCII.

16. The second-order all-pass network as claimed in claim 15, wherein the fourth CCII is configured for post-production tunability or wherein the fourth CCII enables post-production tunability of the second-order all-pass network.

17. The second-order all-pass network as claimed in claim 15, wherein a Y port of the fourth CCII is connected to the Z port of the second CCII.

18. The second-order all-pass network as claimed in claim 15, wherein a Z port of the fourth CCII is connected or connectable to the network output, the Z port of the third CCII thus being indirectly connected to the network output via the fourth CCII.

19. The second-order all-pass network as claimed in claim 18, wherein an X port of the fourth CCII is connected to the Z port of the fourth CCII.

20. A method of tuning the second-order all-pass network as claimed in claim 1, the method comprising tuning one or more of the network elements.

21. The method as claimed in claim 20, wherein the tuning the one or more of the network elements comprises iterative tuning passes in accordance with a pre-defined optimizer algorithm.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0028] The invention will now be further described, by way of example, with reference to the accompanying diagrammatic drawings.

[0029] In the drawings:

[0030] FIG. 1 shows a first embodiment of a second-order all-pass network comprising CCIIs, in accordance with the invention;

[0031] FIG. 2 show graphs of response characteristics of various effects of CCII non-idealities on the second-order all-pass network of FIG. 1: (a) non-unity Av vs. |H|, (b) non-unity Av vs. r, (c) non-unity Ai vs. |H|, (d) non-unity Ai vs. .sub.s, (e) non-zero R.sub.X vs. |H|, (f) non-zero R.sub.X vs. .sub.s, (g) finite R.sub.Z vs. |H|, (h) finite R.sub.Z vs. .sub.s, (i) finite R.sub.Y vs. |H|, (j) finite R.sub.Y vs. .sub.s, with the asterisk (*) denotes the all-pass network of FIG. 1. In all cases the solid curve represents the best-case response, where all the non-idealities are known beforehand and compensated for (if possible) in the selection of R and C values. The dotted curves on the other hand represent the response without any compensation for non-idealities (even if compensation is possible);

[0032] FIG. 3 shows graphs of trade-offs between the delay Q-value of the network of FIG. 1 and |H| for various CCII R.sub.X, R.sub.Z and R.sub.Y non-idealities. The solid curve represents the best-case response, and the dotted curves responses without any compensation for non-idealities (even if compensation is possible);

[0033] FIG. 4 shows a schematic circuit diagram of a CCII+ used in the all-pass network of FIG. 1;

[0034] FIG. 5 shows a second embodiment of a second-order all-pass network comprising CCIIs, in accordance with the invention;

[0035] FIG. 6 show corner and Monte Carlo simulations of the second-order all-pass network of FIG. 5;

[0036] FIG. 7 shows a noise simulation of the all-pass network of FIG. 5;

[0037] FIG. 8 shows a top view of a micrograph of the all-pass network of FIG. 5;

[0038] FIG. 9 shows a test PCB for housing and testing the all-pass network of FIG. 5;

[0039] FIG. 10 shows a post-production measurement and genetic optimisation setup for the all-pass network of FIG. 5;

[0040] FIG. 11 show simulated or measured outputs of: (a) measured voltage transfer curve of the all-pass network of FIG. 5, (b) measured and simulated group delay curves of the all-pass network of FIG. 5, (c) various metrics used in the calculation of the objective function versus the iteration for the all-pass network of FIG. 5, and (d) overall objective function versus the iteration for the all-pass network of FIG. 5; and

[0041] FIG. 12 shows measured input versus output sinusoid signals at 100 MHz, for the pass network of FIG. 5.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENT

[0042] The following description of the invention is provided as an enabling teaching of the invention. Those skilled in the relevant art will recognise that many changes can be made to the embodiment described, while still attaining the beneficial results of the present invention. It will also be apparent that some of the desired benefits of the present invention can be attained by selecting some of the features of the present invention without utilising other features. Accordingly, those skilled in the art will recognise that modifications and adaptations to the present invention are possible and can even be desirable in certain circumstances, and are a part of the present invention. Thus, the following description is provided as illustrative of the principles of the present invention and not a limitation thereof.

[0043] FIG. 1 illustrates a second-order all-pass network 100, in accordance with the invention. The all-pass network 100 comprises three CCIIs 102, 104, 106 and realises a generalized second-order transfer function. The components designated by Y.sub.1-Y.sub.4 are network elements as described below. The transfer function, considering non-unity Ai and Av, is:

[00002]$\begin{array}{cc}\frac{V_o}{V_i}=\frac{A_i.Math.A_v.Math.\left[Y_1-Y_3.Math.A_i.Math.A_v\right]}{Y_2-Y_4.Math.A_i.Math.A_v}.& \left(1\right)\end{array}$

[0044] A desired second-order all-pass transfer function can be written as:

[00003]$\begin{array}{cc}\frac{V_o}{V_i}=\frac{s_n^2-s_n/Q+1}{s_n^2+s_n/Q+1}=\frac{Y_N}{Y_D}& \left(2\right)\end{array}$

[0045] where s.sub.n=s/.sub.0, Q=. .sub.0/4, .sub.0=2f.sub.0 is a centre frequency of the second-order all-pass delay function, and is the corresponding peak-to-nominal group delay. Following the approach in [12], equation (2) can be written as:

[00004]$\begin{array}{cc}\frac{Y_N}{s_n\left(s_n+1\right)}=\frac{s_n^2-s_n/Q+1}{s_n\left(s_n+1\right)}.& \left(3\right)\end{array}$

[0046] After division and partial fraction decomposition, this becomes

[00005]$\begin{array}{cc}\frac{Y_N}{s_n+1}=s_n+1-\frac{s_n\left(2+1/Q\right)}{s_n+1}.& \left(4\right)\end{array}$

[0047] Similarly, for the denominator

[00006]$\begin{array}{cc}\frac{Y_D}{s_n+1}=s_n+1-\frac{s_n\left(2-1/Q\right)}{s_n+1}.& \left(5\right)\end{array}$

[0048] Equating terms in (4) and (5) with (1) and introducing a real scaling constant , the following set of equations can be derived:

[00007]$\begin{array}{cc}{A}_i.Math.A_v.Math.Y_1=\left(s_n+1\right).Math.,& \left(6\right)\\ Y_2=\left(s_n+1\right).Math.,& \left(7\right)\\ A_i^2.Math.A_v^2.Math.Y_3=\frac{s_n.Math.\left(2+1/Q\right)}{s_n+1},& \left(8\right)\\ Y_4.Math.A_i.Math.A_v=\frac{s_n.Math.\left(2-1/Q\right)}{s_n+1}.& \left(9\right)\end{array}$

[0049] Y.sub.1 and Y.sub.2 can be realized as a parallel RC network, and Y.sub.3 and Y.sub.4 as a series RC network, with:

[00008]$\begin{array}{cc}{R}_1=\frac{A_i.Math.A_v}{},C_1=\frac{}{A_i.Math.A_v.Math.{}_0},& \left(10\right)\\ R_2=\frac{1}{},C_2=\frac{}{{}_0},& \left(10\right)\\ R_3=\frac{A_i^2.Math.A_v^2}{\left(2+1/Q\right)},C_3=\frac{\left(2+1/Q\right)}{{}_0.Math.A_i^2.Math.A_v^2},& \left(10\right)\\ R_4=\frac{A_i.Math.A_v}{\left(2-1/Q\right)},C_4=\frac{\left(2-1/Q\right)}{{}_0.Math.A_i.Math.A_v},& \left(10\right)\end{array}$

[0050] where the subscripts of each network element Y correspond to those of the R and C components.

[0051] In the preceding derivation, CCII non-idealities other than A.sub.i and A.sub.v (specifically the critical parameter R.sub.X) are not considered, since equating terms in (4) and (5) with (1) then becomes impossible without applying an approximation. It is evident in FIG. 1 that R.sub.X of both the 2.sup.nd and 3.sup.rd CCIIs 104, 106 can be incorporated into the series R.sub.4 and R.sub.3, respectively, thus effectively compensating for its non-ideal effect. Perfect compensation for R.sub.X in the 1.sup.st CCII 102 is not possible; however, this may not be necessary for many practical cases (R.sub.X<30).

[0052] Next, the effects that CCII non-idealities have on the proposed design, as well as on other all-pass networks in the literature [8], [14], [15], [17]-[21], are investigated and compared. In each case, the transfer function of the all-pass network is derived, including the effect of the non-ideal constituent CCII parameters, and the numerical transfer response computed for variable values of different CCII non-idealities. In all cases, identical non-ideality is assumed for all CCIIs in the second-order network, with only one non-ideality swept at a time.

[0053] It may also be important to consider in this comparison to what degree the synthesis of the network (selection of R and C values) can be adapted to a priori known CC II non-idealities. It is evident from their respective transfer functions that non-ideal Ai can be compensated for in this work, as well as in [8], [14], [18], [19], [21] through appropriate selection of R and C values. Similarly, non-ideal A.sub.v can be compensated for and in [20] and R.sub.X in circuits [18]-[21]. In most or all cases, R.sub.Z and R.sub.Y cannot be perfectly compensated, but this is often not necessary for practical cases.

[0054] From each numerical transmission response calculation over frequency, two performance metrics are extracted. These are the magnitude response variation (|H|) and the group delay similarity, defined as:

.sub.s=.sub.0.sup.2.sup.0|.sub.ideal.sub.net|d/.sub.0.sup.2.sup.0|.sub.ideal|d,(11)

[0055] where .sub.ideal is the delay response with ideal CCIIs and .sub.net the non-ideal network response. A .sub.s=0 indicates that the two responses are identical whereas a .sub.s>0 indicates dissimilarity between the group delays. This definition captures both and .sub.0 deviations, as well as deviations from the ideal group delay curve shape. This is important to consider, as CCII non-idealities can disrupt a response of the all-pass network 100 to such an extent that the network's delay no longer resembles that of a second-order all-pass network. Finally, as all the considered networks are underdetermined (fewer bounding equations than R and C unknowns), the following component choices are made to ensure a fair comparison between the circuits, as shown in TABLE 1. In all cases C.sub.1=C.sub.2=C.

TABLE-US-00001 TABLE 1 component choices for inter-circuit comparison. All-pass Imposed Design Design Design network conditions eq. 1 eq. 2 eq. 3 [14] R.sub.2 = R.sub.3 = R.sub.4 = R R.sub.2 = R.sub.1 = /(Q.sup.2 A.sub.i) C = (A.sub.1.sup.2Q/(.sub.0) [15] R.sub.1 = R.sub.2 = /Q.sup.2 C = Q/(.sub.0) [17] R.sub.1 = R.sub.2 R.sub.1 = R.sub.3 = /Q.sup.2 C = Q/(.sub.0) [18] R.sub.1 = R.sub.2 = A.sub.i /Q.sup.2 C = Q/(.sub.0) [19] R.sub.2 = R.sub.3 R.sub.1 = R.sub.2 = A.sub.i /Q C = Q/(.sub.0) [20] R.sub.2 = 2R.sub.3 R.sub.3 = R.sub.1 = 4 /Q.sup.2 C = Q/(2.sub.0) [21] R.sub.2 = R.sub.3 R.sub.1 = R.sub.2 = A.sub.i /Q C = Q/(.sub.0)

[0056] The value for is chosen as 10.sup.3 (as this leads to a realisable resistance on-chip), Q is set as 2 and .sub.0 as 2..200.10.sup.6 (corresponding to design choices explained later). It is, however, reasonable to expect the general conclusions using these parameters to hold for other design choices as well.

[0057] For the all-pass network 100, as well as the network in [8], the design choices C.sub.1=/.sub.0, C.sub.2=(2+1/Q)/0, C.sub.3=2/.sub.0Q, R.sub.1=1/, R.sub.2=1/(.Math.(2+1/Q)), and R.sub.3=Q/2 are made. In both cases a is chosen as 10.sup.3, to ensure agreement to the component values in TABLE 1 for the other networks.

[0058] FIG. 2 shows |H| and .sub.s over the various CCII non-idealities. In each sub-figure, the solid curve represents the best-case response, where all the non-idealities are known beforehand and compensated for (if possible) in the selection of R and C values. The dotted curves on the other hand represent the response without any compensation for non-idealities (even if compensation is possible).

[0059] From FIG. 2a-2b, it can be seen that the proposed network 100 and the design in [20] are the only designs in which A.sub.v can be compensated for. For |H|<0.5 dB, designs [8], [15], [17] require A.sub.v precisions within 1.4% of unity, designs [18], [19], [21] A.sub.v precisions within 2.7% of unity, and design [14] an A.sub.v precision within 6% of unity (making it the design most resilient to CCII A.sub.v variation without explicit compensation applied). Achieving even this level of precision, however, requires a high-precision CCII with feedback control which complicates the design and reduces the achievable bandwidth [33]. This point is further illustrated later with a Monte Carlo analysis.

[0060] FIG. 2c-2d shows the benefit of the proposed design over the circuit in [20], since it allows for ideal compensation of A variation. In [20], Ai precision within 3% of unity is required for |H|<0.5 dBa value that is difficult to guarantee with CMOS CCIIsagain illustrated later with a Monte Carlo analysis.

[0061] In FIG. 2e-2f, the proposed design is shown to require R.sub.X<30 for |H|<0.5 dB, which is easily achievable with most CCIIs presented in the literature. In contrast, design [14] requires R.sub.X<13 and design [8] R.sub.X<4 for |H|<0.5 dB. This, again, necessitates high-precision CCIIs. Even though designs [18]-[21] can compensate for non-zero R.sub.X, they still require high-precision CCIIs to achieve the required A.sub.v and A.sub.i precisions, as was shown in FIG. 2a-2b.

[0062] FIG. 2g-2h indicates that for |H|<0.5 dB, the proposed design requires R.sub.Z>100 k, circuit [14] an R.sub.Z>66 k, designs [8], [19], [21] an R.sub.Z>50 k, and designs [15], [17], [18] an R.sub.Z>33 k. An 100 k can be achieved with a cascode current mirror. Even though current conveying bandwidth is reduced by a low R.sub.Z, its effect on CCII bandwidth is much smaller compared to the bandwidth reduction incurred by the feedback required in high-precision CCII designs.

[0063] Finally, FIG. 2i-2j indicates that a |H|<0.5 dB requires R.sub.Y>100 k for all the designs, a value achievable with many CCIIs. Given the ability to compensate for known non-ideal A.sub.i and A.sub.v, as well as the acceptable sensitivity to R.sub.X, R.sub.Y and R.sub.Z without the need for bandwidth-limiting high-precision CCIIs, the all-pass network 100 is more suitable for second-order delay network implementation than others analysed from literature.

[0064] FIG. 2 also illustrates the importance of post-production tunability of the R and C components to account for a postiori knowledge of CCII non-idealities. This need is exacerbated by other circuit non-idealities not captured by the above analysis, such as process tolerances and parasitic capacitances.

[0065] Finally, the effects of varying Q (and therefore ) on the response of the proposed compensated network are shown in FIG. 3, for different values of R.sub.X, R.sub.Y and R.sub.Z. There is scope for trade-off consideration in the choice of Q given a requirement for |H| (for instance R.sub.Y can be increased by decreasing the bias current through the current mirror). Such a trade-off, is on the other hand, difficult to achieve in passive soft-substrate designs without the use of active enhancement techniques.

[0066] The all-pass network 100 is suitable for monolithic integration in CMOS, e.g., 0.35 m CMOS technology node. The high-bandwidth, low-R.sub.X CCII presented in [34] with the characteristics A.sub.i0.976, A.sub.v=0.96, R.sub.X<20, R.sub.Y=25 and R.sub.Z35 k is used as the basis of the CCII design in the all-pass network 100. Even though higher-precision CCIIs have been reported, their design is complicated by necessary stability analyses and compensation networks [33]. Furthermore, the higher precision comes at the expense of lower bandwidth. Non-idealities of the chosen CCII lie within acceptable bounds and a bandwidth-precision trade-off is not necessary. A minimum theoretical magnitude variation of 2 dB can be achieved after compensation using the all-pass network 100, which is attributed mostly to R.sub.Y and R.sub.Z as per FIG. 2e-2j. The CCII used in the all-pass network 100 is presented in FIG. 4 with bias currents and transistor aspect ratios as given in TABLE 2.

TABLE-US-00002 TABLE 2 Transistor sizes chosen for devices in FIG. 4. W/L W/L W/L Device (MM/MM) Device (m/m) Device (m/m) M0 11/0.5 M8 10/1.95 M16 40/0.35 M1 10/1.95 M9 10/1.95 M17 40/0.35 M2 5/1.95 M10 20/0.35 M18 10/0.35 M3 18.9/0.75 M11 20/0.35 M19 10/0.35 M4 18.9/0.75 M12 30/0.35 M20 10/0.35 M5 18.9/0.75 M13 30/0.35 M21 10/0.35 M6 25/1.5 M14 30/0.35 M7 10/1.95 M15 30/0.35

[0067] Resistor R.sub.1 is chosen as 333 to ensure an M.sub.0 bias current of 150 A with V.sub.B1 set to 0 V. To establish a range of possible operating conditions of the CC II, a Monte Carlo analysis is performed on the circuit, leading to the performance characteristic range as shown in TABLE 3.

TABLE-US-00003 TABLE 3 performance characteristics of the CCII in FIG. 4. Parameter MEAN Standard deviation Minimum Maximum A.sub.v (V/V) 1.083 9.814 10.sup.3 1.062 1.114 A.sub.i (A/A) 0.992 6.306 10.sup.3 0.968 1.009 R.sub.X () 18.66 8.611 12 161 R.sub.Z (k) 70 26 23 125 R.sub.Y (k) 26 2.4 18 30

[0068] These simulation results agree well with values presented in the literature. Resistance R.sub.X is well within maximum bounds for successful compensation in most scenarios, as only 3% of the simulated 500 samples have R.sub.X of greater than 20 and only 1.4% have R.sub.X of greater than 30. The maximum achievable 3 dB transmission bandwidth (limited by the voltage transfer between ports Y and X) for the nominal corner is 500 MHz.

[0069] Having designed the CCII as in FIG. 4, the remainder of the proposed all-pass network is implemented as shown in FIG. 5, illustrated as a more development embodiment of a second-order all-pass network 200, in accordance with the invention. The following selection are made: f.sub.0=200 MHz and =7 ns. Component values are then calculated using (10), with chosen as 10.sup.3. Using the mean A.sub.v and A.sub.i from TABLE III, the synthesis results in R.sub.1=1074, R.sub.2=1 k, R.sub.3=470, R.sub.4=695, C.sub.1=0.74 pF, C.sub.2=0.80 pF, C.sub.3=1.69 pF, C.sub.4=1.15 pF. All resistors are implemented as NMOS devices operating in the triode region, where the bias voltages V.sub.R1-V.sub.R4 are chosen such that the effective channel resistance corresponds to R.sub.1-R.sub.4 above. The NMOS devices in FIG. 5 are chosen as (10 m/0.5 m) for M.sub.1,2 and (20 m/0.5 m) for M.sub.3,4, requiring nominal bias voltages of V.sub.R1=1.943 V, V.sub.R2=1.974 V, V.sub.R3=1.952 V, V.sub.R4=1.832 V.

[0070] Capacitors are implemented using accumulation-mode MOS varactors [35] which are tuned with gate bias voltages V.sub.C1-V.sub.C4 such that the effective capacitance values correspond to C.sub.1-C.sub.4 above. The peak capacitances of the varactors are chosen as C.sub.1p=C.sub.2p=1.8 pF and C.sub.3p=C.sub.4p=2.88 pF, allowing for a sufficient tuning range around the nominal values. Nominal bias voltages V.sub.C1=0.028 V, V.sub.C2=0.063 V, V.sub.C3=0.107 V, V.sub.C4=0.270 V are then required. Lastly, remaining bias values are set as in FIG. 4.

[0071] An additional voltage buffer stage (4th CCII+) is added to make the circuit capable of driving a 50 load impedance, as is required for the VNA measurement. A high-precision CCII as reported in [33] is used for this purpose.

[0072] After initial circuit synthesis and layout, a simulation of the proposed all-pass network 200 is performed using accurate non-ideal device models from the AMS foundry as well as extracted layout RC parasitics, as shown in FIG. 6. To compensate for the resulting change in circuit response, bias voltages are optimised (in simulation) using a global optimiser resulting in the solid black curve, as indicated. The optimised bias voltages are V.sub.R1=2.009 V, V.sub.R2=1.976 V, V.sub.R3=2.052 V, V.sub.R4=1.925 V, V.sub.C1=0.027 V, V.sub.C2=0.129 V, V.sub.C3=0.156 V, V.sub.C4=0.399 V, V.sub.B1=0.020 V. These values serve as the initial values for the automated tuning procedure during measurement. A corner simulation is also performed as indicated by the legend in FIG. 6a-6b, with the temperature swept from 0-85 C. in each corner (as indicated by the dotted grey or lighter curves). This serves to illustrate the large variation in response characteristics that can be expected without post-production tuning. A Monte Carlo simulation of the full circuit, analysing |H| and |H| over 500 samples, indicates that a magnitude flatness of 5.6 dB is most likely, which further justifies the proposed post-production tuning approach.

[0073] The power consumption of the second-order all-pass network 200 is simulated to be 37 mW (15 mW without the voltage buffer). A noise simulation is also performed, as shown in FIG. 7, indicating a nominal output noise of 22 nV/Hz, peaking at 62 nV/Hz at resonance.

[0074] The second-order all-pass network of FIG. 5 is manufactured using the C35B4 0.35 m CMOS process from AMS, as shown in the micrograph of FIG. 8. A PCB (Printed Circuit Board) is also designed to house the IC (Integrated Circuit) and supply the necessary bias voltages and RF (Radio Frequency) test signals, as shown in FIG. 9. Bondwires are used to connect the IC to the PCB pads. Power supply and DC (Direct Current) bias voltages are supplied by an IDC (Insulation-Displacement Contact) connector. The V.sub.in and V.sub.out terminals are routed to SMA (Sub-Miniature version C) connectors, which are connected to an Anritsu MS4640A VNA for measurements. To ensure wideband operation, decoupling capacitors are placed as close to the IC as possible (less than /10 at 500 MHz).

[0075] The overall measurement and post-production automated tuning setup is shown in FIG. 10. The pre-calibrated VNA captures 1001-point two-port S-parameter data and sends it to a computer running a genetic optimiser algorithm in MATLAB. The optimiser code extracts the transmission magnitude and group delay response from the S-parameters, and calculates the required bias voltage settings for the next measurement iteration. These values are programmed to an Analog Devices AD5370 DAC card connected to the computer via USB (Universal Serial Bus), and then applied to the DUT. A 500 MHz bandwidth digital oscilloscope is also used to monitor the input and output excitations.

[0076] Measured results are shown in FIG. 11 versus the genetic optimiser iteration. This particular IC falls roughly into the cmostmwn corner (as shown in FIG. 11a-11b)resulting in a much lower bandwidth than predicted by nominal operating conditions. As expected from the corner simulations, the initial response is far from the desired all-pass response with a magnitude variation of 15 dB. After running the optimiser for 4500 iterations, the magnitude variation is reduced to 3.1 dB with a 3 dB voltage transfer bandwidth of 280 MHz. The group delay f.sub.0=73 MHz and =10 ns, giving a Q-value of 1.15.

[0077] FIG. 11c shows the metrics used to calculate the overall objective function in FIG. 11d. The group delay similarity, .sub.s, as defined earlier, turns out to be important in correctly guiding the genetic optimiser to the correct minimum. The overall objective function is then a simple linear superposition of these components.

[0078] A time-domain measurement of the optimised circuit's output for an input sinusoid of 100 MHz is shown in FIG. 12 (filtered with a digital low-pass filter to remove noise), further confirming correct operation of the proposed circuit. The good agreement between the measured and simulated responses in the cmostmwn corner is clear.

[0079] The Applicant believes that a novel on-chip active second-order all-pass network 100, 200 is disclosed. The all-pass network 200 has post-production tunability to account for CCII non-idealities as well as CMOS process tolerances. The benefits of the proposed design over existing methods are quantified by comparative simulation. The method is implemented in a 0.35 m CMOS prototype design, and subjected to automated post-production tuning using a genetic local optimiser to realise a practical all-pass network. Good correspondence between simulated and measured responses is observed. This represents the first measured results of an active on-chip second-order all-pass network with a delay Q-value larger than 1 in published literature. A numerical comparison is provided in Table 4.

TABLE-US-00004 TABLE 4 comparison of present invention with published measured work. Magnitude f.sub.0 3 dB B/W Size Power variation Ref. Order Q (GHz) (GHz) Tech. # of L (mm.sup.2) (mW) (dB) This 2.sup.nd 1.15 0.073 0.280 0.35 m CMOS 0 0.0625 15 3.1 invn [25] 2.sup.nd 0.19 (0.59)*** 3 4 0.25 m CMOS 0 0.085 30 1.5 (>25) [23] 2.sup.nd 0.08 (0.52) 6 13 0.13 m CMOS 1 0.0627 18.5 0.5 (>13) [26] 2.sup.nd 0.071 6.5 16.5 0.09 m CMOS 0 [27] 2.sup.nd 0.049 (0.61) 6.3 12 0.13 m CMOS 1 16.5 1.5 (>10) [24] 2.sup.nd 0.047 6 7.5 SiGe BiCMOS HBT 1 0.49* 121 ~1 (f.sub.r = 95 GHz) [28] 2.sup.nd 0 0 12.2 0.16 m CMOS 0 0.15 450 1.4 (f.sub.0 = 0)** [29] 2.sup.nd 0 0 10 SiGeRF HBT 2 0.4197 38.8 2-2.5 (f.sub.0 = 0)** (f.sub.r = 80 GHz) [30] 2.sup.nd 0 0 4.38 0.18 m CMOS 0 0.0512 16.79 (f.sub.0 = 0)** [31] 2.sup.nd 0 0 >3 0.13 m CMOS 0 0.29 112 ~0.75 (f.sub.0 = 0)** *Including pads **constant delay with frequency ***values in brackets are computed over the entire bandwidth with the associated magnitude variation also shown in brackets.

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