Signal processor

Abstract

A signal processor and a method for processing an input signal are presented. The signal processor is adapted to clip an oversampled input signal without introducing noise in the frequency band of interest. For instance, the signal processor may be used for clipping an acoustic signal. The signal processor includes a summer coupled to a limiter and to a feedback circuit. The summer is adapted to sum the input signal with at least one feedback signal to provide an adjusted signal. The limiter is adapted to compare the adjusted signal with a first threshold value and a second threshold value to provide a limited signal. The feedback circuit is adapted to calculate a difference between the limited signal and the adjusted signal, and to generate at least one feedback signal based on the difference.

Claims

1. A signal processor for processing an input signal, the signal processor comprising a summer adapted to sum the input signal with at least one feedback signal to provide an adjusted signal; a limiter adapted to compare the adjusted signal with a first threshold value and a second threshold value to provide a limited signal; a feedback circuit adapted to calculate a difference between the limited signal and the adjusted signal, and to generate the said at least one feedback signal based on the difference.

2. The signal processor as claimed in claim 1, wherein the feedback circuit is adapted to provide an error signal such that when the adjusted signal is greater than the first threshold value, the error signal is equal to the adjusted signal minus the first threshold value; when the adjusted signal is less than the second threshold value, the error signal is equal to the adjusted signal minus the second threshold value; and when the adjusted signal is between the first threshold value and the second threshold value, the error signal is equal to a reference signal.

3. The signal processor as claimed in claim 2, wherein the feedback circuit is adapted to delay the error signal to generate the said at least one feedback signal.

4. The signal processor as claimed in claim 1, wherein when the adjusted signal is greater than the first threshold value, the limited signal is equal to the first threshold value; when the adjusted signal is less than the second threshold value, the limited signal is equal to the second threshold value; and when the adjusted signal is between the first threshold value and the second threshold value, the limited signal is equal to the adjusted signal.

5. The signal processor as claimed in claim 1, wherein the feedback circuit comprises a first subtractor adapted to subtract the first threshold value from the adjusted signal to provide a first error value and a second subtractor adapted to subtract the second threshold value from the adjusted signal to provide a second error value.

6. The signal processor as claimed in claim 5, wherein the feedback circuit comprises a multiplexer having a first input coupled to the first subtractor, a second input coupled to the second subtractor and a third input coupled to a reference source; the multiplexer being coupled to the summer via a first path comprising a first delay.

7. The signal processor as claimed in claim 6, wherein the said at least one feedback signal comprises a first feedback signal and a second feedback signal; the multiplexer being coupled to the summer via the first path and a second path; wherein the first path comprises a first gain element coupled to the first delay to generate the first feedback signal; and wherein the second path comprises the first delay, a second delay and a second gain element to generate the second feedback signal.

8. The signal processor as claimed in claim 1, comprising a quantizer to quantize the limited signal.

9. The signal processor as claimed in claim 8, wherein the feedback circuit is adapted to calculate a quantization error, wherein the said at least one feedback signal comprises the quantization error.

10. The signal processor as claimed in claim 9, wherein the feedback circuit comprises an output subtractor adapted to subtract an output of the quantizer from the limited signal to provide the quantization error, and an output summer adapted to sum the error signal with the quantization error to provide an adjusted error signal.

11. The signal processor as claimed in claim 1, wherein the input signal comprises a delta-sigma modulated signal.

12. The signal processor as claimed in claim 11, wherein the input signal comprises a pulse-code modulated signal.

13. A method of processing an input signal, the method comprising summing the input signal with at least one feedback signal to provide an adjusted signal; comparing the adjusted signal with a first threshold value and a second threshold value to provide a limited signal; calculating a difference between the limited signal and the adjusted signal; and generating the said at least one feedback signal based on the difference.

14. The method as claimed in claim 13, comprising generating an error signal, wherein when the adjusted signal is greater than the first threshold value, the error signal is equal to the adjusted signal minus the first threshold value; when the adjusted signal is less than the second threshold value, the error signal is equal to the adjusted signal minus the second threshold value; and when the adjusted signal is between the first threshold value and the second threshold value, the error signal is equal to a reference signal.

15. The method as claimed in claim 14, comprising delaying the error signal to generate the said at least one feedback signal.

16. The method as claimed in claim 14, wherein the said at least one feedback signal comprises a first feedback signal and a second feedback signal; the method comprising delaying the error signal to obtain a first delayed error signal and delaying the first delayed error signal to obtain a second delayed error signal, generating the first feedback signal based on the first delayed error signal and generating the second feedback signal based on the second delayed error signal.

17. The method as claimed in claim 14, comprising quantizing the limited signal.

18. The method as claimed in claim 17, comprising calculating a quantization error, wherein the said at least one feedback signal comprises the quantization error.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The disclosure is described in further detail below by way of example and with reference to the accompanying drawings, in which:

(2) FIG. 1A is a sinusoidal signal encoded using pulse code modulation;

(3) FIG. 1B is the spectrum of the signal of FIG. 1A;

(4) FIG. 2A is a sinusoidal signal encoded using sigma delta modulation;

(5) FIG. 2B is the spectrum of the signal of FIG. 2A obtained with and without clipping;

(6) FIG. 3 is a diagram of a signal processor according to the disclosure;

(7) FIG. 4 is an exemplary embodiment of the signal processor according to FIG. 3 provided with a first order feedback loop;

(8) FIG. 5A is a sinusoidal input signal processed using the circuit of FIG. 4;

(9) FIG. 5B is a series of three spectra: a first spectrum derived from an input signal; a second spectrum derived from the input signal processed using hard clipping and a third spectrum derived from the input signal processed using the circuit of FIG. 4;

(10) FIG. 6 is another exemplary embodiment of the signal processor according to FIG. 3 provided with a second order feedback loop;

(11) FIG. 7 is a series of three spectra: a first spectrum derived from an input signal; a second spectrum derived from the input signal processed using hard clipping and a third spectrum derived from the input signal processed using the circuit of FIG. 6;

(12) FIG. 8 is another exemplary embodiment of the signal processor according to FIG. 3 provided with a quantizer;

(13) FIG. 9 is a flow chart of a method for processing a signal.

DESCRIPTION

(14) FIG. 1A shows an example of a 1 kHz sinusoidal wave 110 encoded by PCM with no noise-shaping, along with clipping levels 120a and 120b. FIG. 1B shows the spectrum 130 of the signal 110 of FIG. 1A. In the audio band, the signal 110 is a single sinusoidal wave with a peak amplitude of 0.5 arbitrary units. There is no out-of-band noise present in the signal 110 and clipping the signal to +0.5 does not affect the signal.

(15) FIG. 2A shows an example of a 1 kHz sinusoidal wave 210 encoded by SDM and converted to a signal with the same number of quantization levels as a the PCM signal 110. The data or sample values locates above and below the threshold levels 120a and 120b are caused by out-of-band noise. FIG. 2B illustrates the spectrum 220 of the signal 210 obtained without clipping, and the spectrum 230 obtained by applying a hard limit to the input signal 210 and referred to as hard clipping. The spectrum 220 display significant noise above the audible region. When hard clipping is applied any sample values greater than the maximum threshold level 120a, in this example 0.5, are set to the maximum threshold level (0.5) and any sample values less than the minimum threshold level 120b, in this example 0.5 are set to the minimum threshold level (0.5). This results in a significant increase in the noise floor of the spectrum across a wide range of frequencies, including within the audible region between about 20 Hz to about 20 kHz, as evidenced by spectrum 230.

(16) FIG. 3 is a diagram of a signal processor for clipping or limiting an audio signal. The signal processor 300 includes a summer also referred to as input adder 310 coupled to a limiter 320 and to an error feedback circuit 330 also referred to as error feedback loop.

(17) In operation the signal processor 300 limits the input signal Sin to the limit levels defined by Max_val and Min_val. The feedback loop 330 calculates the difference between the output of the limiter and the input of the limiter for every sample and feed it back into the next sample. The adder 310 receives an input signal S.sub.in and an error feedback signal S.sub.fb from the error feedback loop to produce an adjusted signal S.sub.sum=S.sub.in+S.sub.fb. The limiter 320 receives the signal S.sub.sum and compares it with a maximum value Max_val and a minimum value Min_Val. The minimum and maximum values Max_val and Min_val may be programmable values. The limiter 320 is adapted to control the output signal value as follows. If S.sub.sum>Max_val, the limiter 320 provides an output signal S.sub.out=Max_val. If S.sub.sum<Min_Val, the limiter 320 provides an output signal S.sub.out=Min_val. If Max_valS.sub.sumMin_val, the limiter 320 outputs an output signal S.sub.out=S.sub.sum. The error feedback loop 330 receives the output signal S.sub.out from the limiter 320 and compares S.sub.out with S.sub.sum to generate the feedback signal S.sub.fb.

(18) Using the signal processor 300 permits to shift the noise introduced by clipping out-of band sample values such that it appears mainly out-of-band. For instance out-of-band noise may be the noise contained in frequencies outside the audio frequency band discernible by the human ear that is between about 20 Hz to about 20 kHZ.

(19) FIG. 4 is an exemplary embodiment of the signal processor of FIG. 3. The signal processor 400 includes an input adder 410 coupled to a limiter 420 and an error feedback circuit 430. The limiter 420 includes a data selector 422 implemented as a 3 to 1 multiplexer. The multiplexer 422, also referred to as clipping multiplexer, has a first input to receive the value Max_val, a second input to receive the value Min_val, and a third input to receive the signal S.sub.sum. The multiplexer 422 is also provided with a selection input to receive the signal S.sub.sum.

(20) The feedback loop circuit 430 includes two subtractors 432 and 434 and a reference source 435 coupled to the input channels of an error multiplexer 436; and a delay 438 coupled to the output of the error multiplexer. The first subtractor 432 has a first input to receive the signal S.sub.sum and a second input to receive the maximum threshold value Max_val. Similarly, the second subtractor 434 has a first input to receive the signal S.sub.sum and a second input to receive the minimum threshold value Min_val. The error multiplexer 436 has a first input to receive the output of the first subtractor 432 defined as S.sub.sumMax_val, a second input to receive the output of the second subtractor 434 defined as S.sub.sumMin_val, and a third input to receive a reference signal S.sub.ref from the reference source 435. For instance the reference signal may be a constant value such as a zero value or a small DC value. Alternatively the reference signal may vary over time. For instance the reference signal may include a high frequency component. The error multiplexer 436 is also provided with a selection input to receive the signal S.sub.sum. The output of the multiplexer 436 is coupled to a delay 438. The delay 438 may be a Z-domain delay cell. The input signal S.sub.in may be an audio signal encoded by sigma delta modulation SDM. This may be achieved using a sigma delta DAC. The delay 438 may be designed to implement a delay at the same rate as the sigma delta DAC.

(21) In operation the error multiplexer 436 receives the signal S.sub.sum at the selection input and provides an error signal S.sub.error, also referred to as clipping error signal, by selecting one of its three channel inputs. Stated another way the signal S.sub.sum is used as a selection signal to connect the desired channel input of the multiplexer to its output. If S.sub.sum>Max_val, the multiplexer 436 outputs an error signal S.sub.error=S.sub.sumMax_val. If S.sub.sum<Min_Val, the multiplexer 436 outputs an error signal S.sub.error=S.sub.sumMin_val. If Min_valS.sub.sumMax_val, the multiplexer 436 outputs an error signal S.sub.error=S.sub.ref, for example zero. The error signal S.sub.error is then delayed by the delay 438 to produce the feedback signal S.sub.fb. The feedback signal S.sub.fb is then fed to the adder 410 to produce the signal S.sub.sum=S.sub.in+S.sub.fb.

(22) The clipping multiplexer 422 receives the threshold values Max_val and Min_val at its first and second input channels respectively. The signal S.sub.sum is received at the third channel input and the selection input. If S.sub.sum>Max_val, the multiplexer 422 provides an output signal S.sub.out=Max_val. If S.sub.sum<Min_Val, the multiplexer 422 provides an output signal S.sub.out=Min_val. If Max_valS.sub.sumMin_val, the multiplexer 422 provides an output signal S.sub.out=S.sub.sum.

(23) FIG. 5A shows an example of a 1 kHz sinusoidal wave 510 encoded by SDM and processed using the circuit of FIG. 4. FIG. 5B shows the spectrum 530 of the input signal 510 processed using the circuit of FIG. 4. For comparison the spectra 220 and 230 described in FIG. 2B are also presented. Within the audible region, the noise floor of the spectrum 530 has decreased significantly compared with the noise floor of the spectrum 230. For instance at 100 Hz the noise floor of the spectrum 530 is about 390 dB compared with about 230 dB for spectrum 230. Therefore in-band noise has been reduced significantly compared with the level of noise introduced by applying a hard limit to the input signal. However the noise floor of spectrum 530 remains higher than the noise floor of spectrum 220. The proposed signal processor 400 may be considered as a circuit with a first order feedback loop. Further noise reduction can be obtained by implementing higher orders of feedback.

(24) FIG. 6 shows a signal processor provided with a second order feedback loop. The processor 600 is similar to the processor 400 described with reference to FIG. 4, in which certain parts of the circuit have been added/modified. Components which are same or similar to the processor 400 are described using the same reference numerals and their description will not be repeated for sake of brevity. The circuit 600 includes an adder 610 coupled to a limiter 420 as described with respect to FIG. 4 and a second order feedback loop 630. The second order feedback loop 630 includes the subtractors 432 and 434 coupled to the error multiplexer 436. The output of the error multiplexer 436 is coupled to the adder 610 via a firth feedback path to provide a first feedback signal S.sub.fb1 and a second feedback path to provide a second feedback signal S.sub.fb2. The first feedback path is formed by a first delay 642 coupled to a gain element 644. The second feedback path is formed by the first delay 642 coupled in series with a second delay 646 and a second gain element 648.

(25) In operation, the error multiplexer 436 provides an error signal S.sub.error as explained above with reference to FIG. 4. The error signal S.sub.error is delayed by a first period by the delay 642 and its amplitude adjusted by the gain element 644 to produce the first feedback signal S.sub.fb1. The error signal S.sub.error is also further delayed by an additional second period by the delay 646 and its amplitude adjusted by the gain element 648 to produce the second feedback signal S.sub.fb2. The adder 610 then receives the feedback signals S.sub.fb1 and S.sub.fb2 to provide the adjusted signal S.sub.sum=S.sub.in+S.sub.fb1+S.sub.fb2.

(26) The first gain of the gain elements 644, referred to as Error Feedback Gain 1, and the second gain of the gain element 648, referred to as Error Feedback Gain 2 may be programmable. The first gain and the second gain may be set by considering the first and second feedback paths as a filter. For instance the publication titled The Implementation of Recursive Digital Filters for High-Fidelity Audio by Jon Dattorro, Journal of Audio Engineering Society, Volume 36, Number 11, November 1988 describes how noise-shaping coefficients may be chosen in a normal biquad filter. A similar approach may be applied for selecting the gains of gains elements 644 and 648. Alternatively the gains may be limited to integers, allowing for efficient hardware implementation.

(27) Following the same principle as described above, higher orders feedback loops may be implemented. For instance a third order feedback loop may be implemented with three feedback path, each path providing its own feedback signal. This could be implemented using three delays and three gain elements to produce three feedback signals fed to the adder.

(28) FIG. 7 shows the spectrum 730 derived from an input signal processed using the circuit of FIG. 6. For comparison the spectra 220 (without clipping) and 230 (with hard clipping) described in FIG. 2B are also presented. By setting the gains of elements 644 and 648 as Error Feedback Gain 1=2 and Error Feedback Gain 2=1, the spectrum 730 of the example input signal results in a noise profile very close to the modulated input 220.

(29) The signal processors of FIGS. 3, 4 and 6 may be modified to quantise the processor output such that it uses a different number of quantization levels than the input.

(30) FIG. 8 shows a modified version of the processor of FIG. 4. Components which are same or similar to the processor 400 are described using the same reference numerals and their description will not be repeated for sake of brevity.

(31) The circuit 800 includes an input adder 410 coupled to a limiter 820 and to a feedback circuit 830. The limiter 820 includes a clipping multiplexer 422 coupled to a quantizer 824. The feedback circuit 830 includes the error subtractors 432 and 434 coupled to the error multiplexer 436, an output subtractor 832 and an output adder 834. The output subtractor 832 is coupled to the output of the clipping multiplexer 422 and to the output of the quantizer 824. The output adder 834 is coupled to the output of the output subtractor 832 and to the output of the error multiplexer 436. The output adder 834 is coupled to the delay 438 to produce the feedback signal S.sub.fb.

(32) In operation the output signal S.sub.out provided by the clipping multiplexer 422 is received by the quantizer 824 to provide a quantized output signal S.sub.out. The output subtractor 832 receives the signals S.sub.out and S.sub.out to generate the quantization error signal S.sub.error=S.sub.outS.sub.out indicative of quantization noise between the quantized signal and the original signal. The output adder 834 receives the clipping error signal S.sub.error from the error multiplexer 436 and the quantization error signal S.sub.error from adder 832 and provides a total error signal S.sub.error=S.sub.error+S.sub.error. The total error signal S.sub.error is then delayed by delay 438 to generate the feedback signal S.sub.fb. Using this approach the quantization error is included into the error feedback path.

(33) FIG. 9 is a flow chart of a method for processing a signal such an audio signal. At step 910 the input is summed with one or more feedback signals to provide an adjusted signal. The input signal may be an oversampled signal such as an SDM modulated signal. At step 920 the adjusted signal is compared with a first threshold value and a second threshold value to provide a limited signal. At step 930 a difference is calculated between the limited signal and the adjusted signal. At step 940 one or more feedback signals are generated based on the calculated difference.

(34) To provide the one or more feedback signals an error signal may be generated as follows. The adjusted signal has an amplitude that varies with time. When the adjusted signal has an amplitude greater than the first threshold value, the error signal is equal to the adjusted signal minus the first threshold value. When the adjusted signal has an amplitude less than the second threshold value, the error signal is equal to the adjusted signal minus the second threshold value; and when the adjusted signal has an amplitude between the first threshold value and the second threshold value, the error signal is equal to a reference signal. For instance the reference signal may be a pre-set constant value, for example a zero value. Alternatively the reference signal may vary over time. For instance, the reference signal may have a high frequency component. Using this approach, an oversampled input signal can be clipped while limiting the introduction of noise in the frequency band of interest.

(35) A skilled person will appreciate that variations of the disclosed arrangements are possible without departing from the disclosure. Accordingly, the above description of the specific embodiment is made by way of example only and not for the purposes of limitation. It will be clear to the skilled person that minor modifications may be made without significant changes to the operation described.