Stacked III-V semiconductor component

Abstract

A stacked III-V semiconductor component having a stack with a top, a bottom, a side surface, and a longitudinal axis. The stack has a p.sup.+ region, an n.sup. layer, and an n.sup.+ region. The p.sup.+ region, the n.sup. layer, and the n.sup.+ region follow one another in the specified order along the longitudinal axis and are monolithic in design, and include a GaAs compound. The n.sup.+ region or the p.sup.+ region is a substrate layer. The stack has, in the region of the side surface, a first and a second peripheral, shoulder-like edge. The first edge is composed of the substrate layer; the second edge is composed of the n.sup. layer or of an intermediate layer adjacent to the n.sup. layer and to the p.sup.+ region and the first and the second peripheral edges each have a width of at least 10 m.

Claims

1. A stacked III-V semiconductor component comprising: a stack with a top, a bottom, a side surface connecting the top and the bottom, and a longitudinal axis extending through the top and the bottom, wherein the stack has a p.sup.+ region with a top, a bottom, and a dopant concentration of 5.Math.10.sup.18-5.Math.10.sup.20 N/cm.sup.3, wherein the stack has an n.sup. layer with a top and a bottom, a dopant concentration of 10.sup.12-10.sup.17 N/cm.sup.3, and a layer thickness of 10-300 m, wherein the stack has an n.sup.+ region with a top, a bottom, and a dopant concentration of at least 10.sup.19 N/cm.sup.3, wherein the p.sup.+ region, the n.sup. layer, and the n.sup.+ region follow one another along the longitudinal axis of the stack, and are each monolithic in design, and each include a GaAs compound or are each made of a GaAs compound, and wherein the n.sup.+ region or the p.sup.+ region is a substrate layer, wherein the stack has, in a region of the side surface, a first peripheral, shoulder-like edge and a second peripheral, shoulder-like edge, wherein the first edge is composed of the substrate layer, wherein the second edge is composed of the n.sup. layer or of an intermediate layer adjacent to the n.sup. layer and to the p.sup.+ region, and wherein the first peripheral edge and the second peripheral edge each have a width of at least 10 m.

2. The stacked III-V semiconductor component according to claim 1, wherein a first insulating layer created by implantation is formed in the stack at least along a part of the side surface of the stack.

3. The stacked III-V semiconductor component according to claim 1, wherein a second insulating layer extends at least along a part of the side surface of the stack.

4. The stacked III-V semiconductor component according to claim 1, wherein the semiconductor component includes a first contact layer and a second contact layer, wherein the second contact layer partially covers the top of the stack, and the top of the stack forms a third peripheral edge with a width of at least 10 m around the second contact layer.

5. The stacked III-V semiconductor component according to claim 1, wherein the p.sup.+ region and the n.sup.+ region are implemented in layer form, wherein the n.sup.+ region in layer form and the p.sup.+ region in layer form are each integrally joined to the n.sup. layer, wherein the n.sup.+ region in layer form has a layer thickness of 50-675 m, wherein the p.sup.+ region in layer form has a layer thickness greater than 2 m, wherein the stacked III-V semiconductor component has a first defect layer with a layer thickness between 0.5 m and 50 m, and wherein the defect layer is located within the n.sup. layer and has a defect density in a range between 1.Math.10.sup.13 N/cm.sup.3 and 5.Math.10.sup.16 N/cm.sup.3.

6. The stacked III-V semiconductor component according to claim 1, wherein a distance of the defect layer from a boundary layer between the n.sup. layer and the p.sup.+ region is equal to a maximum of half the layer thickness of the n.sup. layer.

7. The stacked III-V semiconductor component according to claim 1, wherein the p.sup.+ region and the n.sup.+ region are implemented in layer form, wherein the n.sup.+ region in layer form is integrally joined to the n.sup. layer, wherein a doped intermediate layer with a layer thickness of 1-50 m and a dopant concentration of 10.sup.12-10.sup.17 cm.sup.3 is arranged between the n.sup. layer and the p.sup.+ layer, and wherein the intermediate layer is integrally joined to the n.sup. layer and to the p.sup.+ layer.

8. The stacked III-V semiconductor component according to claim 1, wherein the III-V semiconductor diode is monolithic or has a semiconductor bond.

9. The stacked III-V semiconductor component according to claim 8, wherein the semiconductor bond is formed between the p.sup. layer and the n.sup. layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein:

(2) FIG. 1 shows a schematic view of an embodiment according to the invention of a semiconductor component,

(3) FIG. 2 shows a schematic cross-sectional view of the layer sequence of an embodiment according to the invention of a semiconductor component, and

(4) FIG. 3 shows a schematic cross-sectional view of the layer sequences of an embodiment according to the invention of a semiconductor component.

DETAILED DESCRIPTION

(5) The illustration in FIG. 1 schematically shows a perspective view of an embodiment of a stacked III-V semiconductor component 10 according to the invention.

(6) The semiconductor component 10 has a stack 100 that includes multiple semiconductor layers and that has a rectangular top 102, a rectangular bottom 104, and a side surface 106 connecting the top 102 and the bottom 104. The bottom 104 is larger than the top 102. The side surface 106 is formed of four stepped surfaces, so that a first peripheral, shoulder-like edge 110 with a first width B1 and a second peripheral, shoulder-like edge with a second width B2 are formed in the region of the side surface 106.

(7) The bottom 104 of the stack 100 is completely covered by a first contact layer K1. A second contact layer K2 is located on the top 102 of the semiconductor component 10.

(8) A first embodiment of the layer sequence of the semiconductor layers of the stack 100 of the semiconductor component 10 is shown in the illustration in FIG. 2.

(9) The stack 100 has, along a longitudinal axis L, a p.sup.+ region 12 in layer form with a dopant concentration of 5.Math.10.sup.18-5.Math.10.sup.20 N/cm.sup.3, an n.sup. layer with a dopant concentration of 10.sup.12-10.sup.17 N/cm.sup.3, and an n.sup.+ region in layer form with a dopant concentration of at least 10.sup.19 N/cm.sup.3, wherein each layer has a bottom and a top.

(10) The p.sup.+ layer 12 is implemented as a substrate with a layer thickness D1, wherein the bottom of the p.sup.+ layer 12 constitutes the bottom of the stack 100. A first part of the top of the p.sup.+ layer 12 constitutes the peripheral first edge 110 with the width B1. Located on a second part of the top of the p.sup.+ layer 12 is the bottom of the n.sup. layer 14. The n.sup. layer 14 has a layer thickness D2. A part of the top of the n.sup. layer constitutes the peripheral second edge 130 with a width B2. Located on a second part of the top of the n.sup. layer 14 is the bottom of the n.sup.+ layer 16. The n.sup.+ layer 16 has a layer thickness D3. The top of the n.sup.+ layer 16 constitutes the top of the stack 100.

(11) The bottom of the stack 100 is completely covered by the first contact layer K1. The second contact layer K2 is formed in a planar manner on a central region of the top of the stack 100 so that the top of the stack 100, which is to say the n.sup.+ layer 16 here, forms a third peripheral, shoulder-like edge 130 with a width B3.

(12) All layers 12, 14, and 16 are monolithic in design, and include a GaAs compound or are made of a GaAs compound. Optionally, and shown in dashed lines for this reason, the stack 100 has a defect layer 30 with a layer thickness D4, wherein the defect layer is located within the n.sup. layer 14 and has a distance A1 from the bottom of the n.sup. layer 14 or the top of the p.sup.+ layer 12.

(13) Another embodiment of a layer sequence according to the invention of the III-V semiconductor component is shown in the illustration in FIG. 3. Only the differences from the illustration in FIG. 2 are explained below.

(14) The n.sup.+ layer 16 is implemented as a substrate layer, followed by the p.sup. layer 14, a p-doped or n-doped intermediate layer 18 with a layer thickness D5, and the p.sup.+ layer 12.

(15) A region of the stack 100 adjacent to the side surface from the first peripheral edge 110 to an edge adjacent to the top of the stack 100 is made insulating through implantation, and forms a first insulating layer 20.

(16) A second insulating layer 22, for example an oxide layer or a combination of an oxide layer and a nitride layer, is applied by means of chemical vapor deposition to the side surfaces in the region from the first peripheral edge 110 to an edge adjacent to the top of the stack 100. In this case the insulating layer 22 can extend as far as the surface 102.

(17) The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims