Abstract
A method for producing a connection between component parts and a component made of component parts are disclosed. In an embodiment, a includes providing a first component part having a first exposed insulation layer and a second component part having a second exposed insulation layer, wherein each of the insulation layers has at least one opening, joining together the first and second component parts such that the opening of the first insulation layer and the opening of the second insulation layer overlap in top view, wherein an Au layer and a Sn layer are arranged one above the other in at least one of the openings and melting the Au layer and the Sn layer to form an AuSn alloy, wherein the AuSn alloy forms a through-via after cooling electrically conductively connecting the first component part to the second component part.
Claims
1-20. (canceled)
21. A method for producing an electrical connection between a first component part and a second component part, the method comprising: providing the first component part having a first exposed insulation layer and the second component part having a second exposed insulation layer, wherein each of the insulation layers has at least one opening; joining together the first and second component parts such that the opening of the first insulation layer and the opening of the second insulation layer overlap in top view, wherein an Au layer and a Sn layer are arranged one above the other in at least one of the openings; and melting the Au layer and the Sn layer to form an AuSn alloy, wherein the AuSn alloy forms a through-via after cooling electrically conductively connecting the first component part to the second component part.
22. The method according to claim 21, wherein each of the first insulation layer and the second insulation layer has a planarized exposed surface outside of the opening, and wherein the first and second components part are mechanically connected to one another using a direct bonding process at a common interface between the planarized surfaces.
23. The method according to claim 22, wherein the first and second component parts are mechanically joined together when they are brought together, and wherein melting the Au layer and the Sn layer follows mechanically joining the first and second component parts.
24. The method according to claim 21, wherein the Au layer and the Sn layer are integral parts of a connecting stack which has an overall vertical height smaller than an overall vertical depth of the associated opening in which the connecting stack is arranged.
25. The method according to claim 21, wherein a first opening of the first insulation layer and a second opening of the second insulation layer form a common sealed cavity when the first and second component parts are joined together, wherein, in each of the openings, one connecting stack comprising at least the Au layer and the Sn layer is arranged.
26. The method according to claim 25, wherein the connecting stacks arranged in the openings are spaced apart from one another by an intermediate space prior to melting and are in direct mechanical contact with one another at first during melting.
27. The method according to claim 21, wherein a barrier layer is arranged at least in places between the Au layer and the Sn layer in a vertical direction, and wherein the barrier layer is formed from a material whose melting temperature is higher than that of Au and/or Sn.
28. The method according to claim 27, wherein the Au layer or the Sn layer in the associated opening of the insulation layer is completely enclosed by the barrier layer, wherein the barrier layer comprises titanium or platinum, and wherein the through-via is an AuSn eutectic formed in one piece and has traces of the barrier layer made of titanium or platinum.
29. The method according to claim 21, wherein, prior to joining together the first and second component parts, the Au layer and the Sn layer are covered by an exposed protective layer, and wherein the protective layer is formed from a material whose mechanical hardness is greater than that of Au and/or Sn.
30. The method according to claim 29, wherein the protective layer comprises Au, Cu, Ni, Ti, Al or a combination of Au, Cu, Ni, Ti and/or Al.
31. The method according to claim 21, wherein a mask comprising at least one opening is formed on the first or second insulation layer, wherein the opening of the first or second insulation layer is formed in a region of the opening of the mask such that at an interface between the mask and the insulation layer, the opening having a larger cross-section than the associated opening of the mask, wherein, in a lateral direction, the mask in places projects beyond an inner wall of the opening and in top view covers the opening of the insulation layer in places, wherein a connecting stack containing the Au layer and the Sn layer is applied layer by layer and over a large area onto the first or second component part, and wherein a lateral intermediate space is located between the connecting stack located in the opening and the insulation layer.
32. A component comprising: a first component part; a second component part; and a through-via, wherein the first component part has a first insulation layer and the second component part has a second insulation layer, wherein the through-via is an AuSn alloy and electrically conductively connects the first component part to the second component part, and wherein the through-via is arranged in a first opening of the first insulation layer and in a second opening of the second insulation layer and is completely enclosed in lateral directions by both the first insulation layer and the second insulation layer.
33. The component according to claim 32, wherein the openings form a common closed cavity, wherein the cavity has a greater lateral extent than the through-via at least in places so that the through-via only partially fills the cavity, and wherein an interspace is located in the lateral direction between the through-via and the insulation layers.
34. The component according to claim 32, wherein the through-via is an AuSn eutectic which is formed in one piece and comprises traces of titanium or platinum.
35. The component according to claim 32, wherein the first component part is a radiation-inactive carrier wafer and the second component part is a semiconductor wafer comprising a radiation-active layer.
36. The component according to claim 32, wherein the first component part is a radiation-inactive carrier wafer and the second component part is a semiconductor chip.
37. The component according to claim 32, wherein a plurality of second component parts comprises semiconductor chips fixed side by side on the first component part.
38. The component according to claim 32, wherein the first insulation layer and the second insulation layer comprise SiO.sub.2.
39. The component according to claim 32, wherein the openings form a common closed cavity, and wherein, at least in places, the cavity has a larger lateral extent than the through-via so that the through-via only partially fills the cavity.
40. The component according to claim 32, wherein the through-via is an AuSn eutectic which is formed in one piece and comprises traces of Cu, Ni, Ti and/or Al.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0037] Other preferred embodiments and further developments of the component and of the method will become apparent in the exemplary embodiments explained:
[0038] FIGS. 1A, 1B, 1C, 1D, 1E, 1F and 1G show an embodiment of a method for forming a mechanical and electrical connection between the component parts in schematic sectional views;
[0039] FIGS. 2A and 2B show schematic illustrations of some method steps of a further exemplary embodiment of a method for establishing a mechanical and electrical connection between the component parts;
[0040] FIGS. 3A, 3B and 3C show schematic illustrations of some further method steps of a further exemplary embodiment of a method for producing a component or an assembly of component parts;
[0041] FIGS. 4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H and 4I show schematic illustrations of some method steps of a further exemplary embodiment of a method for establishing a mechanical and electrical connection between the component parts; and
[0042] FIGS. 5A, 5B, 6A and 6B show schematic illustrations of some further method steps of a further exemplary embodiment of a method for producing an assembly or a component made of a plurality of component parts.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
[0043] Identical, equivalent or equivalently acting elements are indicated with the same reference numerals in the figures. The figures are schematic illustrations and thus not necessarily true to scale. Comparatively small elements and particularly layer thicknesses can rather be illustrated exaggeratedly large for the purpose of better clarification.
[0044] FIG. 1A schematically shows a first component part 1 and a second component part 2 in sectional view. The component part 1 or 2 has a carrier 1T or 2T. The component part 1 or 2 has a first insulation layer 1I or a second insulation layer 2I, wherein the insulation layer 1I or 2I is located on the carrier 1T or 2T. The component part 1 or 2 may have a main body 1H or 2H, wherein the main body 1H or 2H is disposed in the vertical direction between the carrier 1T or 2T and the insulation layer 1I or 2I.
[0045] The second component part 2 may be a semiconductor wafer. In particular, the component part 2 can have a carrier 2T, for example made of sapphire, on which the main body 2H, which is in particular a semiconductor body, is arranged. The main body 2H can be applied to the carrier 2T by an epitaxial process, wherein the carrier 2T is in particular a growth substrate. The main body 2H may have a semiconductor body which is based, for example, on a III-V or on a II-VI compound semiconductor material. In particular, the main body 2H has a radiation-active layer 23 which is configured to generate or detect electromagnetic radiation during operation of the component part 2 (FIG. 1F). The radioactive layer 23 can be a p-n-junction. The main body 2H may have further semiconductor layers which are for example intrinsic, p-doped or n-doped. In particular, the radiation-active layer 23 of the main body 2H is arranged in the vertical direction between a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer is arranged on the n-side and the second semiconductor layer is arranged on the p-side, or vice versa. In particular, the main body 2H forms a diode structure comprising the semiconductor layers and the radiation-active layer 23. The second component part 2 can be an LED.
[0046] The component part 2 may have a contact structure 2K (FIG. 1F) which is arranged in the vertical direction in particular between the main body 2H and the insulation layer 2I. The contact structure 2K is configured in particular for electrically contacting the main body 2H.
[0047] The first component part 1 can be formed analogously to the second component part 2. It is also possible that the first component part 1 is formed as a radiation-inactive wafer carrier. The main body 1H can be free of a radiation-active layer. The main body 1H can be formed as an etch stop layer and/or as a starting layer for electroplating further layers on the main body 1H. The carrier 1T can be a Si wafer. The first component part 1 can have a contact structure 1K (FIG. 1F) which is arranged in the vertical direction between the first insulation layer 1I and the first main body 1H. The first contact structure 1K and the second contact structure 2K are not shown in FIG. 1A, but may be formed similar to the exemplary embodiments shown in FIGS. 1F, 4A and 4C.
[0048] According to FIG. 1B, a mask M is formed on the insulation layer 1I or 2I. The mask M can be formed from a resist layer, in particular from a photo-structurable resist layer. The mask M has at least one opening MC or a plurality of openings MC. In the opening MC or in the openings MC, a surface 1IF or 2IF of the first insulation layer 1I or of the second insulation layer 2I is exposed in places.
[0049] According to FIG. 1C, the openings 1IC and 2IC of the first or of the second insulation layer 1I or 2I are formed in the areas of the openings MC of the mask M, for example, by applying an etching process. In the openings 1IC or 2IC of the insulation layer 1I or 2I, the contact layers of the contact structure 1K or 2K can be freely accessible in places. At an interface between the mask M and the insulation layer 1I or 2I, the openings 1IC or 2IC can have a larger cross-section than the associated opening MC of the mask M. Along a lateral direction, the mask M may protrude beyond an inner wall of the opening 1IC or 2IC in places and thus partially cover the opening 1IC or 2IC in top view.
[0050] As shown in FIG. 1D, a connecting stack S is applied onto the component part 1 or 2 in layers and in particular in a flat manner over a large area. The connecting stack S may have a first layer S1, a second layer S2 and a layer S3 between the first and second layers. The first layer S1 is in particular a gold layer. The second layer S2 is in particular a tin layer. It is possible that the first layer S1 is a tin layer and that the second layer S2 is a gold layer. The third layer S3 is in particular a barrier layer S3 which is formed from titanium or platinum, for example.
[0051] The connecting stack S is located within the opening 1IC or 2IC of the first or second insulation layer 1I or 2I. In lateral directions, the connecting stack S is in particular completely surrounded by the first insulation layer 1I or by the second insulation layer 2I. As shown in FIG. 1D, there is a lateral intermediate space, in particular between the connecting stack S and the insulation layer 1I or 2I. This intermediate space can completely surround the connecting stack S in lateral directions. The intermediate space is formed for instance in that area of the opening 1IC or 2IC which is covered by the mask M in top view. The intermediate space can be formed since at a common interface between the mask M and the insulation layer 1I or 2I, the opening 1IC or 2IC has a larger lateral cross-section than the opening MC of the mask M. When the connecting stack S is applied, the intermediate space is not covered by the layers S1 to S3 so that the intermediate space is not filled by material of the connecting stack S.
[0052] As shown in FIG. 1E, outside the openings 1IC or 2IC, the mask M and the layers S1 to S3 are removed. A planarization process, especially a chemical-mechanical planarization process (CMP), is suitable for this purpose. The surface 1IF and/or 2IF of the first and/or second insulation layer is/are planarized by this process. In particular, the planarized surface 1IF or 2IF outside the openings 1IC or 2IC has a maximum roughness that is less than 100 nm, 50 nm, 30 nm, 20 nm or less than 10 nm.
[0053] Subsequent to the planarization process, the insulation layer 1I or 2I has a vertical layer thickness T. The vertical layer thickness T corresponds for instance to the total depth T of the opening or of the openings 1IC and/or 2IC. The connecting stack S is located completely within the corresponding opening 1IC or 2IC. In particular, the connecting stack S has an overall height H which is preferably smaller than the overall depth T of the opening or openings 1IC or 2IC. In particular, the total height H and the total depth T differ by at least 2 nm, 5 nm or 10 nm and at most 30 nm, 50 nm, 100 nm or 1 m. As shown in FIG. 1E, the connecting stack H is thus slightly retracted from the planarized surface 1IF or 2IF.
[0054] As shown in FIG. 1F, the component parts 1 and 2 are joined together. In particular, the component parts 1 and 2 are mechanically joined at the common interface G12 of the first insulation layer 1I and of the second insulation layer 2I using a direct bonding process at normal room temperatures. The first component part 1 can be a radiation-inactive carrier wafer. The second component part 2 can be a radiation-active semiconductor wafer. The component part 2 has a main body 2H which in particular comprises a radiation-active layer 23. The first component part 1 can be free of such a radiation-active layer.
[0055] As shown in FIG. 1F, the openings 1IC and 2IC form a common, in particular closed cavity 12K when the component parts 1 and 2 are joined together. The connecting stack S of the first component part 1 and of the connecting stack S of the second component part 2 are arranged in the common cavity 2K. Since the connecting stacks S are each retracted from the planarized surface 1IF or 2IF, there is an intermediate area 12Z or space 12Z in the vertical direction between the connecting stacks S. Due to the presence of the intermediate space 12Z, no electrical connection between component parts 1 and 2 is established, in particular even after the mechanical fixing of the component parts 1 and 2.
[0056] The contact formation, i.e., the formation of the through-via 12, is achieved in particular by melting the connecting stacks S, especially by melting the solder materials gold and tin. Here, the shape of the respective connecting stack S can change from a cylindrical shape to a drop shape, wherein the height of the respective connecting stack S can exceed the common interface G12, as a result of which a through-via 12 is formed between the first component part 1 and the second component part 2. The through-via 12 thus establishes an electrical connection between the first component part 1 and the second component part 2.
[0057] Depending on the filling quantity and the geometries of the openings 1IC and 2IC, the through-via 12 can have a positive or a negative curvature. Excess solder material can be accommodated in the lateral intermediate space between the through-via 12 and the inner walls of the common cavity 12K. The intermediate space can be formed, inter alia, by removing the material of the insulation layer/s 1I and/or 2I. Thus, no force can be exerted on the planar bond connection, in particular on the direct bond connection, during the formation of the through-via 12 which could lead to a detachment of the insulation layers 1I and 2I.
[0058] FIG. 1G schematically shows an assembly 10 made of component parts 1 and 2 or a component 10 or 10B made of component parts 1 and 2. The through-via 12 electrically connecting the component parts 1 and 2 is formed in particular by melting the connecting stack S or the connecting stacks S. As shown in FIG. 1G, even after the formation of the through-via 12, there is still an intermediate space in the lateral direction between the through-via 12 and the insulation layers 1I and 2I. In particular, the through-via 12 is a one-piece construction. In particular, the through-via 12 is formed from a gold-tin eutectic. The gold-tin eutectic may contain traces of materials of the barrier layer S3 or of a protective layer. In particular, the through-via 12 may contain traces of other metals such as copper, nickel, titanium or aluminum.
[0059] The exemplary embodiment of an assembly 10 or of a component 10 made of the component parts 1 and 2 shown in FIG. 2A is essentially the same as the exemplary embodiment of an assembly 10 or a component 10 or 10B shown in FIG. 1G. In contrast, FIG. 2A shows a plurality of through-vias 12, wherein each of the through-via 12 is formed in a common cavity 12K. In the lateral directions, the through-vias 12 are spatially separated from each other. The through-vias 12 are completely enclosed in lateral directions by the first insulation layer 1I and/or by the second insulation layer 2I.
[0060] As shown in FIG. 2A, the through-via 12 only partially fills its associated cavity 12K. In particular, there are intermediate spaces between the through-via 12 and the inner walls of the cavity 12K. The intermediate spaces can be filled with a gaseous medium such as air. The through-via 12 can have a drop shape in places. The through-via 12 has side surfaces that can have a positive curvature some areas and/or a negative curvature in other areas. The through-via 12 can have the shape of a hyperboloid. In sectional view, the through-via 12 can be cylindrical in shape comprising side surfaces having either positive or negative curvature. The through-vias 12 can be assigned to the same electrical polarity of the component 10 or 10B or different electrical polarities of the component 10 or 10B.
[0061] As shown in FIGS. 1G and 2A, the common interface G12 between the insulation layers 1I and 2I is particularly planar. The common interface G12 has openings 12K, especially in the areas of the common cavities. The common interface surface 12 is formed in particular by the overlapping areas of the surfaces 1IF and 2IF of the insulation layers 1I and 2I.
[0062] The exemplary embodiment of an assembly 10 or a component 10 shown in FIG. 2B essentially corresponds to the exemplary embodiment of an assembly 10 or a component 10 made of component parts 1 and 2 shown in FIG. 2A. As indicated in FIG. 2B, the assembly 10 can be separated from component parts 1 and 2 into a plurality of smaller components 10B. For example, the assembly 10 is separated into a plurality of individual components 10B at the separation lines TB. The individual component 10B is thus a subset of the assembly 10. The individual component 10B can have a single carrier from the first component part 1 and a single main body, particularly a radiation-active main body, from the component part 2. The carrier is electrically conductively connected to the main body of the individual component 10B via the through-via 12.
[0063] The exemplary embodiment shown in FIG. 3A for a method of establishing a connection between the component parts 1 and 2 essentially corresponds to the exemplary embodiments shown in FIGS. 1F, 1G and 2A. In contrast, the second component part 2 in FIG. 3A is formed as a single component part, for instance as a semiconductor chip 2C. In particular, the semiconductor chip 2C has a main body 2H having a radiation-active layer 23. The first component part 1 is formed in particular as a carrier for the semiconductor chip 2C or for a plurality of semiconductor chips 2C. The semiconductor chips 2C can be applied onto the component part 1 either simultaneously or successively, wherein the mechanical and electrical connection between the component part 1 and the component part 2, which in this case is formed as a semiconductor chip 2C, can be carried out analogously to the exemplary embodiments shown in FIGS. 1F and 1G. This is illustrated, for example, in FIGS. 3B and 3C.
[0064] According to FIG. 3C, the assembly 10 or the component 10 has a common component part 1 and a plurality of second component parts 2. The second component parts 2, which are in particular semiconductor chips 2C, are mechanically contacted side by side on the common component part 1 and electrically connected to it. Each of the component parts 2 can have a second insulation layer 2I. The mechanical connection between the first component part 1 and the second component parts 2 can be established either successively or simultaneously. Via through-vias 12, the electrical connections between the first component part 1 and the second component parts 2 can also be established simultaneously or consecutively. As shown in FIG. 3C, the second component part 2, in particular the semiconductor chips 2C, are arranged side by side on the first component part 1. In particular, the second component parts 2 can be individually electrically contacted via the through-vias 12 and can thus be individually controlled.
[0065] In FIGS. 4A to 4I, further method steps for providing a first component part 1 and/or a second component part 2 are shown schematically in sectional views.
[0066] The exemplary embodiment shown in FIG. 4A essentially corresponds to the exemplary embodiment shown in FIG. 1A, but initially without the insulation layer 1I or 2I. In contrast, FIG. 4A shows the contact structure 1K or 2K in more detail. The contact structure 1K or 2K can have contact layers 41 and 42. The contact layers 41 and 42 are especially configured for electrically contacting the main body 1H or 2H. The contact structure 1K or 2K can have a separating layer 40 which electrically isolates the contact layer 41 from the other contact layer 42.
[0067] The first component part 1 can have a silicon carrier 1T. The second component part 2 can have a carrier 2T, which is a growth substrate, on which the main body 2H, which is in particular a semiconductor body and/or has an LED structure, can be grown epitaxially. For example, the growth substrate is a sapphire substrate. The semiconductor body can be based on gallium nitride. In particular, the semiconductor body has a radiation-active layer, wherein the contact layers 41 and 42 are configured for electrically contacting the semiconductor body.
[0068] According to FIG. 4B, a first layer S1 of the connecting stack S is formed. The first layer S1 can be a gold layer or a tin layer. The first layer S1 can first be applied onto the 1K or 2K contact structure in a widespread and flat manner and then structured such that the first layer S1 only remains in the areas of the contact layers 41 and 42. Alternatively, it is possible to apply the first layer S1 in a structured manner onto the contact layers 41 and 42.
[0069] According to FIG. 4C, the insulation layer 1I or 2I is applied onto the first layer S1 and/or onto the contact structure 1K or 2K. The insulation layer 1I or 2I has a surface 1IF or 2IF facing away from the main body 1H or 2H, which has vertical elevations, especially in the areas of the first layer S1, especially in the form of steps. In top view, the insulation layer 1I or 2I covers the first layer S1 and/or the contact layers 41 and 42 in particular completely.
[0070] According to FIG. 4D, a plurality of openings 1IC or 2IC are formed in the insulation layer 1I or 2I by means of a mask M which is formed in particular from a photo-structurable resist layer. In the openings 1IC and 2IC, the first layer S1 is exposed in places. Before the openings 1IC and 2IC are formed, the insulation layer 1I or 2I can be planarized, for example, using a chemical-mechanical planarization process. The insulation layer 1I or 2I is preferably formed from silicon oxide, especially from silicon dioxide.
[0071] According to FIG. 4E, a barrier layer S3 is formed at least in the areas of the openings 1IC and/or 2IC. The barrier layer S3 can cover, in particular completely cover a bottom surface and inner walls of the openings 1IC or 2IC. The bottom surface of the opening or openings 1IC and 2IC is formed in particular by a surface of the first layer S1. The barrier layer S3 may be directly adjacent to the first layer S1. The barrier layer S3 may be formed of titanium or platinum. For example, the barrier layer S3 has a vertical layer thickness between 1 nm and 30 nm inclusive, for instance between 1 nm and 20 nm, preferably between 1 nm and 10 nm.
[0072] According to FIG. 4F, a second layer S2 of the connecting stack S is formed. In particular, the second layer S2 is applied by a sputtering process onto the insulation layer 1I or 2I and onto the barrier layer S3. For example, a layer thickness of the second layer S2 is chosen such that the second layer S2 only partially fills the openings 1IC or 2IC of the insulation layer 1I or 2I. The second layer S2 is preferably formed of tin or gold. At least in the areas of the openings 1IC and 2IC of the insulation layer 1I or 2I, the barrier layer S3 is located in the vertical direction between the first layer S1 and the second layer S2.
[0073] According to FIG. 4G, outside the openings of the insulation layer 1I or 2I, the second layer S2 is removed.
[0074] After partially removing the second layer S2, a further barrier layer S3 is applied onto the insulation layer 1I or 2I and the second layer S2 as shown in FIG. 4H. In a subsequent method step, a protective layer S4 is applied, in particular in a widespread and flat manner, onto the further barrier layer S3 or onto the insulation layer 1I or 2I. The protective layer S4 can be formed from nickel, copper, aluminum or from a material whose hardness is in particular higher than that of the material of the first layer S1 and/or of the second layer S2. In particular, the protective layer S4 may be made of gold.
[0075] According to FIG. 4I, the insulation layer 1I or 2I is planarized. During this process the protective layer S4 is partially removed. In particular outside the openings 1IC and 2IC, the protective layer S4 is completely removed, thus exposing the insulation layer 1I or 2I. Prior to the planarization process, the protective layer S4 completely fills the opening or the openings 1IC or 2IC. After the planarization process, the openings 1IC or 2IC are only partially filled by the protective layer S4. In other words, the protective layer S4 is slightly retracted from the surface 1IF, 2IF in the areas of the openings of the insulation layer 1I or 2I. For example, the protective layer S4 is retracted from the surface 1IF, 2IF by a distance between 1 nm and 1 m inclusive, preferably between 1 nm and 500 nm, for instance between 1 nm and 100 nm inclusive or between 10 nm and 50 nm inclusive.
[0076] For the direct bonding process and for the formation of the through-via 12, it is crucial that a predetermined distance from the protective layer 4 to the particularly planarized surface 1IF or 2IF is maintained. If the distance is too small or if the protective layer S4, i.e., the connecting stack S, protrudes beyond the surface 1IF or 2IF, direct bonding cannot be reliably carried out. The direct bond connection can also be damaged due to its increase in volume when the connecting stack S is heated. If the distance between the protective layer S4 and the surface 1IF or 2IF is too large, there is a risk that the through-via 12 will not be formed continuously. In general, it is preferable that the distance between the protective layer S4 and the surface 1IF or 2IF be maintained at for instance 30 nm10 nm. The challenge is, among other things, to achieve this distance reliably and reproducibly for all connecting stacks S of the first component part 1 and/or the second component part 2, if possible.
[0077] It has been found that such an exact distance can be set very accurately in a planarization process having protective layer 4. On the other hand, gold and tin are much softer than a material of the protective layer S4, e.g., of nickel, and are therefore not particularly suitable for forming the top layer of the connecting stack S.
[0078] As shown in FIG. 4I, the second layer S2 in the corresponding opening of the insulation layer 1I or 2I is completely enclosed by the barrier layer S3. The barrier layer S3 is located in particular in the vertical direction between the first layer S1 and the second layer S2. In places, the barrier layer S3 is located in the vertical direction between the second layer S2 and the protective layer S4. The barrier layer S3 can thus prevent an early reaction, such as an intermetallic diffusion, between the layers S1 and S2 and/or between the layers S2 and the protective layer S4.
[0079] The exemplary embodiment shown in FIG. 5A essentially corresponds to the exemplary embodiment shown in FIG. 1F, wherein the first component part 1 and the second component part 2 are joined together to produce an assembly 10 or a component 10 or 10B. In particular, a mechanical connection between the component parts 1 and 2 is achieved by a direct bonding process. The openings 1IC and 2IC of the insulation layers 1I and 2I can form a common, in particular sealed cavity 12K. Even after the mechanical connection between the component parts 1 and 2 has been established, there may still be an intermediate space 12Z between the connecting stacks S in the common cavity 12K.
[0080] After the mechanical fixation of the component parts 1 and 2, an annealing step can be carried out, wherein the connecting stacks S are melted to form the through-via 12 or the plurality of through-vias 12. The exemplary embodiment shown in FIG. 5B is essentially the same as the exemplary embodiment shown in FIG. 1G. In particular, the through-via 12 is gold-tin eutectic formed in one piece. The gold-tin eutectic may contain traces of materials of the barrier layer S3 and/or of the protective layer S4. In contrast to the exemplary embodiment shown in FIG. 1G, the through-via 12 can completely fill the common cavity 12K as shown in FIG. 5B.
[0081] The exemplary embodiments shown in FIGS. 6A and 6B essentially correspond to the exemplary embodiments shown in FIGS. 5A and 5B for establishing a mechanical and electrical connection between the component parts 1 and 2. In contrast, FIG. 6A shows that the first insulation layer 1I and the second insulation layer 2I can have steps 3 or jumps 3 at the common interface G12, especially in the areas of the common cavities 12K. Such steps 3 or jumps 3 can be regarded as characteristic features of a so-called hybrid direct bonding process. Such steps 3 or jumps 3 at the common interface G12 can also be seen in particular on the side faces of the through-via 12 or on the side faces of the through-vias 12, as shown for example in FIG. 6B.
[0082] The invention is not restricted to the exemplary embodiments by the description of the invention made with reference to exemplary embodiments. The invention rather comprises any novel feature and any combination of features, including in particular any combination of features in the claims, even if this feature or this combination is not itself explicitly indicated in the claims or exemplary embodiments.
